pdcsata.c revision 1.8
1 /* $NetBSD: pdcsata.c,v 1.8 2006/06/26 17:45:39 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/malloc.h> 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 #include <dev/pci/pciidereg.h> 40 #include <dev/pci/pciidevar.h> 41 #include <dev/ata/atareg.h> 42 #include <dev/ata/satavar.h> 43 #include <dev/ata/satareg.h> 44 45 #define PDC203xx_NCHANNELS 4 46 #define PDC40718_NCHANNELS 4 47 #define PDC20575_NCHANNELS 3 48 49 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 50 51 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 52 #define PDC_ERRMASK 0x00780700 53 54 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 55 static void pdc203xx_setup_channel(struct ata_channel *); 56 static void pdc203xx_irqack(struct ata_channel *); 57 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 58 static void pdc203xx_dma_start(void *,int ,int); 59 static int pdc203xx_dma_finish(void *, int, int, int); 60 static int pdcsata_pci_intr(void *); 61 static void pdcsata_do_reset(struct ata_channel *, int); 62 63 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 64 static void pdc205xx_drv_probe(struct ata_channel *); 65 66 static int pdcsata_match(struct device *, struct cfdata *, void *); 67 static void pdcsata_attach(struct device *, struct device *, void *); 68 69 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 70 pdcsata_match, pdcsata_attach, NULL, NULL); 71 72 static const struct pciide_product_desc pciide_pdcsata_products[] = { 73 { PCI_PRODUCT_PROMISE_PDC20318, 74 0, 75 "Promise PDC20318 SATA150 controller", 76 pdcsata_chip_map, 77 }, 78 { PCI_PRODUCT_PROMISE_PDC20319, 79 0, 80 "Promise PDC20319 SATA150 controller", 81 pdcsata_chip_map, 82 }, 83 { PCI_PRODUCT_PROMISE_PDC20371, 84 0, 85 "Promise PDC20371 SATA150 controller", 86 pdcsata_chip_map, 87 }, 88 { PCI_PRODUCT_PROMISE_PDC20375, 89 0, 90 "Promise PDC20375 SATA150 controller", 91 pdcsata_chip_map, 92 }, 93 { PCI_PRODUCT_PROMISE_PDC20376, 94 0, 95 "Promise PDC20376 SATA150 controller", 96 pdcsata_chip_map, 97 }, 98 { PCI_PRODUCT_PROMISE_PDC20377, 99 0, 100 "Promise PDC20377 SATA150 controller", 101 pdcsata_chip_map, 102 }, 103 { PCI_PRODUCT_PROMISE_PDC20378, 104 0, 105 "Promise PDC20378 SATA150 controller", 106 pdcsata_chip_map, 107 }, 108 { PCI_PRODUCT_PROMISE_PDC20379, 109 0, 110 "Promise PDC20379 SATA150 controller", 111 pdcsata_chip_map, 112 }, 113 { PCI_PRODUCT_PROMISE_PDC40518, 114 0, 115 "Promise PDC40518 SATA 150 controller", 116 pdcsata_chip_map, 117 }, 118 { PCI_PRODUCT_PROMISE_PDC40718, 119 0, 120 "Promise PDC40718 SATA300 controller", 121 pdcsata_chip_map, 122 }, 123 { PCI_PRODUCT_PROMISE_PDC40719, 124 0, 125 "Promise PDC40719 SATA300 controller", 126 pdcsata_chip_map, 127 }, 128 { PCI_PRODUCT_PROMISE_PDC20571, 129 0, 130 "Promise PDC20571 SATA150 controller", 131 pdcsata_chip_map, 132 }, 133 { PCI_PRODUCT_PROMISE_PDC20575, 134 0, 135 "Promise PDC20575 SATA150 controller", 136 pdcsata_chip_map, 137 }, 138 { PCI_PRODUCT_PROMISE_PDC20579, 139 0, 140 "Promise PDC20579 SATA150 controller", 141 pdcsata_chip_map, 142 }, 143 { PCI_PRODUCT_PROMISE_PDC20775, 144 0, 145 "Promise PDC20775 SATA300 controller", 146 pdcsata_chip_map, 147 }, 148 { 0, 149 0, 150 NULL, 151 NULL 152 } 153 }; 154 155 static int 156 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 157 { 158 struct pci_attach_args *pa = aux; 159 160 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 161 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 162 return (2); 163 } 164 return (0); 165 } 166 167 static void 168 pdcsata_attach(struct device *parent, struct device *self, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 struct pciide_softc *sc = (struct pciide_softc *)self; 172 173 pciide_common_attach(sc, pa, 174 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 175 } 176 177 static void 178 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 179 { 180 struct pciide_channel *cp; 181 struct ata_channel *wdc_cp; 182 struct wdc_regs *wdr; 183 int channel, i; 184 bus_size_t dmasize; 185 pci_intr_handle_t intrhandle; 186 const char *intrstr; 187 188 /* 189 * Promise SATA controllers have 3 or 4 channels, 190 * the usual IDE registers are mapped in I/O space, with offsets. 191 */ 192 if (pci_intr_map(pa, &intrhandle) != 0) { 193 aprint_error("%s: couldn't map interrupt\n", 194 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 195 return; 196 } 197 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 198 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 199 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 200 201 if (sc->sc_pci_ih == NULL) { 202 aprint_error("%s: couldn't establish native-PCI interrupt", 203 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 204 if (intrstr != NULL) 205 aprint_normal(" at %s", intrstr); 206 aprint_normal("\n"); 207 return; 208 } 209 aprint_normal("%s: interrupting at %s\n", 210 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 211 intrstr ? intrstr : "unknown interrupt"); 212 213 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 214 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 215 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 216 if (!sc->sc_dma_ok) { 217 aprint_error("%s: couldn't map bus-master DMA registers\n", 218 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 219 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 220 return; 221 } 222 223 sc->sc_dmat = pa->pa_dmat; 224 225 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 226 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 227 &sc->sc_ba5_sh, NULL, NULL) != 0) { 228 aprint_error("%s: couldn't map IDE registers\n", 229 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 230 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 231 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 232 return; 233 } 234 235 aprint_normal("%s: bus-master DMA support present\n", 236 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 237 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 238 if (sc->sc_dma_ok) { 239 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 240 } 241 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 242 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 243 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 244 sc->sc_wdcdev.irqack = pdc203xx_irqack; 245 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 246 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 247 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 248 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 249 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 250 251 sc->sc_wdcdev.reset = pdcsata_do_reset; 252 253 switch (sc->sc_pp->ide_product) { 254 case PCI_PRODUCT_PROMISE_PDC20318: 255 case PCI_PRODUCT_PROMISE_PDC20319: 256 case PCI_PRODUCT_PROMISE_PDC20371: 257 case PCI_PRODUCT_PROMISE_PDC20375: 258 case PCI_PRODUCT_PROMISE_PDC20376: 259 case PCI_PRODUCT_PROMISE_PDC20377: 260 case PCI_PRODUCT_PROMISE_PDC20378: 261 case PCI_PRODUCT_PROMISE_PDC20379: 262 default: 263 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 264 sc->sc_wdcdev.sc_atac.atac_nchannels = 265 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 266 PDC203xx_NCHANNELS : 3; 267 268 break; 269 270 case PCI_PRODUCT_PROMISE_PDC40518: 271 case PCI_PRODUCT_PROMISE_PDC40718: 272 case PCI_PRODUCT_PROMISE_PDC40719: 273 case PCI_PRODUCT_PROMISE_PDC20571: 274 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 275 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 276 277 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 278 279 break; 280 case PCI_PRODUCT_PROMISE_PDC20575: 281 case PCI_PRODUCT_PROMISE_PDC20579: 282 case PCI_PRODUCT_PROMISE_PDC20775: 283 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 284 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS; 285 286 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 287 288 break; 289 } 290 291 wdc_allocate_regs(&sc->sc_wdcdev); 292 293 sc->sc_wdcdev.dma_arg = sc; 294 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 295 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 296 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 297 298 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 299 channel++) { 300 cp = &sc->pciide_channels[channel]; 301 sc->wdc_chanarray[channel] = &cp->ata_channel; 302 303 cp->ih = sc->sc_pci_ih; 304 cp->name = NULL; 305 cp->ata_channel.ch_channel = channel; 306 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 307 cp->ata_channel.ch_queue = 308 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 309 cp->ata_channel.ch_ndrive = 2; 310 if (cp->ata_channel.ch_queue == NULL) { 311 aprint_error("%s channel %d: " 312 "can't allocate memory for command queue\n", 313 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 314 goto next_channel; 315 } 316 wdc_cp = &cp->ata_channel; 317 wdr = CHAN_TO_WDC_REGS(wdc_cp); 318 319 wdr->ctl_iot = sc->sc_ba5_st; 320 wdr->cmd_iot = sc->sc_ba5_st; 321 322 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 323 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 324 aprint_error("%s: couldn't map channel %d ctl regs\n", 325 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 326 channel); 327 goto next_channel; 328 } 329 for (i = 0; i < WDC_NREG; i++) { 330 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 331 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 332 &wdr->cmd_iohs[i]) != 0) { 333 aprint_error("%s: couldn't map channel %d cmd " 334 "regs\n", 335 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 336 channel); 337 goto next_channel; 338 } 339 } 340 wdc_init_shadow_regs(wdc_cp); 341 342 /* 343 * subregion de busmaster registers. They're spread all over 344 * the controller's register space :(. They are also 4 bytes 345 * sized, with some specific extentions in the extra bits. 346 * It also seems that the IDEDMA_CTL register isn't available. 347 */ 348 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 349 0x260 + (channel << 7), 1, 350 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 351 aprint_normal("%s channel %d: can't subregion DMA " 352 "registers\n", 353 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 354 goto next_channel; 355 } 356 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 357 0x244 + (channel << 7), 4, 358 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 359 aprint_normal("%s channel %d: can't subregion DMA " 360 "registers\n", 361 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 362 goto next_channel; 363 } 364 365 wdcattach(wdc_cp); 366 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 367 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 368 0) & ~0x00003f9f) | (channel + 1)); 369 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 370 (channel + 1) << 2, 0x00000001); 371 next_channel: 372 continue; 373 } 374 return; 375 } 376 377 static void 378 pdc203xx_setup_channel(struct ata_channel *chp) 379 { 380 struct ata_drive_datas *drvp; 381 int drive, s; 382 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 383 384 pciide_channel_dma_setup(cp); 385 386 for (drive = 0; drive < 2; drive++) { 387 drvp = &chp->ch_drive[drive]; 388 if ((drvp->drive_flags & DRIVE) == 0) 389 continue; 390 if (drvp->drive_flags & DRIVE_UDMA) { 391 s = splbio(); 392 drvp->drive_flags &= ~DRIVE_DMA; 393 splx(s); 394 } 395 } 396 } 397 398 static int 399 pdcsata_pci_intr(void *arg) 400 { 401 struct pciide_softc *sc = arg; 402 struct pciide_channel *cp; 403 struct ata_channel *wdc_cp; 404 int i, rv, crv; 405 u_int32_t scr, status, chanbase; 406 407 rv = 0; 408 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 409 if (scr == 0xffffffff) return(rv); 410 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 411 scr = scr & 0x0000ffff; 412 if (!scr) return(rv); 413 414 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 415 cp = &sc->pciide_channels[i]; 416 wdc_cp = &cp->ata_channel; 417 if (scr & (1 << (i + 1))) { 418 chanbase = PDC_CHANNELBASE(i) + 0x48; 419 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 420 if (status & PDC_ERRMASK) { 421 chanbase = PDC_CHANNELBASE(i) + 0x60; 422 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 423 status |= 0x800; 424 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 425 status &= ~0x800; 426 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 427 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 428 continue; 429 } 430 crv = wdcintr(wdc_cp); 431 if (crv == 0) { 432 printf("%s:%d: bogus intr (reg 0x%x)\n", 433 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 434 i, scr); 435 } else 436 rv = 1; 437 } 438 } 439 return rv; 440 } 441 442 static void 443 pdc203xx_irqack(struct ata_channel *chp) 444 { 445 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 446 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 447 448 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 449 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 450 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 451 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 452 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 453 } 454 455 static int 456 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 457 size_t datalen, int flags) 458 { 459 struct pciide_softc *sc = v; 460 461 return pciide_dma_dmamap_setup(sc, channel, drive, 462 databuf, datalen, flags); 463 } 464 465 static void 466 pdc203xx_dma_start(void *v, int channel, int drive) 467 { 468 struct pciide_softc *sc = v; 469 struct pciide_channel *cp = &sc->pciide_channels[channel]; 470 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 471 472 /* Write table addr */ 473 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 474 dma_maps->dmamap_table->dm_segs[0].ds_addr); 475 /* start DMA engine */ 476 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 477 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 478 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 479 } 480 481 static int 482 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 483 { 484 struct pciide_softc *sc = v; 485 struct pciide_channel *cp = &sc->pciide_channels[channel]; 486 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 487 488 /* stop DMA channel */ 489 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 490 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 491 0) & ~0x80)); 492 493 /* Unload the map of the data buffer */ 494 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 495 dma_maps->dmamap_xfer->dm_mapsize, 496 (dma_maps->dma_flags & WDC_DMA_READ) ? 497 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 498 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 499 500 return 0; 501 } 502 503 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 504 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 505 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 506 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 507 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 508 509 510 #define SCONTROL_WRITE(sc,channel,scontrol) \ 511 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 512 PDC205_SCONTROL(channel), scontrol) 513 514 #define SSTATUS_READ(sc,channel) \ 515 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 516 PDC205_SSTATUS(channel)) 517 518 519 520 static void 521 pdcsata_do_reset(struct ata_channel *chp, int poll) 522 { 523 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 524 int reset, status, i, chanbase; 525 526 /* reset SATA */ 527 reset = (1 << 11); 528 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 529 for (i = 0; i < 11;i ++) { 530 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 531 if (status & reset) break; 532 delay(100); 533 status |= reset; 534 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 535 } 536 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 537 status &= ~reset; 538 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 539 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 540 541 wdc_do_reset(chp, poll); 542 543 } 544 545 static void 546 pdc205xx_drv_probe(struct ata_channel *chp) 547 { 548 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 549 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 550 u_int32_t scontrol, sstatus; 551 u_int16_t scnt, sn, cl, ch; 552 int i, s; 553 554 /* XXX This should be done by other code. */ 555 for (i = 0; i < 2; i++) { 556 chp->ch_drive[i].chnl_softc = chp; 557 chp->ch_drive[i].drive = i; 558 } 559 560 SCONTROL_WRITE(sc, chp->ch_channel, 0); 561 delay(50*1000); 562 563 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 564 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 565 delay(50*1000); 566 567 scontrol &= ~SControl_DET_INIT; 568 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 569 delay(50*1000); 570 571 sstatus = SSTATUS_READ(sc,chp->ch_channel); 572 573 switch (sstatus & SStatus_DET_mask) { 574 case SStatus_DET_NODEV: 575 /* No Device; be silent. */ 576 break; 577 578 case SStatus_DET_DEV_NE: 579 aprint_error("%s: port %d: device connected, but " 580 "communication not established\n", 581 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 582 break; 583 584 case SStatus_DET_OFFLINE: 585 aprint_error("%s: port %d: PHY offline\n", 586 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 587 break; 588 589 case SStatus_DET_DEV: 590 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 591 WDSD_IBM); 592 delay(10); /* 400ns delay */ 593 scnt = bus_space_read_2(wdr->cmd_iot, 594 wdr->cmd_iohs[wd_seccnt], 0); 595 sn = bus_space_read_2(wdr->cmd_iot, 596 wdr->cmd_iohs[wd_sector], 0); 597 cl = bus_space_read_2(wdr->cmd_iot, 598 wdr->cmd_iohs[wd_cyl_lo], 0); 599 ch = bus_space_read_2(wdr->cmd_iot, 600 wdr->cmd_iohs[wd_cyl_hi], 0); 601 #if 0 602 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 603 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 604 scnt, sn, cl, ch); 605 #endif 606 /* 607 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 608 * cases we get wrong values here, so ignore it. 609 */ 610 s = splbio(); 611 if (cl == 0x14 && ch == 0xeb) 612 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 613 else 614 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 615 splx(s); 616 #if 0 617 aprint_normal("%s: port %d: device present, speed: %s\n", 618 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 619 sata_speed(sstatus)); 620 #endif 621 break; 622 623 default: 624 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 625 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 626 sstatus); 627 } 628 } 629
Indexes created Mon Sep 29 21:09:56 GMT 2025