pdcsata.c revision 1.9
1 /* $NetBSD: pdcsata.c,v 1.9 2006/06/26 17:54:06 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 2004, Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: pdcsata.c,v 1.9 2006/06/26 17:54:06 xtraeme Exp $"); 34 35 #include <sys/types.h> 36 #include <sys/malloc.h> 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciidereg.h> 43 #include <dev/pci/pciidevar.h> 44 #include <dev/ata/atareg.h> 45 #include <dev/ata/satavar.h> 46 #include <dev/ata/satareg.h> 47 48 #define PDC203xx_NCHANNELS 4 49 #define PDC40718_NCHANNELS 4 50 #define PDC20575_NCHANNELS 3 51 52 #define PDC203xx_BAR_IDEREGS 0x1c /* BAR where the IDE registers are mapped */ 53 54 #define PDC_CHANNELBASE(ch) 0x200 + ((ch) * 0x80) 55 #define PDC_ERRMASK 0x00780700 56 57 static void pdcsata_chip_map(struct pciide_softc *, struct pci_attach_args *); 58 static void pdc203xx_setup_channel(struct ata_channel *); 59 static void pdc203xx_irqack(struct ata_channel *); 60 static int pdc203xx_dma_init(void *, int, int, void *, size_t, int); 61 static void pdc203xx_dma_start(void *,int ,int); 62 static int pdc203xx_dma_finish(void *, int, int, int); 63 static int pdcsata_pci_intr(void *); 64 static void pdcsata_do_reset(struct ata_channel *, int); 65 66 /* PDC205xx, PDC405xx and PDC407xx. but tested only pdc40718 */ 67 static void pdc205xx_drv_probe(struct ata_channel *); 68 69 static int pdcsata_match(struct device *, struct cfdata *, void *); 70 static void pdcsata_attach(struct device *, struct device *, void *); 71 72 CFATTACH_DECL(pdcsata, sizeof(struct pciide_softc), 73 pdcsata_match, pdcsata_attach, NULL, NULL); 74 75 static const struct pciide_product_desc pciide_pdcsata_products[] = { 76 { PCI_PRODUCT_PROMISE_PDC20318, 77 0, 78 "Promise PDC20318 SATA150 controller", 79 pdcsata_chip_map, 80 }, 81 { PCI_PRODUCT_PROMISE_PDC20319, 82 0, 83 "Promise PDC20319 SATA150 controller", 84 pdcsata_chip_map, 85 }, 86 { PCI_PRODUCT_PROMISE_PDC20371, 87 0, 88 "Promise PDC20371 SATA150 controller", 89 pdcsata_chip_map, 90 }, 91 { PCI_PRODUCT_PROMISE_PDC20375, 92 0, 93 "Promise PDC20375 SATA150 controller", 94 pdcsata_chip_map, 95 }, 96 { PCI_PRODUCT_PROMISE_PDC20376, 97 0, 98 "Promise PDC20376 SATA150 controller", 99 pdcsata_chip_map, 100 }, 101 { PCI_PRODUCT_PROMISE_PDC20377, 102 0, 103 "Promise PDC20377 SATA150 controller", 104 pdcsata_chip_map, 105 }, 106 { PCI_PRODUCT_PROMISE_PDC20378, 107 0, 108 "Promise PDC20378 SATA150 controller", 109 pdcsata_chip_map, 110 }, 111 { PCI_PRODUCT_PROMISE_PDC20379, 112 0, 113 "Promise PDC20379 SATA150 controller", 114 pdcsata_chip_map, 115 }, 116 { PCI_PRODUCT_PROMISE_PDC40518, 117 0, 118 "Promise PDC40518 SATA 150 controller", 119 pdcsata_chip_map, 120 }, 121 { PCI_PRODUCT_PROMISE_PDC40718, 122 0, 123 "Promise PDC40718 SATA300 controller", 124 pdcsata_chip_map, 125 }, 126 { PCI_PRODUCT_PROMISE_PDC40719, 127 0, 128 "Promise PDC40719 SATA300 controller", 129 pdcsata_chip_map, 130 }, 131 { PCI_PRODUCT_PROMISE_PDC20571, 132 0, 133 "Promise PDC20571 SATA150 controller", 134 pdcsata_chip_map, 135 }, 136 { PCI_PRODUCT_PROMISE_PDC20575, 137 0, 138 "Promise PDC20575 SATA150 controller", 139 pdcsata_chip_map, 140 }, 141 { PCI_PRODUCT_PROMISE_PDC20579, 142 0, 143 "Promise PDC20579 SATA150 controller", 144 pdcsata_chip_map, 145 }, 146 { PCI_PRODUCT_PROMISE_PDC20775, 147 0, 148 "Promise PDC20775 SATA300 controller", 149 pdcsata_chip_map, 150 }, 151 { 0, 152 0, 153 NULL, 154 NULL 155 } 156 }; 157 158 static int 159 pdcsata_match(struct device *parent, struct cfdata *match, void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 163 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_PROMISE) { 164 if (pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)) 165 return (2); 166 } 167 return (0); 168 } 169 170 static void 171 pdcsata_attach(struct device *parent, struct device *self, void *aux) 172 { 173 struct pci_attach_args *pa = aux; 174 struct pciide_softc *sc = (struct pciide_softc *)self; 175 176 pciide_common_attach(sc, pa, 177 pciide_lookup_product(pa->pa_id, pciide_pdcsata_products)); 178 } 179 180 static void 181 pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 182 { 183 struct pciide_channel *cp; 184 struct ata_channel *wdc_cp; 185 struct wdc_regs *wdr; 186 int channel, i; 187 bus_size_t dmasize; 188 pci_intr_handle_t intrhandle; 189 const char *intrstr; 190 191 /* 192 * Promise SATA controllers have 3 or 4 channels, 193 * the usual IDE registers are mapped in I/O space, with offsets. 194 */ 195 if (pci_intr_map(pa, &intrhandle) != 0) { 196 aprint_error("%s: couldn't map interrupt\n", 197 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 198 return; 199 } 200 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 201 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 202 intrhandle, IPL_BIO, pdcsata_pci_intr, sc); 203 204 if (sc->sc_pci_ih == NULL) { 205 aprint_error("%s: couldn't establish native-PCI interrupt", 206 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 207 if (intrstr != NULL) 208 aprint_normal(" at %s", intrstr); 209 aprint_normal("\n"); 210 return; 211 } 212 aprint_normal("%s: interrupting at %s\n", 213 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 214 intrstr ? intrstr : "unknown interrupt"); 215 216 sc->sc_dma_ok = (pci_mapreg_map(pa, PCIIDE_REG_BUS_MASTER_DMA, 217 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_dma_iot, 218 &sc->sc_dma_ioh, NULL, &dmasize) == 0); 219 if (!sc->sc_dma_ok) { 220 aprint_error("%s: couldn't map bus-master DMA registers\n", 221 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 222 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 223 return; 224 } 225 226 sc->sc_dmat = pa->pa_dmat; 227 228 if (pci_mapreg_map(pa, PDC203xx_BAR_IDEREGS, 229 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_ba5_st, 230 &sc->sc_ba5_sh, NULL, NULL) != 0) { 231 aprint_error("%s: couldn't map IDE registers\n", 232 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 233 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, dmasize); 234 pci_intr_disestablish(pa->pa_pc, sc->sc_pci_ih); 235 return; 236 } 237 238 aprint_normal("%s: bus-master DMA support present\n", 239 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 240 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 241 if (sc->sc_dma_ok) { 242 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 243 } 244 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 245 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 246 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 247 sc->sc_wdcdev.irqack = pdc203xx_irqack; 248 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 249 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 250 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 251 sc->sc_wdcdev.sc_atac.atac_set_modes = pdc203xx_setup_channel; 252 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 253 254 sc->sc_wdcdev.reset = pdcsata_do_reset; 255 256 switch (sc->sc_pp->ide_product) { 257 case PCI_PRODUCT_PROMISE_PDC20318: 258 case PCI_PRODUCT_PROMISE_PDC20319: 259 case PCI_PRODUCT_PROMISE_PDC20371: 260 case PCI_PRODUCT_PROMISE_PDC20375: 261 case PCI_PRODUCT_PROMISE_PDC20376: 262 case PCI_PRODUCT_PROMISE_PDC20377: 263 case PCI_PRODUCT_PROMISE_PDC20378: 264 case PCI_PRODUCT_PROMISE_PDC20379: 265 default: 266 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x6c, 0x00ff0033); 267 sc->sc_wdcdev.sc_atac.atac_nchannels = 268 (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x48) & 0x02) ? 269 PDC203xx_NCHANNELS : 3; 270 271 break; 272 273 case PCI_PRODUCT_PROMISE_PDC40518: 274 case PCI_PRODUCT_PROMISE_PDC40718: 275 case PCI_PRODUCT_PROMISE_PDC40719: 276 case PCI_PRODUCT_PROMISE_PDC20571: 277 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 278 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC40718_NCHANNELS; 279 280 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 281 282 break; 283 case PCI_PRODUCT_PROMISE_PDC20575: 284 case PCI_PRODUCT_PROMISE_PDC20579: 285 case PCI_PRODUCT_PROMISE_PDC20775: 286 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x60, 0x00ff00ff); 287 sc->sc_wdcdev.sc_atac.atac_nchannels = PDC20575_NCHANNELS; 288 289 sc->sc_wdcdev.sc_atac.atac_probe = pdc205xx_drv_probe; 290 291 break; 292 } 293 294 wdc_allocate_regs(&sc->sc_wdcdev); 295 296 sc->sc_wdcdev.dma_arg = sc; 297 sc->sc_wdcdev.dma_init = pdc203xx_dma_init; 298 sc->sc_wdcdev.dma_start = pdc203xx_dma_start; 299 sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish; 300 301 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 302 channel++) { 303 cp = &sc->pciide_channels[channel]; 304 sc->wdc_chanarray[channel] = &cp->ata_channel; 305 306 cp->ih = sc->sc_pci_ih; 307 cp->name = NULL; 308 cp->ata_channel.ch_channel = channel; 309 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 310 cp->ata_channel.ch_queue = 311 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 312 cp->ata_channel.ch_ndrive = 2; 313 if (cp->ata_channel.ch_queue == NULL) { 314 aprint_error("%s channel %d: " 315 "can't allocate memory for command queue\n", 316 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 317 goto next_channel; 318 } 319 wdc_cp = &cp->ata_channel; 320 wdr = CHAN_TO_WDC_REGS(wdc_cp); 321 322 wdr->ctl_iot = sc->sc_ba5_st; 323 wdr->cmd_iot = sc->sc_ba5_st; 324 325 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 326 0x0238 + (channel << 7), 1, &wdr->ctl_ioh) != 0) { 327 aprint_error("%s: couldn't map channel %d ctl regs\n", 328 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 329 channel); 330 goto next_channel; 331 } 332 for (i = 0; i < WDC_NREG; i++) { 333 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 334 0x0200 + (i << 2) + (channel << 7), i == 0 ? 4 : 1, 335 &wdr->cmd_iohs[i]) != 0) { 336 aprint_error("%s: couldn't map channel %d cmd " 337 "regs\n", 338 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 339 channel); 340 goto next_channel; 341 } 342 } 343 wdc_init_shadow_regs(wdc_cp); 344 345 /* 346 * subregion de busmaster registers. They're spread all over 347 * the controller's register space :(. They are also 4 bytes 348 * sized, with some specific extentions in the extra bits. 349 * It also seems that the IDEDMA_CTL register isn't available. 350 */ 351 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 352 0x260 + (channel << 7), 1, 353 &cp->dma_iohs[IDEDMA_CMD]) != 0) { 354 aprint_normal("%s channel %d: can't subregion DMA " 355 "registers\n", 356 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 357 goto next_channel; 358 } 359 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 360 0x244 + (channel << 7), 4, 361 &cp->dma_iohs[IDEDMA_TBL]) != 0) { 362 aprint_normal("%s channel %d: can't subregion DMA " 363 "registers\n", 364 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel); 365 goto next_channel; 366 } 367 368 wdcattach(wdc_cp); 369 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 370 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 371 0) & ~0x00003f9f) | (channel + 1)); 372 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 373 (channel + 1) << 2, 0x00000001); 374 next_channel: 375 continue; 376 } 377 return; 378 } 379 380 static void 381 pdc203xx_setup_channel(struct ata_channel *chp) 382 { 383 struct ata_drive_datas *drvp; 384 int drive, s; 385 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 386 387 pciide_channel_dma_setup(cp); 388 389 for (drive = 0; drive < 2; drive++) { 390 drvp = &chp->ch_drive[drive]; 391 if ((drvp->drive_flags & DRIVE) == 0) 392 continue; 393 if (drvp->drive_flags & DRIVE_UDMA) { 394 s = splbio(); 395 drvp->drive_flags &= ~DRIVE_DMA; 396 splx(s); 397 } 398 } 399 } 400 401 static int 402 pdcsata_pci_intr(void *arg) 403 { 404 struct pciide_softc *sc = arg; 405 struct pciide_channel *cp; 406 struct ata_channel *wdc_cp; 407 int i, rv, crv; 408 u_int32_t scr, status, chanbase; 409 410 rv = 0; 411 scr = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40); 412 if (scr == 0xffffffff) return(rv); 413 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 0x40, scr & 0x0000ffff); 414 scr = scr & 0x0000ffff; 415 if (!scr) return(rv); 416 417 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 418 cp = &sc->pciide_channels[i]; 419 wdc_cp = &cp->ata_channel; 420 if (scr & (1 << (i + 1))) { 421 chanbase = PDC_CHANNELBASE(i) + 0x48; 422 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 423 if (status & PDC_ERRMASK) { 424 chanbase = PDC_CHANNELBASE(i) + 0x60; 425 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 426 status |= 0x800; 427 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 428 status &= ~0x800; 429 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 430 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 431 continue; 432 } 433 crv = wdcintr(wdc_cp); 434 if (crv == 0) { 435 printf("%s:%d: bogus intr (reg 0x%x)\n", 436 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 437 i, scr); 438 } else 439 rv = 1; 440 } 441 } 442 return rv; 443 } 444 445 static void 446 pdc203xx_irqack(struct ata_channel *chp) 447 { 448 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 449 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 450 451 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 452 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 453 0) & ~0x00003f9f) | (cp->ata_channel.ch_channel + 1)); 454 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 455 (cp->ata_channel.ch_channel + 1) << 2, 0x00000001); 456 } 457 458 static int 459 pdc203xx_dma_init(void *v, int channel, int drive, void *databuf, 460 size_t datalen, int flags) 461 { 462 struct pciide_softc *sc = v; 463 464 return pciide_dma_dmamap_setup(sc, channel, drive, 465 databuf, datalen, flags); 466 } 467 468 static void 469 pdc203xx_dma_start(void *v, int channel, int drive) 470 { 471 struct pciide_softc *sc = v; 472 struct pciide_channel *cp = &sc->pciide_channels[channel]; 473 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 474 475 /* Write table addr */ 476 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 477 dma_maps->dmamap_table->dm_segs[0].ds_addr); 478 /* start DMA engine */ 479 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 480 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 481 0) & ~0xc0) | ((dma_maps->dma_flags & WDC_DMA_READ) ? 0x80 : 0xc0)); 482 } 483 484 static int 485 pdc203xx_dma_finish(void *v, int channel, int drive, int force) 486 { 487 struct pciide_softc *sc = v; 488 struct pciide_channel *cp = &sc->pciide_channels[channel]; 489 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 490 491 /* stop DMA channel */ 492 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 493 (bus_space_read_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 494 0) & ~0x80)); 495 496 /* Unload the map of the data buffer */ 497 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 498 dma_maps->dmamap_xfer->dm_mapsize, 499 (dma_maps->dma_flags & WDC_DMA_READ) ? 500 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 501 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 502 503 return 0; 504 } 505 506 #define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 507 #define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 508 #define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 509 #define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 510 #define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 511 512 513 #define SCONTROL_WRITE(sc,channel,scontrol) \ 514 bus_space_write_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 515 PDC205_SCONTROL(channel), scontrol) 516 517 #define SSTATUS_READ(sc,channel) \ 518 bus_space_read_4((sc)->sc_ba5_st, (sc)->sc_ba5_sh, \ 519 PDC205_SSTATUS(channel)) 520 521 522 523 static void 524 pdcsata_do_reset(struct ata_channel *chp, int poll) 525 { 526 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 527 int reset, status, i, chanbase; 528 529 /* reset SATA */ 530 reset = (1 << 11); 531 chanbase = PDC_CHANNELBASE(chp->ch_channel) + 0x60; 532 for (i = 0; i < 11;i ++) { 533 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 534 if (status & reset) break; 535 delay(100); 536 status |= reset; 537 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 538 } 539 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 540 status &= ~reset; 541 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase, status); 542 status = bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, chanbase); 543 544 wdc_do_reset(chp, poll); 545 546 } 547 548 static void 549 pdc205xx_drv_probe(struct ata_channel *chp) 550 { 551 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 552 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 553 u_int32_t scontrol, sstatus; 554 u_int16_t scnt, sn, cl, ch; 555 int i, s; 556 557 /* XXX This should be done by other code. */ 558 for (i = 0; i < 2; i++) { 559 chp->ch_drive[i].chnl_softc = chp; 560 chp->ch_drive[i].drive = i; 561 } 562 563 SCONTROL_WRITE(sc, chp->ch_channel, 0); 564 delay(50*1000); 565 566 scontrol = SControl_DET_INIT | SControl_SPD_ANY | SControl_IPM_NONE; 567 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 568 delay(50*1000); 569 570 scontrol &= ~SControl_DET_INIT; 571 SCONTROL_WRITE(sc,chp->ch_channel,scontrol); 572 delay(50*1000); 573 574 sstatus = SSTATUS_READ(sc,chp->ch_channel); 575 576 switch (sstatus & SStatus_DET_mask) { 577 case SStatus_DET_NODEV: 578 /* No Device; be silent. */ 579 break; 580 581 case SStatus_DET_DEV_NE: 582 aprint_error("%s: port %d: device connected, but " 583 "communication not established\n", 584 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 585 break; 586 587 case SStatus_DET_OFFLINE: 588 aprint_error("%s: port %d: PHY offline\n", 589 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 590 break; 591 592 case SStatus_DET_DEV: 593 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 594 WDSD_IBM); 595 delay(10); /* 400ns delay */ 596 scnt = bus_space_read_2(wdr->cmd_iot, 597 wdr->cmd_iohs[wd_seccnt], 0); 598 sn = bus_space_read_2(wdr->cmd_iot, 599 wdr->cmd_iohs[wd_sector], 0); 600 cl = bus_space_read_2(wdr->cmd_iot, 601 wdr->cmd_iohs[wd_cyl_lo], 0); 602 ch = bus_space_read_2(wdr->cmd_iot, 603 wdr->cmd_iohs[wd_cyl_hi], 0); 604 #if 0 605 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 606 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 607 scnt, sn, cl, ch); 608 #endif 609 /* 610 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 611 * cases we get wrong values here, so ignore it. 612 */ 613 s = splbio(); 614 if (cl == 0x14 && ch == 0xeb) 615 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 616 else 617 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 618 splx(s); 619 #if 0 620 aprint_normal("%s: port %d: device present, speed: %s\n", 621 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 622 sata_speed(sstatus)); 623 #endif 624 break; 625 626 default: 627 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 628 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 629 sstatus); 630 } 631 } 632
Indexes created Mon Sep 29 21:09:56 GMT 2025