piixide.c revision 1.19.2.4 1 1.19.2.4 tron /* $NetBSD: piixide.c,v 1.19.2.4 2005/08/24 21:51:26 tron Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*
4 1.1 bouyer * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 1.1 bouyer *
6 1.1 bouyer * Redistribution and use in source and binary forms, with or without
7 1.1 bouyer * modification, are permitted provided that the following conditions
8 1.1 bouyer * are met:
9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.1 bouyer * notice, this list of conditions and the following disclaimer.
11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.1 bouyer * documentation and/or other materials provided with the distribution.
14 1.1 bouyer * 3. All advertising materials mentioning features or use of this software
15 1.1 bouyer * must display the following acknowledgement:
16 1.1 bouyer * This product includes software developed by Manuel Bouyer.
17 1.1 bouyer * 4. The name of the author may not be used to endorse or promote products
18 1.1 bouyer * derived from this software without specific prior written permission.
19 1.1 bouyer *
20 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.19 perry * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 bouyer */
31 1.1 bouyer
32 1.1 bouyer #include <sys/param.h>
33 1.1 bouyer #include <sys/systm.h>
34 1.1 bouyer
35 1.1 bouyer #include <dev/pci/pcivar.h>
36 1.1 bouyer #include <dev/pci/pcidevs.h>
37 1.1 bouyer #include <dev/pci/pciidereg.h>
38 1.1 bouyer #include <dev/pci/pciidevar.h>
39 1.1 bouyer #include <dev/pci/pciide_piix_reg.h>
40 1.1 bouyer
41 1.2 thorpej static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *);
42 1.12 thorpej static void piix_setup_channel(struct ata_channel *);
43 1.12 thorpej static void piix3_4_setup_channel(struct ata_channel *);
44 1.2 thorpej static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t);
45 1.2 thorpej static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *);
46 1.2 thorpej static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t);
47 1.5 bouyer static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *);
48 1.2 thorpej
49 1.18 jmcneill static void piixide_powerhook(int, void *);
50 1.2 thorpej static int piixide_match(struct device *, struct cfdata *, void *);
51 1.2 thorpej static void piixide_attach(struct device *, struct device *, void *);
52 1.1 bouyer
53 1.2 thorpej static const struct pciide_product_desc pciide_intel_products[] = {
54 1.1 bouyer { PCI_PRODUCT_INTEL_82092AA,
55 1.1 bouyer 0,
56 1.1 bouyer "Intel 82092AA IDE controller",
57 1.1 bouyer default_chip_map,
58 1.1 bouyer },
59 1.1 bouyer { PCI_PRODUCT_INTEL_82371FB_IDE,
60 1.1 bouyer 0,
61 1.1 bouyer "Intel 82371FB IDE controller (PIIX)",
62 1.1 bouyer piix_chip_map,
63 1.1 bouyer },
64 1.1 bouyer { PCI_PRODUCT_INTEL_82371SB_IDE,
65 1.1 bouyer 0,
66 1.1 bouyer "Intel 82371SB IDE Interface (PIIX3)",
67 1.1 bouyer piix_chip_map,
68 1.1 bouyer },
69 1.1 bouyer { PCI_PRODUCT_INTEL_82371AB_IDE,
70 1.1 bouyer 0,
71 1.1 bouyer "Intel 82371AB IDE controller (PIIX4)",
72 1.1 bouyer piix_chip_map,
73 1.1 bouyer },
74 1.1 bouyer { PCI_PRODUCT_INTEL_82440MX_IDE,
75 1.1 bouyer 0,
76 1.1 bouyer "Intel 82440MX IDE controller",
77 1.1 bouyer piix_chip_map
78 1.1 bouyer },
79 1.1 bouyer { PCI_PRODUCT_INTEL_82801AA_IDE,
80 1.1 bouyer 0,
81 1.1 bouyer "Intel 82801AA IDE Controller (ICH)",
82 1.1 bouyer piix_chip_map,
83 1.1 bouyer },
84 1.1 bouyer { PCI_PRODUCT_INTEL_82801AB_IDE,
85 1.1 bouyer 0,
86 1.1 bouyer "Intel 82801AB IDE Controller (ICH0)",
87 1.1 bouyer piix_chip_map,
88 1.1 bouyer },
89 1.1 bouyer { PCI_PRODUCT_INTEL_82801BA_IDE,
90 1.1 bouyer 0,
91 1.1 bouyer "Intel 82801BA IDE Controller (ICH2)",
92 1.1 bouyer piix_chip_map,
93 1.1 bouyer },
94 1.1 bouyer { PCI_PRODUCT_INTEL_82801BAM_IDE,
95 1.1 bouyer 0,
96 1.1 bouyer "Intel 82801BAM IDE Controller (ICH2-M)",
97 1.1 bouyer piix_chip_map,
98 1.1 bouyer },
99 1.1 bouyer { PCI_PRODUCT_INTEL_82801CA_IDE_1,
100 1.1 bouyer 0,
101 1.1 bouyer "Intel 82801CA IDE Controller (ICH3)",
102 1.1 bouyer piix_chip_map,
103 1.1 bouyer },
104 1.1 bouyer { PCI_PRODUCT_INTEL_82801CA_IDE_2,
105 1.1 bouyer 0,
106 1.1 bouyer "Intel 82801CA IDE Controller (ICH3)",
107 1.1 bouyer piix_chip_map,
108 1.1 bouyer },
109 1.1 bouyer { PCI_PRODUCT_INTEL_82801DB_IDE,
110 1.1 bouyer 0,
111 1.1 bouyer "Intel 82801DB IDE Controller (ICH4)",
112 1.1 bouyer piix_chip_map,
113 1.1 bouyer },
114 1.1 bouyer { PCI_PRODUCT_INTEL_82801DBM_IDE,
115 1.1 bouyer 0,
116 1.1 bouyer "Intel 82801DBM IDE Controller (ICH4-M)",
117 1.1 bouyer piix_chip_map,
118 1.1 bouyer },
119 1.1 bouyer { PCI_PRODUCT_INTEL_82801EB_IDE,
120 1.1 bouyer 0,
121 1.1 bouyer "Intel 82801EB IDE Controller (ICH5)",
122 1.1 bouyer piix_chip_map,
123 1.1 bouyer },
124 1.1 bouyer { PCI_PRODUCT_INTEL_82801EB_SATA,
125 1.1 bouyer 0,
126 1.1 bouyer "Intel 82801EB Serial ATA Controller",
127 1.5 bouyer piixsata_chip_map,
128 1.4 bouyer },
129 1.4 bouyer { PCI_PRODUCT_INTEL_82801ER_SATA,
130 1.4 bouyer 0,
131 1.4 bouyer "Intel 82801ER Serial ATA/Raid Controller",
132 1.5 bouyer piixsata_chip_map,
133 1.1 bouyer },
134 1.9 thorpej { PCI_PRODUCT_INTEL_6300ESB_IDE,
135 1.9 thorpej 0,
136 1.9 thorpej "Intel 6300ESB IDE Controller (ICH5)",
137 1.9 thorpej piix_chip_map,
138 1.9 thorpej },
139 1.9 thorpej { PCI_PRODUCT_INTEL_6300ESB_SATA,
140 1.9 thorpej 0,
141 1.9 thorpej "Intel 6300ESB Serial ATA Controller",
142 1.9 thorpej piixsata_chip_map,
143 1.9 thorpej },
144 1.19.2.2 tron { PCI_PRODUCT_INTEL_6300ESB_RAID,
145 1.19.2.2 tron 0,
146 1.19.2.2 tron "Intel 6300ESB Serial ATA/RAID Controller",
147 1.19.2.2 tron piixsata_chip_map,
148 1.19.2.2 tron },
149 1.17 cube { PCI_PRODUCT_INTEL_82801FB_IDE,
150 1.17 cube 0,
151 1.17 cube "Intel 82801FB IDE Controller (ICH6)",
152 1.17 cube piix_chip_map,
153 1.17 cube },
154 1.16 cube { PCI_PRODUCT_INTEL_82801FB_SATA,
155 1.16 cube 0,
156 1.16 cube "Intel 82801FB Serial ATA/Raid Controller",
157 1.16 cube piixsata_chip_map,
158 1.16 cube },
159 1.16 cube { PCI_PRODUCT_INTEL_82801FR_SATA,
160 1.16 cube 0,
161 1.16 cube "Intel 82801FR Serial ATA/Raid Controller",
162 1.16 cube piixsata_chip_map,
163 1.16 cube },
164 1.19.2.1 tron { PCI_PRODUCT_INTEL_82801FBM_SATA,
165 1.19.2.1 tron 0,
166 1.19.2.1 tron "Intel 82801FBM Serial ATA Controller (ICH6)",
167 1.19.2.1 tron piixsata_chip_map,
168 1.19.2.1 tron },
169 1.19.2.3 riz { PCI_PRODUCT_INTEL_82801G_IDE,
170 1.19.2.3 riz 0,
171 1.19.2.3 riz "Intel 82801GB/GR IDE Controller (ICH7)",
172 1.19.2.3 riz piix_chip_map,
173 1.19.2.3 riz },
174 1.19.2.3 riz { PCI_PRODUCT_INTEL_82801G_SATA,
175 1.19.2.3 riz 0,
176 1.19.2.3 riz "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)",
177 1.19.2.3 riz piixsata_chip_map,
178 1.19.2.3 riz },
179 1.1 bouyer { 0,
180 1.1 bouyer 0,
181 1.1 bouyer NULL,
182 1.1 bouyer NULL
183 1.1 bouyer }
184 1.1 bouyer };
185 1.1 bouyer
186 1.1 bouyer CFATTACH_DECL(piixide, sizeof(struct pciide_softc),
187 1.1 bouyer piixide_match, piixide_attach, NULL, NULL);
188 1.1 bouyer
189 1.2 thorpej static int
190 1.2 thorpej piixide_match(struct device *parent, struct cfdata *match, void *aux)
191 1.1 bouyer {
192 1.1 bouyer struct pci_attach_args *pa = aux;
193 1.1 bouyer
194 1.1 bouyer if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
195 1.1 bouyer if (pciide_lookup_product(pa->pa_id, pciide_intel_products))
196 1.1 bouyer return (2);
197 1.1 bouyer }
198 1.1 bouyer return (0);
199 1.1 bouyer }
200 1.1 bouyer
201 1.2 thorpej static void
202 1.2 thorpej piixide_attach(struct device *parent, struct device *self, void *aux)
203 1.1 bouyer {
204 1.1 bouyer struct pci_attach_args *pa = aux;
205 1.1 bouyer struct pciide_softc *sc = (struct pciide_softc *)self;
206 1.1 bouyer
207 1.1 bouyer pciide_common_attach(sc, pa,
208 1.1 bouyer pciide_lookup_product(pa->pa_id, pciide_intel_products));
209 1.1 bouyer
210 1.18 jmcneill /* Setup our powerhook */
211 1.18 jmcneill sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc);
212 1.18 jmcneill if (sc->sc_powerhook == NULL)
213 1.18 jmcneill printf("%s: WARNING: unable to establish PCI power hook\n",
214 1.18 jmcneill sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
215 1.18 jmcneill }
216 1.18 jmcneill
217 1.18 jmcneill static void
218 1.18 jmcneill piixide_powerhook(int why, void *hdl)
219 1.18 jmcneill {
220 1.18 jmcneill struct pciide_softc *sc = (struct pciide_softc *)hdl;
221 1.18 jmcneill
222 1.18 jmcneill switch (why) {
223 1.18 jmcneill case PWR_SUSPEND:
224 1.18 jmcneill case PWR_STANDBY:
225 1.18 jmcneill pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf);
226 1.18 jmcneill break;
227 1.18 jmcneill case PWR_RESUME:
228 1.18 jmcneill pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf);
229 1.18 jmcneill break;
230 1.18 jmcneill case PWR_SOFTSUSPEND:
231 1.18 jmcneill case PWR_SOFTSTANDBY:
232 1.18 jmcneill case PWR_SOFTRESUME:
233 1.18 jmcneill break;
234 1.18 jmcneill }
235 1.18 jmcneill
236 1.18 jmcneill return;
237 1.1 bouyer }
238 1.1 bouyer
239 1.2 thorpej static void
240 1.2 thorpej piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
241 1.1 bouyer {
242 1.1 bouyer struct pciide_channel *cp;
243 1.1 bouyer int channel;
244 1.1 bouyer u_int32_t idetim;
245 1.1 bouyer bus_size_t cmdsize, ctlsize;
246 1.19.2.4 tron pcireg_t interface = PCI_INTERFACE(pa->pa_class);
247 1.1 bouyer
248 1.1 bouyer if (pciide_chipen(sc, pa) == 0)
249 1.1 bouyer return;
250 1.1 bouyer
251 1.1 bouyer aprint_normal("%s: bus-master DMA support present",
252 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
253 1.1 bouyer pciide_mapreg_dma(sc, pa);
254 1.1 bouyer aprint_normal("\n");
255 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
256 1.1 bouyer if (sc->sc_dma_ok) {
257 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
258 1.1 bouyer sc->sc_wdcdev.irqack = pciide_irqack;
259 1.1 bouyer switch(sc->sc_pp->ide_product) {
260 1.1 bouyer case PCI_PRODUCT_INTEL_82371AB_IDE:
261 1.1 bouyer case PCI_PRODUCT_INTEL_82440MX_IDE:
262 1.1 bouyer case PCI_PRODUCT_INTEL_82801AA_IDE:
263 1.1 bouyer case PCI_PRODUCT_INTEL_82801AB_IDE:
264 1.1 bouyer case PCI_PRODUCT_INTEL_82801BA_IDE:
265 1.1 bouyer case PCI_PRODUCT_INTEL_82801BAM_IDE:
266 1.1 bouyer case PCI_PRODUCT_INTEL_82801CA_IDE_1:
267 1.1 bouyer case PCI_PRODUCT_INTEL_82801CA_IDE_2:
268 1.1 bouyer case PCI_PRODUCT_INTEL_82801DB_IDE:
269 1.1 bouyer case PCI_PRODUCT_INTEL_82801DBM_IDE:
270 1.1 bouyer case PCI_PRODUCT_INTEL_82801EB_IDE:
271 1.9 thorpej case PCI_PRODUCT_INTEL_6300ESB_IDE:
272 1.17 cube case PCI_PRODUCT_INTEL_82801FB_IDE:
273 1.19.2.3 riz case PCI_PRODUCT_INTEL_82801G_IDE:
274 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
275 1.1 bouyer }
276 1.1 bouyer }
277 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
278 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
279 1.1 bouyer switch(sc->sc_pp->ide_product) {
280 1.1 bouyer case PCI_PRODUCT_INTEL_82801AA_IDE:
281 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
282 1.1 bouyer break;
283 1.1 bouyer case PCI_PRODUCT_INTEL_82801BA_IDE:
284 1.1 bouyer case PCI_PRODUCT_INTEL_82801BAM_IDE:
285 1.1 bouyer case PCI_PRODUCT_INTEL_82801CA_IDE_1:
286 1.1 bouyer case PCI_PRODUCT_INTEL_82801CA_IDE_2:
287 1.1 bouyer case PCI_PRODUCT_INTEL_82801DB_IDE:
288 1.1 bouyer case PCI_PRODUCT_INTEL_82801DBM_IDE:
289 1.1 bouyer case PCI_PRODUCT_INTEL_82801EB_IDE:
290 1.9 thorpej case PCI_PRODUCT_INTEL_6300ESB_IDE:
291 1.17 cube case PCI_PRODUCT_INTEL_82801FB_IDE:
292 1.19.2.3 riz case PCI_PRODUCT_INTEL_82801G_IDE:
293 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
294 1.1 bouyer break;
295 1.1 bouyer default:
296 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
297 1.1 bouyer }
298 1.1 bouyer if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE)
299 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel;
300 1.1 bouyer else
301 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel;
302 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
303 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
304 1.1 bouyer
305 1.11 thorpej ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x",
306 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
307 1.1 bouyer DEBUG_PROBE);
308 1.1 bouyer if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
309 1.11 thorpej ATADEBUG_PRINT((", sidetim=0x%x",
310 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
311 1.1 bouyer DEBUG_PROBE);
312 1.14 thorpej if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
313 1.11 thorpej ATADEBUG_PRINT((", udamreg 0x%x",
314 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
315 1.1 bouyer DEBUG_PROBE);
316 1.1 bouyer }
317 1.1 bouyer if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
318 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
319 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
320 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
321 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
322 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
323 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
324 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
325 1.9 thorpej sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
326 1.17 cube sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
327 1.19.2.3 riz sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
328 1.19.2.3 riz sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) {
329 1.11 thorpej ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
330 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
331 1.1 bouyer DEBUG_PROBE);
332 1.1 bouyer }
333 1.1 bouyer
334 1.1 bouyer }
335 1.11 thorpej ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
336 1.1 bouyer
337 1.12 thorpej wdc_allocate_regs(&sc->sc_wdcdev);
338 1.12 thorpej
339 1.14 thorpej for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
340 1.14 thorpej channel++) {
341 1.1 bouyer cp = &sc->pciide_channels[channel];
342 1.19.2.4 tron if (pciide_chansetup(sc, channel, interface) == 0)
343 1.1 bouyer continue;
344 1.1 bouyer idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
345 1.1 bouyer if ((PIIX_IDETIM_READ(idetim, channel) &
346 1.1 bouyer PIIX_IDETIM_IDE) == 0) {
347 1.1 bouyer #if 1
348 1.1 bouyer aprint_normal("%s: %s channel ignored (disabled)\n",
349 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
350 1.12 thorpej cp->ata_channel.ch_flags |= ATACH_DISABLED;
351 1.1 bouyer continue;
352 1.1 bouyer #else
353 1.1 bouyer pcireg_t interface;
354 1.1 bouyer
355 1.1 bouyer idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
356 1.1 bouyer channel);
357 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
358 1.1 bouyer idetim);
359 1.1 bouyer interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
360 1.1 bouyer sc->sc_tag, PCI_CLASS_REG));
361 1.1 bouyer aprint_normal("channel %d idetim=%08x interface=%02x\n",
362 1.1 bouyer channel, idetim, interface);
363 1.1 bouyer #endif
364 1.1 bouyer }
365 1.19.2.4 tron pciide_mapchan(pa, cp, interface,
366 1.19.2.4 tron &cmdsize, &ctlsize, pciide_pci_intr);
367 1.1 bouyer }
368 1.1 bouyer
369 1.11 thorpej ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
370 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
371 1.1 bouyer DEBUG_PROBE);
372 1.1 bouyer if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
373 1.11 thorpej ATADEBUG_PRINT((", sidetim=0x%x",
374 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
375 1.1 bouyer DEBUG_PROBE);
376 1.14 thorpej if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
377 1.11 thorpej ATADEBUG_PRINT((", udamreg 0x%x",
378 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
379 1.1 bouyer DEBUG_PROBE);
380 1.1 bouyer }
381 1.1 bouyer if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
382 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
383 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
384 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
385 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
386 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
387 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
388 1.9 thorpej sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
389 1.9 thorpej sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
390 1.17 cube sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
391 1.19.2.3 riz sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
392 1.19.2.3 riz sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) {
393 1.11 thorpej ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
394 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
395 1.1 bouyer DEBUG_PROBE);
396 1.1 bouyer }
397 1.1 bouyer }
398 1.11 thorpej ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
399 1.1 bouyer }
400 1.1 bouyer
401 1.2 thorpej static void
402 1.12 thorpej piix_setup_channel(struct ata_channel *chp)
403 1.1 bouyer {
404 1.1 bouyer u_int8_t mode[2], drive;
405 1.1 bouyer u_int32_t oidetim, idetim, idedma_ctl;
406 1.13 thorpej struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
407 1.13 thorpej struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
408 1.12 thorpej struct ata_drive_datas *drvp = cp->ata_channel.ch_drive;
409 1.1 bouyer
410 1.1 bouyer oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
411 1.8 thorpej idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel);
412 1.1 bouyer idedma_ctl = 0;
413 1.1 bouyer
414 1.1 bouyer /* set up new idetim: Enable IDE registers decode */
415 1.1 bouyer idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
416 1.8 thorpej chp->ch_channel);
417 1.1 bouyer
418 1.1 bouyer /* setup DMA */
419 1.1 bouyer pciide_channel_dma_setup(cp);
420 1.1 bouyer
421 1.1 bouyer /*
422 1.1 bouyer * Here we have to mess up with drives mode: PIIX can't have
423 1.1 bouyer * different timings for master and slave drives.
424 1.1 bouyer * We need to find the best combination.
425 1.1 bouyer */
426 1.1 bouyer
427 1.1 bouyer /* If both drives supports DMA, take the lower mode */
428 1.1 bouyer if ((drvp[0].drive_flags & DRIVE_DMA) &&
429 1.1 bouyer (drvp[1].drive_flags & DRIVE_DMA)) {
430 1.1 bouyer mode[0] = mode[1] =
431 1.1 bouyer min(drvp[0].DMA_mode, drvp[1].DMA_mode);
432 1.1 bouyer drvp[0].DMA_mode = mode[0];
433 1.1 bouyer drvp[1].DMA_mode = mode[1];
434 1.1 bouyer goto ok;
435 1.1 bouyer }
436 1.1 bouyer /*
437 1.1 bouyer * If only one drive supports DMA, use its mode, and
438 1.1 bouyer * put the other one in PIO mode 0 if mode not compatible
439 1.1 bouyer */
440 1.1 bouyer if (drvp[0].drive_flags & DRIVE_DMA) {
441 1.1 bouyer mode[0] = drvp[0].DMA_mode;
442 1.1 bouyer mode[1] = drvp[1].PIO_mode;
443 1.1 bouyer if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] ||
444 1.1 bouyer piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]])
445 1.1 bouyer mode[1] = drvp[1].PIO_mode = 0;
446 1.1 bouyer goto ok;
447 1.1 bouyer }
448 1.1 bouyer if (drvp[1].drive_flags & DRIVE_DMA) {
449 1.1 bouyer mode[1] = drvp[1].DMA_mode;
450 1.1 bouyer mode[0] = drvp[0].PIO_mode;
451 1.1 bouyer if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] ||
452 1.1 bouyer piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]])
453 1.1 bouyer mode[0] = drvp[0].PIO_mode = 0;
454 1.1 bouyer goto ok;
455 1.1 bouyer }
456 1.1 bouyer /*
457 1.1 bouyer * If both drives are not DMA, takes the lower mode, unless
458 1.1 bouyer * one of them is PIO mode < 2
459 1.1 bouyer */
460 1.1 bouyer if (drvp[0].PIO_mode < 2) {
461 1.1 bouyer mode[0] = drvp[0].PIO_mode = 0;
462 1.1 bouyer mode[1] = drvp[1].PIO_mode;
463 1.1 bouyer } else if (drvp[1].PIO_mode < 2) {
464 1.1 bouyer mode[1] = drvp[1].PIO_mode = 0;
465 1.1 bouyer mode[0] = drvp[0].PIO_mode;
466 1.1 bouyer } else {
467 1.1 bouyer mode[0] = mode[1] =
468 1.1 bouyer min(drvp[1].PIO_mode, drvp[0].PIO_mode);
469 1.1 bouyer drvp[0].PIO_mode = mode[0];
470 1.1 bouyer drvp[1].PIO_mode = mode[1];
471 1.1 bouyer }
472 1.1 bouyer ok: /* The modes are setup */
473 1.1 bouyer for (drive = 0; drive < 2; drive++) {
474 1.1 bouyer if (drvp[drive].drive_flags & DRIVE_DMA) {
475 1.1 bouyer idetim |= piix_setup_idetim_timings(
476 1.8 thorpej mode[drive], 1, chp->ch_channel);
477 1.1 bouyer goto end;
478 1.1 bouyer }
479 1.1 bouyer }
480 1.1 bouyer /* If we are there, none of the drives are DMA */
481 1.1 bouyer if (mode[0] >= 2)
482 1.1 bouyer idetim |= piix_setup_idetim_timings(
483 1.8 thorpej mode[0], 0, chp->ch_channel);
484 1.19 perry else
485 1.1 bouyer idetim |= piix_setup_idetim_timings(
486 1.8 thorpej mode[1], 0, chp->ch_channel);
487 1.1 bouyer end: /*
488 1.1 bouyer * timing mode is now set up in the controller. Enable
489 1.1 bouyer * it per-drive
490 1.1 bouyer */
491 1.1 bouyer for (drive = 0; drive < 2; drive++) {
492 1.1 bouyer /* If no drive, skip */
493 1.1 bouyer if ((drvp[drive].drive_flags & DRIVE) == 0)
494 1.1 bouyer continue;
495 1.1 bouyer idetim |= piix_setup_idetim_drvs(&drvp[drive]);
496 1.1 bouyer if (drvp[drive].drive_flags & DRIVE_DMA)
497 1.1 bouyer idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
498 1.1 bouyer }
499 1.1 bouyer if (idedma_ctl != 0) {
500 1.1 bouyer /* Add software bits in status register */
501 1.3 fvdl bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
502 1.1 bouyer idedma_ctl);
503 1.1 bouyer }
504 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
505 1.1 bouyer }
506 1.1 bouyer
507 1.2 thorpej static void
508 1.12 thorpej piix3_4_setup_channel(struct ata_channel *chp)
509 1.1 bouyer {
510 1.1 bouyer struct ata_drive_datas *drvp;
511 1.1 bouyer u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl;
512 1.13 thorpej struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
513 1.13 thorpej struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
514 1.8 thorpej struct wdc_softc *wdc = &sc->sc_wdcdev;
515 1.15 thorpej int drive, s;
516 1.8 thorpej int channel = chp->ch_channel;
517 1.1 bouyer
518 1.1 bouyer oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
519 1.1 bouyer sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM);
520 1.1 bouyer udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG);
521 1.1 bouyer ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG);
522 1.1 bouyer idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel);
523 1.1 bouyer sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) |
524 1.1 bouyer PIIX_SIDETIM_RTC_MASK(channel));
525 1.1 bouyer idedma_ctl = 0;
526 1.1 bouyer
527 1.1 bouyer /* set up new idetim: Enable IDE registers decode */
528 1.1 bouyer idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel);
529 1.1 bouyer
530 1.1 bouyer /* setup DMA if needed */
531 1.1 bouyer pciide_channel_dma_setup(cp);
532 1.1 bouyer
533 1.1 bouyer for (drive = 0; drive < 2; drive++) {
534 1.1 bouyer udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) |
535 1.1 bouyer PIIX_UDMATIM_SET(0x3, channel, drive));
536 1.1 bouyer drvp = &chp->ch_drive[drive];
537 1.1 bouyer /* If no drive, skip */
538 1.1 bouyer if ((drvp->drive_flags & DRIVE) == 0)
539 1.1 bouyer continue;
540 1.1 bouyer if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
541 1.1 bouyer (drvp->drive_flags & DRIVE_UDMA) == 0))
542 1.1 bouyer goto pio;
543 1.1 bouyer
544 1.1 bouyer if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
545 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
546 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
547 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
548 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
549 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
550 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
551 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
552 1.9 thorpej sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
553 1.17 cube sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
554 1.19.2.3 riz sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
555 1.19.2.3 riz sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) {
556 1.1 bouyer ideconf |= PIIX_CONFIG_PINGPONG;
557 1.1 bouyer }
558 1.1 bouyer if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
559 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
560 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
561 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
562 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
563 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
564 1.9 thorpej sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
565 1.17 cube sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
566 1.19.2.3 riz sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
567 1.19.2.3 riz sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) {
568 1.1 bouyer /* setup Ultra/100 */
569 1.1 bouyer if (drvp->UDMA_mode > 2 &&
570 1.1 bouyer (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
571 1.1 bouyer drvp->UDMA_mode = 2;
572 1.1 bouyer if (drvp->UDMA_mode > 4) {
573 1.1 bouyer ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
574 1.1 bouyer } else {
575 1.1 bouyer ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
576 1.1 bouyer if (drvp->UDMA_mode > 2) {
577 1.1 bouyer ideconf |= PIIX_CONFIG_UDMA66(channel,
578 1.1 bouyer drive);
579 1.1 bouyer } else {
580 1.1 bouyer ideconf &= ~PIIX_CONFIG_UDMA66(channel,
581 1.1 bouyer drive);
582 1.1 bouyer }
583 1.1 bouyer }
584 1.1 bouyer }
585 1.1 bouyer if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) {
586 1.1 bouyer /* setup Ultra/66 */
587 1.1 bouyer if (drvp->UDMA_mode > 2 &&
588 1.1 bouyer (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
589 1.1 bouyer drvp->UDMA_mode = 2;
590 1.1 bouyer if (drvp->UDMA_mode > 2)
591 1.1 bouyer ideconf |= PIIX_CONFIG_UDMA66(channel, drive);
592 1.1 bouyer else
593 1.1 bouyer ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive);
594 1.1 bouyer }
595 1.14 thorpej if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) &&
596 1.1 bouyer (drvp->drive_flags & DRIVE_UDMA)) {
597 1.1 bouyer /* use Ultra/DMA */
598 1.15 thorpej s = splbio();
599 1.1 bouyer drvp->drive_flags &= ~DRIVE_DMA;
600 1.15 thorpej splx(s);
601 1.1 bouyer udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive);
602 1.1 bouyer udmareg |= PIIX_UDMATIM_SET(
603 1.1 bouyer piix4_sct_udma[drvp->UDMA_mode], channel, drive);
604 1.1 bouyer } else {
605 1.1 bouyer /* use Multiword DMA */
606 1.15 thorpej s = splbio();
607 1.1 bouyer drvp->drive_flags &= ~DRIVE_UDMA;
608 1.15 thorpej splx(s);
609 1.1 bouyer if (drive == 0) {
610 1.1 bouyer idetim |= piix_setup_idetim_timings(
611 1.1 bouyer drvp->DMA_mode, 1, channel);
612 1.1 bouyer } else {
613 1.1 bouyer sidetim |= piix_setup_sidetim_timings(
614 1.1 bouyer drvp->DMA_mode, 1, channel);
615 1.1 bouyer idetim =PIIX_IDETIM_SET(idetim,
616 1.1 bouyer PIIX_IDETIM_SITRE, channel);
617 1.1 bouyer }
618 1.1 bouyer }
619 1.1 bouyer idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
620 1.19 perry
621 1.1 bouyer pio: /* use PIO mode */
622 1.1 bouyer idetim |= piix_setup_idetim_drvs(drvp);
623 1.1 bouyer if (drive == 0) {
624 1.1 bouyer idetim |= piix_setup_idetim_timings(
625 1.1 bouyer drvp->PIO_mode, 0, channel);
626 1.1 bouyer } else {
627 1.1 bouyer sidetim |= piix_setup_sidetim_timings(
628 1.1 bouyer drvp->PIO_mode, 0, channel);
629 1.1 bouyer idetim =PIIX_IDETIM_SET(idetim,
630 1.1 bouyer PIIX_IDETIM_SITRE, channel);
631 1.1 bouyer }
632 1.1 bouyer }
633 1.1 bouyer if (idedma_ctl != 0) {
634 1.1 bouyer /* Add software bits in status register */
635 1.3 fvdl bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
636 1.1 bouyer idedma_ctl);
637 1.1 bouyer }
638 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
639 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim);
640 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg);
641 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf);
642 1.1 bouyer }
643 1.1 bouyer
644 1.1 bouyer
645 1.1 bouyer /* setup ISP and RTC fields, based on mode */
646 1.1 bouyer static u_int32_t
647 1.1 bouyer piix_setup_idetim_timings(mode, dma, channel)
648 1.1 bouyer u_int8_t mode;
649 1.1 bouyer u_int8_t dma;
650 1.1 bouyer u_int8_t channel;
651 1.1 bouyer {
652 1.19 perry
653 1.1 bouyer if (dma)
654 1.1 bouyer return PIIX_IDETIM_SET(0,
655 1.19 perry PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) |
656 1.1 bouyer PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]),
657 1.1 bouyer channel);
658 1.19 perry else
659 1.1 bouyer return PIIX_IDETIM_SET(0,
660 1.19 perry PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) |
661 1.1 bouyer PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]),
662 1.1 bouyer channel);
663 1.1 bouyer }
664 1.1 bouyer
665 1.1 bouyer /* setup DTE, PPE, IE and TIME field based on PIO mode */
666 1.1 bouyer static u_int32_t
667 1.1 bouyer piix_setup_idetim_drvs(drvp)
668 1.1 bouyer struct ata_drive_datas *drvp;
669 1.1 bouyer {
670 1.1 bouyer u_int32_t ret = 0;
671 1.12 thorpej struct ata_channel *chp = drvp->chnl_softc;
672 1.8 thorpej u_int8_t channel = chp->ch_channel;
673 1.1 bouyer u_int8_t drive = drvp->drive;
674 1.1 bouyer
675 1.1 bouyer /*
676 1.1 bouyer * If drive is using UDMA, timings setups are independant
677 1.1 bouyer * So just check DMA and PIO here.
678 1.1 bouyer */
679 1.1 bouyer if (drvp->drive_flags & DRIVE_DMA) {
680 1.1 bouyer /* if mode = DMA mode 0, use compatible timings */
681 1.1 bouyer if ((drvp->drive_flags & DRIVE_DMA) &&
682 1.1 bouyer drvp->DMA_mode == 0) {
683 1.1 bouyer drvp->PIO_mode = 0;
684 1.1 bouyer return ret;
685 1.1 bouyer }
686 1.1 bouyer ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
687 1.1 bouyer /*
688 1.1 bouyer * PIO and DMA timings are the same, use fast timings for PIO
689 1.1 bouyer * too, else use compat timings.
690 1.1 bouyer */
691 1.1 bouyer if ((piix_isp_pio[drvp->PIO_mode] !=
692 1.1 bouyer piix_isp_dma[drvp->DMA_mode]) ||
693 1.1 bouyer (piix_rtc_pio[drvp->PIO_mode] !=
694 1.1 bouyer piix_rtc_dma[drvp->DMA_mode]))
695 1.1 bouyer drvp->PIO_mode = 0;
696 1.1 bouyer /* if PIO mode <= 2, use compat timings for PIO */
697 1.1 bouyer if (drvp->PIO_mode <= 2) {
698 1.1 bouyer ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive),
699 1.1 bouyer channel);
700 1.1 bouyer return ret;
701 1.1 bouyer }
702 1.1 bouyer }
703 1.1 bouyer
704 1.1 bouyer /*
705 1.1 bouyer * Now setup PIO modes. If mode < 2, use compat timings.
706 1.1 bouyer * Else enable fast timings. Enable IORDY and prefetch/post
707 1.1 bouyer * if PIO mode >= 3.
708 1.1 bouyer */
709 1.1 bouyer
710 1.1 bouyer if (drvp->PIO_mode < 2)
711 1.1 bouyer return ret;
712 1.1 bouyer
713 1.1 bouyer ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
714 1.1 bouyer if (drvp->PIO_mode >= 3) {
715 1.1 bouyer ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel);
716 1.1 bouyer ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel);
717 1.1 bouyer }
718 1.1 bouyer return ret;
719 1.1 bouyer }
720 1.1 bouyer
721 1.1 bouyer /* setup values in SIDETIM registers, based on mode */
722 1.1 bouyer static u_int32_t
723 1.1 bouyer piix_setup_sidetim_timings(mode, dma, channel)
724 1.1 bouyer u_int8_t mode;
725 1.1 bouyer u_int8_t dma;
726 1.1 bouyer u_int8_t channel;
727 1.1 bouyer {
728 1.1 bouyer if (dma)
729 1.1 bouyer return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) |
730 1.1 bouyer PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel);
731 1.19 perry else
732 1.1 bouyer return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) |
733 1.1 bouyer PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel);
734 1.5 bouyer }
735 1.5 bouyer
736 1.5 bouyer static void
737 1.5 bouyer piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
738 1.5 bouyer {
739 1.5 bouyer struct pciide_channel *cp;
740 1.5 bouyer bus_size_t cmdsize, ctlsize;
741 1.19.2.2 tron pcireg_t interface, cmdsts;
742 1.5 bouyer int channel;
743 1.5 bouyer
744 1.5 bouyer if (pciide_chipen(sc, pa) == 0)
745 1.5 bouyer return;
746 1.5 bouyer
747 1.5 bouyer aprint_normal("%s: bus-master DMA support present",
748 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
749 1.5 bouyer pciide_mapreg_dma(sc, pa);
750 1.5 bouyer aprint_normal("\n");
751 1.1 bouyer
752 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
753 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
754 1.1 bouyer if (sc->sc_dma_ok) {
755 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
756 1.1 bouyer sc->sc_wdcdev.irqack = pciide_irqack;
757 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
758 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
759 1.1 bouyer }
760 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
761 1.1 bouyer
762 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
763 1.14 thorpej sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
764 1.1 bouyer
765 1.19.2.2 tron cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
766 1.19.2.2 tron cmdsts &= ~0x0400;
767 1.19.2.2 tron pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts);
768 1.19.2.2 tron
769 1.19.2.2 tron if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
770 1.19.2.2 tron PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
771 1.19.2.2 tron sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
772 1.19.2.2 tron
773 1.1 bouyer interface = PCI_INTERFACE(pa->pa_class);
774 1.1 bouyer
775 1.12 thorpej wdc_allocate_regs(&sc->sc_wdcdev);
776 1.12 thorpej
777 1.14 thorpej for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
778 1.14 thorpej channel++) {
779 1.1 bouyer cp = &sc->pciide_channels[channel];
780 1.1 bouyer if (pciide_chansetup(sc, channel, interface) == 0)
781 1.1 bouyer continue;
782 1.1 bouyer pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
783 1.1 bouyer pciide_pci_intr);
784 1.1 bouyer }
785 1.1 bouyer }
786