piixide.c revision 1.9.2.4
1 1.9.2.4 skrll /* $NetBSD: piixide.c,v 1.9.2.4 2004/09/18 14:49:06 skrll Exp $ */ 2 1.9.2.2 skrll 3 1.9.2.2 skrll /* 4 1.9.2.2 skrll * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 1.9.2.2 skrll * 6 1.9.2.2 skrll * Redistribution and use in source and binary forms, with or without 7 1.9.2.2 skrll * modification, are permitted provided that the following conditions 8 1.9.2.2 skrll * are met: 9 1.9.2.2 skrll * 1. Redistributions of source code must retain the above copyright 10 1.9.2.2 skrll * notice, this list of conditions and the following disclaimer. 11 1.9.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.9.2.2 skrll * notice, this list of conditions and the following disclaimer in the 13 1.9.2.2 skrll * documentation and/or other materials provided with the distribution. 14 1.9.2.2 skrll * 3. All advertising materials mentioning features or use of this software 15 1.9.2.2 skrll * must display the following acknowledgement: 16 1.9.2.2 skrll * This product includes software developed by Manuel Bouyer. 17 1.9.2.2 skrll * 4. The name of the author may not be used to endorse or promote products 18 1.9.2.2 skrll * derived from this software without specific prior written permission. 19 1.9.2.2 skrll * 20 1.9.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 1.9.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 1.9.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 1.9.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 1.9.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 1.9.2.2 skrll * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.9.2.2 skrll * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 1.9.2.2 skrll * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 1.9.2.2 skrll * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 1.9.2.2 skrll * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 1.9.2.2 skrll */ 31 1.9.2.2 skrll 32 1.9.2.2 skrll #include <sys/param.h> 33 1.9.2.2 skrll #include <sys/systm.h> 34 1.9.2.2 skrll 35 1.9.2.2 skrll #include <dev/pci/pcivar.h> 36 1.9.2.2 skrll #include <dev/pci/pcidevs.h> 37 1.9.2.2 skrll #include <dev/pci/pciidereg.h> 38 1.9.2.2 skrll #include <dev/pci/pciidevar.h> 39 1.9.2.2 skrll #include <dev/pci/pciide_piix_reg.h> 40 1.9.2.2 skrll 41 1.9.2.2 skrll static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 1.9.2.3 skrll static void piix_setup_channel(struct ata_channel *); 43 1.9.2.3 skrll static void piix3_4_setup_channel(struct ata_channel *); 44 1.9.2.2 skrll static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 1.9.2.2 skrll static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 1.9.2.2 skrll static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 1.9.2.2 skrll static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 1.9.2.2 skrll 49 1.9.2.2 skrll static int piixide_match(struct device *, struct cfdata *, void *); 50 1.9.2.2 skrll static void piixide_attach(struct device *, struct device *, void *); 51 1.9.2.2 skrll 52 1.9.2.2 skrll static const struct pciide_product_desc pciide_intel_products[] = { 53 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82092AA, 54 1.9.2.2 skrll 0, 55 1.9.2.2 skrll "Intel 82092AA IDE controller", 56 1.9.2.2 skrll default_chip_map, 57 1.9.2.2 skrll }, 58 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82371FB_IDE, 59 1.9.2.2 skrll 0, 60 1.9.2.2 skrll "Intel 82371FB IDE controller (PIIX)", 61 1.9.2.2 skrll piix_chip_map, 62 1.9.2.2 skrll }, 63 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82371SB_IDE, 64 1.9.2.2 skrll 0, 65 1.9.2.2 skrll "Intel 82371SB IDE Interface (PIIX3)", 66 1.9.2.2 skrll piix_chip_map, 67 1.9.2.2 skrll }, 68 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82371AB_IDE, 69 1.9.2.2 skrll 0, 70 1.9.2.2 skrll "Intel 82371AB IDE controller (PIIX4)", 71 1.9.2.2 skrll piix_chip_map, 72 1.9.2.2 skrll }, 73 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82440MX_IDE, 74 1.9.2.2 skrll 0, 75 1.9.2.2 skrll "Intel 82440MX IDE controller", 76 1.9.2.2 skrll piix_chip_map 77 1.9.2.2 skrll }, 78 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801AA_IDE, 79 1.9.2.2 skrll 0, 80 1.9.2.2 skrll "Intel 82801AA IDE Controller (ICH)", 81 1.9.2.2 skrll piix_chip_map, 82 1.9.2.2 skrll }, 83 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801AB_IDE, 84 1.9.2.2 skrll 0, 85 1.9.2.2 skrll "Intel 82801AB IDE Controller (ICH0)", 86 1.9.2.2 skrll piix_chip_map, 87 1.9.2.2 skrll }, 88 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801BA_IDE, 89 1.9.2.2 skrll 0, 90 1.9.2.2 skrll "Intel 82801BA IDE Controller (ICH2)", 91 1.9.2.2 skrll piix_chip_map, 92 1.9.2.2 skrll }, 93 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 1.9.2.2 skrll 0, 95 1.9.2.2 skrll "Intel 82801BAM IDE Controller (ICH2-M)", 96 1.9.2.2 skrll piix_chip_map, 97 1.9.2.2 skrll }, 98 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 1.9.2.2 skrll 0, 100 1.9.2.2 skrll "Intel 82801CA IDE Controller (ICH3)", 101 1.9.2.2 skrll piix_chip_map, 102 1.9.2.2 skrll }, 103 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 1.9.2.2 skrll 0, 105 1.9.2.2 skrll "Intel 82801CA IDE Controller (ICH3)", 106 1.9.2.2 skrll piix_chip_map, 107 1.9.2.2 skrll }, 108 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801DB_IDE, 109 1.9.2.2 skrll 0, 110 1.9.2.2 skrll "Intel 82801DB IDE Controller (ICH4)", 111 1.9.2.2 skrll piix_chip_map, 112 1.9.2.2 skrll }, 113 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 1.9.2.2 skrll 0, 115 1.9.2.2 skrll "Intel 82801DBM IDE Controller (ICH4-M)", 116 1.9.2.2 skrll piix_chip_map, 117 1.9.2.2 skrll }, 118 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801EB_IDE, 119 1.9.2.2 skrll 0, 120 1.9.2.2 skrll "Intel 82801EB IDE Controller (ICH5)", 121 1.9.2.2 skrll piix_chip_map, 122 1.9.2.2 skrll }, 123 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801EB_SATA, 124 1.9.2.2 skrll 0, 125 1.9.2.2 skrll "Intel 82801EB Serial ATA Controller", 126 1.9.2.2 skrll piixsata_chip_map, 127 1.9.2.2 skrll }, 128 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801ER_SATA, 129 1.9.2.2 skrll 0, 130 1.9.2.2 skrll "Intel 82801ER Serial ATA/Raid Controller", 131 1.9.2.2 skrll piixsata_chip_map, 132 1.9.2.2 skrll }, 133 1.9.2.2 skrll { PCI_PRODUCT_INTEL_6300ESB_IDE, 134 1.9.2.2 skrll 0, 135 1.9.2.2 skrll "Intel 6300ESB IDE Controller (ICH5)", 136 1.9.2.2 skrll piix_chip_map, 137 1.9.2.2 skrll }, 138 1.9.2.2 skrll { PCI_PRODUCT_INTEL_6300ESB_SATA, 139 1.9.2.2 skrll 0, 140 1.9.2.2 skrll "Intel 6300ESB Serial ATA Controller", 141 1.9.2.2 skrll piixsata_chip_map, 142 1.9.2.2 skrll }, 143 1.9.2.2 skrll { 0, 144 1.9.2.2 skrll 0, 145 1.9.2.2 skrll NULL, 146 1.9.2.2 skrll NULL 147 1.9.2.2 skrll } 148 1.9.2.2 skrll }; 149 1.9.2.2 skrll 150 1.9.2.2 skrll CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 151 1.9.2.2 skrll piixide_match, piixide_attach, NULL, NULL); 152 1.9.2.2 skrll 153 1.9.2.2 skrll static int 154 1.9.2.2 skrll piixide_match(struct device *parent, struct cfdata *match, void *aux) 155 1.9.2.2 skrll { 156 1.9.2.2 skrll struct pci_attach_args *pa = aux; 157 1.9.2.2 skrll 158 1.9.2.2 skrll if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 159 1.9.2.2 skrll if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 160 1.9.2.2 skrll return (2); 161 1.9.2.2 skrll } 162 1.9.2.2 skrll return (0); 163 1.9.2.2 skrll } 164 1.9.2.2 skrll 165 1.9.2.2 skrll static void 166 1.9.2.2 skrll piixide_attach(struct device *parent, struct device *self, void *aux) 167 1.9.2.2 skrll { 168 1.9.2.2 skrll struct pci_attach_args *pa = aux; 169 1.9.2.2 skrll struct pciide_softc *sc = (struct pciide_softc *)self; 170 1.9.2.2 skrll 171 1.9.2.2 skrll pciide_common_attach(sc, pa, 172 1.9.2.2 skrll pciide_lookup_product(pa->pa_id, pciide_intel_products)); 173 1.9.2.2 skrll 174 1.9.2.2 skrll } 175 1.9.2.2 skrll 176 1.9.2.2 skrll static void 177 1.9.2.2 skrll piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 178 1.9.2.2 skrll { 179 1.9.2.2 skrll struct pciide_channel *cp; 180 1.9.2.2 skrll int channel; 181 1.9.2.2 skrll u_int32_t idetim; 182 1.9.2.2 skrll bus_size_t cmdsize, ctlsize; 183 1.9.2.2 skrll 184 1.9.2.2 skrll if (pciide_chipen(sc, pa) == 0) 185 1.9.2.2 skrll return; 186 1.9.2.2 skrll 187 1.9.2.2 skrll aprint_normal("%s: bus-master DMA support present", 188 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 189 1.9.2.2 skrll pciide_mapreg_dma(sc, pa); 190 1.9.2.2 skrll aprint_normal("\n"); 191 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 192 1.9.2.2 skrll if (sc->sc_dma_ok) { 193 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 194 1.9.2.2 skrll sc->sc_wdcdev.irqack = pciide_irqack; 195 1.9.2.2 skrll switch(sc->sc_pp->ide_product) { 196 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82371AB_IDE: 197 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82440MX_IDE: 198 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801AA_IDE: 199 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801AB_IDE: 200 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801BA_IDE: 201 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801BAM_IDE: 202 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801CA_IDE_1: 203 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801CA_IDE_2: 204 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801DB_IDE: 205 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801DBM_IDE: 206 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801EB_IDE: 207 1.9.2.2 skrll case PCI_PRODUCT_INTEL_6300ESB_IDE: 208 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 209 1.9.2.2 skrll } 210 1.9.2.2 skrll } 211 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 212 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 213 1.9.2.2 skrll switch(sc->sc_pp->ide_product) { 214 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801AA_IDE: 215 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 216 1.9.2.2 skrll break; 217 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801BA_IDE: 218 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801BAM_IDE: 219 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801CA_IDE_1: 220 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801CA_IDE_2: 221 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801DB_IDE: 222 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801DBM_IDE: 223 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801EB_IDE: 224 1.9.2.2 skrll case PCI_PRODUCT_INTEL_6300ESB_IDE: 225 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 226 1.9.2.2 skrll break; 227 1.9.2.2 skrll default: 228 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 229 1.9.2.2 skrll } 230 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 231 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 232 1.9.2.2 skrll else 233 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 234 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 235 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 236 1.9.2.2 skrll 237 1.9.2.3 skrll ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 238 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 239 1.9.2.2 skrll DEBUG_PROBE); 240 1.9.2.2 skrll if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 241 1.9.2.3 skrll ATADEBUG_PRINT((", sidetim=0x%x", 242 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 243 1.9.2.2 skrll DEBUG_PROBE); 244 1.9.2.3 skrll if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 245 1.9.2.3 skrll ATADEBUG_PRINT((", udamreg 0x%x", 246 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 247 1.9.2.2 skrll DEBUG_PROBE); 248 1.9.2.2 skrll } 249 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 250 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 251 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 252 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 253 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 254 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 255 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 256 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 257 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 258 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 259 1.9.2.3 skrll ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 260 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 261 1.9.2.2 skrll DEBUG_PROBE); 262 1.9.2.2 skrll } 263 1.9.2.2 skrll 264 1.9.2.2 skrll } 265 1.9.2.3 skrll ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 266 1.9.2.2 skrll 267 1.9.2.3 skrll wdc_allocate_regs(&sc->sc_wdcdev); 268 1.9.2.3 skrll 269 1.9.2.3 skrll for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 270 1.9.2.3 skrll channel++) { 271 1.9.2.2 skrll cp = &sc->pciide_channels[channel]; 272 1.9.2.2 skrll /* PIIX is compat-only */ 273 1.9.2.2 skrll if (pciide_chansetup(sc, channel, 0) == 0) 274 1.9.2.2 skrll continue; 275 1.9.2.2 skrll idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 276 1.9.2.2 skrll if ((PIIX_IDETIM_READ(idetim, channel) & 277 1.9.2.2 skrll PIIX_IDETIM_IDE) == 0) { 278 1.9.2.2 skrll #if 1 279 1.9.2.2 skrll aprint_normal("%s: %s channel ignored (disabled)\n", 280 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 281 1.9.2.3 skrll cp->ata_channel.ch_flags |= ATACH_DISABLED; 282 1.9.2.2 skrll continue; 283 1.9.2.2 skrll #else 284 1.9.2.2 skrll pcireg_t interface; 285 1.9.2.2 skrll 286 1.9.2.2 skrll idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 287 1.9.2.2 skrll channel); 288 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 289 1.9.2.2 skrll idetim); 290 1.9.2.2 skrll interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 291 1.9.2.2 skrll sc->sc_tag, PCI_CLASS_REG)); 292 1.9.2.2 skrll aprint_normal("channel %d idetim=%08x interface=%02x\n", 293 1.9.2.2 skrll channel, idetim, interface); 294 1.9.2.2 skrll #endif 295 1.9.2.2 skrll } 296 1.9.2.2 skrll /* PIIX are compat-only pciide devices */ 297 1.9.2.2 skrll pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 298 1.9.2.2 skrll } 299 1.9.2.2 skrll 300 1.9.2.3 skrll ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 301 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 302 1.9.2.2 skrll DEBUG_PROBE); 303 1.9.2.2 skrll if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 304 1.9.2.3 skrll ATADEBUG_PRINT((", sidetim=0x%x", 305 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 306 1.9.2.2 skrll DEBUG_PROBE); 307 1.9.2.3 skrll if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 308 1.9.2.3 skrll ATADEBUG_PRINT((", udamreg 0x%x", 309 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 310 1.9.2.2 skrll DEBUG_PROBE); 311 1.9.2.2 skrll } 312 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 313 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 314 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 315 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 316 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 317 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 318 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 319 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 320 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 321 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 322 1.9.2.3 skrll ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 323 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 324 1.9.2.2 skrll DEBUG_PROBE); 325 1.9.2.2 skrll } 326 1.9.2.2 skrll } 327 1.9.2.3 skrll ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 328 1.9.2.2 skrll } 329 1.9.2.2 skrll 330 1.9.2.2 skrll static void 331 1.9.2.3 skrll piix_setup_channel(struct ata_channel *chp) 332 1.9.2.2 skrll { 333 1.9.2.2 skrll u_int8_t mode[2], drive; 334 1.9.2.2 skrll u_int32_t oidetim, idetim, idedma_ctl; 335 1.9.2.3 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 336 1.9.2.3 skrll struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 337 1.9.2.3 skrll struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 338 1.9.2.2 skrll 339 1.9.2.2 skrll oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 340 1.9.2.2 skrll idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 341 1.9.2.2 skrll idedma_ctl = 0; 342 1.9.2.2 skrll 343 1.9.2.2 skrll /* set up new idetim: Enable IDE registers decode */ 344 1.9.2.2 skrll idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 345 1.9.2.2 skrll chp->ch_channel); 346 1.9.2.2 skrll 347 1.9.2.2 skrll /* setup DMA */ 348 1.9.2.2 skrll pciide_channel_dma_setup(cp); 349 1.9.2.2 skrll 350 1.9.2.2 skrll /* 351 1.9.2.2 skrll * Here we have to mess up with drives mode: PIIX can't have 352 1.9.2.2 skrll * different timings for master and slave drives. 353 1.9.2.2 skrll * We need to find the best combination. 354 1.9.2.2 skrll */ 355 1.9.2.2 skrll 356 1.9.2.2 skrll /* If both drives supports DMA, take the lower mode */ 357 1.9.2.2 skrll if ((drvp[0].drive_flags & DRIVE_DMA) && 358 1.9.2.2 skrll (drvp[1].drive_flags & DRIVE_DMA)) { 359 1.9.2.2 skrll mode[0] = mode[1] = 360 1.9.2.2 skrll min(drvp[0].DMA_mode, drvp[1].DMA_mode); 361 1.9.2.2 skrll drvp[0].DMA_mode = mode[0]; 362 1.9.2.2 skrll drvp[1].DMA_mode = mode[1]; 363 1.9.2.2 skrll goto ok; 364 1.9.2.2 skrll } 365 1.9.2.2 skrll /* 366 1.9.2.2 skrll * If only one drive supports DMA, use its mode, and 367 1.9.2.2 skrll * put the other one in PIO mode 0 if mode not compatible 368 1.9.2.2 skrll */ 369 1.9.2.2 skrll if (drvp[0].drive_flags & DRIVE_DMA) { 370 1.9.2.2 skrll mode[0] = drvp[0].DMA_mode; 371 1.9.2.2 skrll mode[1] = drvp[1].PIO_mode; 372 1.9.2.2 skrll if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 373 1.9.2.2 skrll piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 374 1.9.2.2 skrll mode[1] = drvp[1].PIO_mode = 0; 375 1.9.2.2 skrll goto ok; 376 1.9.2.2 skrll } 377 1.9.2.2 skrll if (drvp[1].drive_flags & DRIVE_DMA) { 378 1.9.2.2 skrll mode[1] = drvp[1].DMA_mode; 379 1.9.2.2 skrll mode[0] = drvp[0].PIO_mode; 380 1.9.2.2 skrll if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 381 1.9.2.2 skrll piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 382 1.9.2.2 skrll mode[0] = drvp[0].PIO_mode = 0; 383 1.9.2.2 skrll goto ok; 384 1.9.2.2 skrll } 385 1.9.2.2 skrll /* 386 1.9.2.2 skrll * If both drives are not DMA, takes the lower mode, unless 387 1.9.2.2 skrll * one of them is PIO mode < 2 388 1.9.2.2 skrll */ 389 1.9.2.2 skrll if (drvp[0].PIO_mode < 2) { 390 1.9.2.2 skrll mode[0] = drvp[0].PIO_mode = 0; 391 1.9.2.2 skrll mode[1] = drvp[1].PIO_mode; 392 1.9.2.2 skrll } else if (drvp[1].PIO_mode < 2) { 393 1.9.2.2 skrll mode[1] = drvp[1].PIO_mode = 0; 394 1.9.2.2 skrll mode[0] = drvp[0].PIO_mode; 395 1.9.2.2 skrll } else { 396 1.9.2.2 skrll mode[0] = mode[1] = 397 1.9.2.2 skrll min(drvp[1].PIO_mode, drvp[0].PIO_mode); 398 1.9.2.2 skrll drvp[0].PIO_mode = mode[0]; 399 1.9.2.2 skrll drvp[1].PIO_mode = mode[1]; 400 1.9.2.2 skrll } 401 1.9.2.2 skrll ok: /* The modes are setup */ 402 1.9.2.2 skrll for (drive = 0; drive < 2; drive++) { 403 1.9.2.2 skrll if (drvp[drive].drive_flags & DRIVE_DMA) { 404 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 405 1.9.2.2 skrll mode[drive], 1, chp->ch_channel); 406 1.9.2.2 skrll goto end; 407 1.9.2.2 skrll } 408 1.9.2.2 skrll } 409 1.9.2.2 skrll /* If we are there, none of the drives are DMA */ 410 1.9.2.2 skrll if (mode[0] >= 2) 411 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 412 1.9.2.2 skrll mode[0], 0, chp->ch_channel); 413 1.9.2.2 skrll else 414 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 415 1.9.2.2 skrll mode[1], 0, chp->ch_channel); 416 1.9.2.2 skrll end: /* 417 1.9.2.2 skrll * timing mode is now set up in the controller. Enable 418 1.9.2.2 skrll * it per-drive 419 1.9.2.2 skrll */ 420 1.9.2.2 skrll for (drive = 0; drive < 2; drive++) { 421 1.9.2.2 skrll /* If no drive, skip */ 422 1.9.2.2 skrll if ((drvp[drive].drive_flags & DRIVE) == 0) 423 1.9.2.2 skrll continue; 424 1.9.2.2 skrll idetim |= piix_setup_idetim_drvs(&drvp[drive]); 425 1.9.2.2 skrll if (drvp[drive].drive_flags & DRIVE_DMA) 426 1.9.2.2 skrll idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 427 1.9.2.2 skrll } 428 1.9.2.2 skrll if (idedma_ctl != 0) { 429 1.9.2.2 skrll /* Add software bits in status register */ 430 1.9.2.2 skrll bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 431 1.9.2.2 skrll idedma_ctl); 432 1.9.2.2 skrll } 433 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 434 1.9.2.2 skrll } 435 1.9.2.2 skrll 436 1.9.2.2 skrll static void 437 1.9.2.3 skrll piix3_4_setup_channel(struct ata_channel *chp) 438 1.9.2.2 skrll { 439 1.9.2.2 skrll struct ata_drive_datas *drvp; 440 1.9.2.2 skrll u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 441 1.9.2.3 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 442 1.9.2.3 skrll struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 443 1.9.2.2 skrll struct wdc_softc *wdc = &sc->sc_wdcdev; 444 1.9.2.3 skrll int drive, s; 445 1.9.2.2 skrll int channel = chp->ch_channel; 446 1.9.2.2 skrll 447 1.9.2.2 skrll oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 448 1.9.2.2 skrll sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 449 1.9.2.2 skrll udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 450 1.9.2.2 skrll ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 451 1.9.2.2 skrll idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 452 1.9.2.2 skrll sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 453 1.9.2.2 skrll PIIX_SIDETIM_RTC_MASK(channel)); 454 1.9.2.2 skrll idedma_ctl = 0; 455 1.9.2.2 skrll 456 1.9.2.2 skrll /* set up new idetim: Enable IDE registers decode */ 457 1.9.2.2 skrll idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 458 1.9.2.2 skrll 459 1.9.2.2 skrll /* setup DMA if needed */ 460 1.9.2.2 skrll pciide_channel_dma_setup(cp); 461 1.9.2.2 skrll 462 1.9.2.2 skrll for (drive = 0; drive < 2; drive++) { 463 1.9.2.2 skrll udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 464 1.9.2.2 skrll PIIX_UDMATIM_SET(0x3, channel, drive)); 465 1.9.2.2 skrll drvp = &chp->ch_drive[drive]; 466 1.9.2.2 skrll /* If no drive, skip */ 467 1.9.2.2 skrll if ((drvp->drive_flags & DRIVE) == 0) 468 1.9.2.2 skrll continue; 469 1.9.2.2 skrll if (((drvp->drive_flags & DRIVE_DMA) == 0 && 470 1.9.2.2 skrll (drvp->drive_flags & DRIVE_UDMA) == 0)) 471 1.9.2.2 skrll goto pio; 472 1.9.2.2 skrll 473 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 474 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 475 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 476 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 477 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 478 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 479 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 480 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 481 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 482 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 483 1.9.2.2 skrll ideconf |= PIIX_CONFIG_PINGPONG; 484 1.9.2.2 skrll } 485 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 486 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 487 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 488 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 489 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 490 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 491 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 492 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 493 1.9.2.2 skrll /* setup Ultra/100 */ 494 1.9.2.2 skrll if (drvp->UDMA_mode > 2 && 495 1.9.2.2 skrll (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 496 1.9.2.2 skrll drvp->UDMA_mode = 2; 497 1.9.2.2 skrll if (drvp->UDMA_mode > 4) { 498 1.9.2.2 skrll ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 499 1.9.2.2 skrll } else { 500 1.9.2.2 skrll ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 501 1.9.2.2 skrll if (drvp->UDMA_mode > 2) { 502 1.9.2.2 skrll ideconf |= PIIX_CONFIG_UDMA66(channel, 503 1.9.2.2 skrll drive); 504 1.9.2.2 skrll } else { 505 1.9.2.2 skrll ideconf &= ~PIIX_CONFIG_UDMA66(channel, 506 1.9.2.2 skrll drive); 507 1.9.2.2 skrll } 508 1.9.2.2 skrll } 509 1.9.2.2 skrll } 510 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 511 1.9.2.2 skrll /* setup Ultra/66 */ 512 1.9.2.2 skrll if (drvp->UDMA_mode > 2 && 513 1.9.2.2 skrll (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 514 1.9.2.2 skrll drvp->UDMA_mode = 2; 515 1.9.2.2 skrll if (drvp->UDMA_mode > 2) 516 1.9.2.2 skrll ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 517 1.9.2.2 skrll else 518 1.9.2.2 skrll ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 519 1.9.2.2 skrll } 520 1.9.2.3 skrll if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 521 1.9.2.2 skrll (drvp->drive_flags & DRIVE_UDMA)) { 522 1.9.2.2 skrll /* use Ultra/DMA */ 523 1.9.2.3 skrll s = splbio(); 524 1.9.2.2 skrll drvp->drive_flags &= ~DRIVE_DMA; 525 1.9.2.3 skrll splx(s); 526 1.9.2.2 skrll udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 527 1.9.2.2 skrll udmareg |= PIIX_UDMATIM_SET( 528 1.9.2.2 skrll piix4_sct_udma[drvp->UDMA_mode], channel, drive); 529 1.9.2.2 skrll } else { 530 1.9.2.2 skrll /* use Multiword DMA */ 531 1.9.2.3 skrll s = splbio(); 532 1.9.2.2 skrll drvp->drive_flags &= ~DRIVE_UDMA; 533 1.9.2.3 skrll splx(s); 534 1.9.2.2 skrll if (drive == 0) { 535 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 536 1.9.2.2 skrll drvp->DMA_mode, 1, channel); 537 1.9.2.2 skrll } else { 538 1.9.2.2 skrll sidetim |= piix_setup_sidetim_timings( 539 1.9.2.2 skrll drvp->DMA_mode, 1, channel); 540 1.9.2.2 skrll idetim =PIIX_IDETIM_SET(idetim, 541 1.9.2.2 skrll PIIX_IDETIM_SITRE, channel); 542 1.9.2.2 skrll } 543 1.9.2.2 skrll } 544 1.9.2.2 skrll idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 545 1.9.2.2 skrll 546 1.9.2.2 skrll pio: /* use PIO mode */ 547 1.9.2.2 skrll idetim |= piix_setup_idetim_drvs(drvp); 548 1.9.2.2 skrll if (drive == 0) { 549 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 550 1.9.2.2 skrll drvp->PIO_mode, 0, channel); 551 1.9.2.2 skrll } else { 552 1.9.2.2 skrll sidetim |= piix_setup_sidetim_timings( 553 1.9.2.2 skrll drvp->PIO_mode, 0, channel); 554 1.9.2.2 skrll idetim =PIIX_IDETIM_SET(idetim, 555 1.9.2.2 skrll PIIX_IDETIM_SITRE, channel); 556 1.9.2.2 skrll } 557 1.9.2.2 skrll } 558 1.9.2.2 skrll if (idedma_ctl != 0) { 559 1.9.2.2 skrll /* Add software bits in status register */ 560 1.9.2.2 skrll bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 561 1.9.2.2 skrll idedma_ctl); 562 1.9.2.2 skrll } 563 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 564 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 565 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 566 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 567 1.9.2.2 skrll } 568 1.9.2.2 skrll 569 1.9.2.2 skrll 570 1.9.2.2 skrll /* setup ISP and RTC fields, based on mode */ 571 1.9.2.2 skrll static u_int32_t 572 1.9.2.2 skrll piix_setup_idetim_timings(mode, dma, channel) 573 1.9.2.2 skrll u_int8_t mode; 574 1.9.2.2 skrll u_int8_t dma; 575 1.9.2.2 skrll u_int8_t channel; 576 1.9.2.2 skrll { 577 1.9.2.2 skrll 578 1.9.2.2 skrll if (dma) 579 1.9.2.2 skrll return PIIX_IDETIM_SET(0, 580 1.9.2.2 skrll PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 581 1.9.2.2 skrll PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 582 1.9.2.2 skrll channel); 583 1.9.2.2 skrll else 584 1.9.2.2 skrll return PIIX_IDETIM_SET(0, 585 1.9.2.2 skrll PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 586 1.9.2.2 skrll PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 587 1.9.2.2 skrll channel); 588 1.9.2.2 skrll } 589 1.9.2.2 skrll 590 1.9.2.2 skrll /* setup DTE, PPE, IE and TIME field based on PIO mode */ 591 1.9.2.2 skrll static u_int32_t 592 1.9.2.2 skrll piix_setup_idetim_drvs(drvp) 593 1.9.2.2 skrll struct ata_drive_datas *drvp; 594 1.9.2.2 skrll { 595 1.9.2.2 skrll u_int32_t ret = 0; 596 1.9.2.3 skrll struct ata_channel *chp = drvp->chnl_softc; 597 1.9.2.2 skrll u_int8_t channel = chp->ch_channel; 598 1.9.2.2 skrll u_int8_t drive = drvp->drive; 599 1.9.2.2 skrll 600 1.9.2.2 skrll /* 601 1.9.2.2 skrll * If drive is using UDMA, timings setups are independant 602 1.9.2.2 skrll * So just check DMA and PIO here. 603 1.9.2.2 skrll */ 604 1.9.2.2 skrll if (drvp->drive_flags & DRIVE_DMA) { 605 1.9.2.2 skrll /* if mode = DMA mode 0, use compatible timings */ 606 1.9.2.2 skrll if ((drvp->drive_flags & DRIVE_DMA) && 607 1.9.2.2 skrll drvp->DMA_mode == 0) { 608 1.9.2.2 skrll drvp->PIO_mode = 0; 609 1.9.2.2 skrll return ret; 610 1.9.2.2 skrll } 611 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 612 1.9.2.2 skrll /* 613 1.9.2.2 skrll * PIO and DMA timings are the same, use fast timings for PIO 614 1.9.2.2 skrll * too, else use compat timings. 615 1.9.2.2 skrll */ 616 1.9.2.2 skrll if ((piix_isp_pio[drvp->PIO_mode] != 617 1.9.2.2 skrll piix_isp_dma[drvp->DMA_mode]) || 618 1.9.2.2 skrll (piix_rtc_pio[drvp->PIO_mode] != 619 1.9.2.2 skrll piix_rtc_dma[drvp->DMA_mode])) 620 1.9.2.2 skrll drvp->PIO_mode = 0; 621 1.9.2.2 skrll /* if PIO mode <= 2, use compat timings for PIO */ 622 1.9.2.2 skrll if (drvp->PIO_mode <= 2) { 623 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 624 1.9.2.2 skrll channel); 625 1.9.2.2 skrll return ret; 626 1.9.2.2 skrll } 627 1.9.2.2 skrll } 628 1.9.2.2 skrll 629 1.9.2.2 skrll /* 630 1.9.2.2 skrll * Now setup PIO modes. If mode < 2, use compat timings. 631 1.9.2.2 skrll * Else enable fast timings. Enable IORDY and prefetch/post 632 1.9.2.2 skrll * if PIO mode >= 3. 633 1.9.2.2 skrll */ 634 1.9.2.2 skrll 635 1.9.2.2 skrll if (drvp->PIO_mode < 2) 636 1.9.2.2 skrll return ret; 637 1.9.2.2 skrll 638 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 639 1.9.2.2 skrll if (drvp->PIO_mode >= 3) { 640 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 641 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 642 1.9.2.2 skrll } 643 1.9.2.2 skrll return ret; 644 1.9.2.2 skrll } 645 1.9.2.2 skrll 646 1.9.2.2 skrll /* setup values in SIDETIM registers, based on mode */ 647 1.9.2.2 skrll static u_int32_t 648 1.9.2.2 skrll piix_setup_sidetim_timings(mode, dma, channel) 649 1.9.2.2 skrll u_int8_t mode; 650 1.9.2.2 skrll u_int8_t dma; 651 1.9.2.2 skrll u_int8_t channel; 652 1.9.2.2 skrll { 653 1.9.2.2 skrll if (dma) 654 1.9.2.2 skrll return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 655 1.9.2.2 skrll PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 656 1.9.2.2 skrll else 657 1.9.2.2 skrll return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 658 1.9.2.2 skrll PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 659 1.9.2.2 skrll } 660 1.9.2.2 skrll 661 1.9.2.2 skrll static void 662 1.9.2.2 skrll piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 663 1.9.2.2 skrll { 664 1.9.2.2 skrll struct pciide_channel *cp; 665 1.9.2.2 skrll bus_size_t cmdsize, ctlsize; 666 1.9.2.2 skrll pcireg_t interface; 667 1.9.2.2 skrll int channel; 668 1.9.2.2 skrll 669 1.9.2.2 skrll if (pciide_chipen(sc, pa) == 0) 670 1.9.2.2 skrll return; 671 1.9.2.2 skrll 672 1.9.2.2 skrll aprint_normal("%s: bus-master DMA support present", 673 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 674 1.9.2.2 skrll pciide_mapreg_dma(sc, pa); 675 1.9.2.2 skrll aprint_normal("\n"); 676 1.9.2.2 skrll 677 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 678 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 679 1.9.2.2 skrll if (sc->sc_dma_ok) { 680 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 681 1.9.2.2 skrll sc->sc_wdcdev.irqack = pciide_irqack; 682 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 683 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 684 1.9.2.2 skrll } 685 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 686 1.9.2.2 skrll 687 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 688 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 689 1.9.2.2 skrll 690 1.9.2.2 skrll interface = PCI_INTERFACE(pa->pa_class); 691 1.9.2.2 skrll 692 1.9.2.3 skrll wdc_allocate_regs(&sc->sc_wdcdev); 693 1.9.2.3 skrll 694 1.9.2.3 skrll for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 695 1.9.2.3 skrll channel++) { 696 1.9.2.2 skrll cp = &sc->pciide_channels[channel]; 697 1.9.2.2 skrll if (pciide_chansetup(sc, channel, interface) == 0) 698 1.9.2.2 skrll continue; 699 1.9.2.2 skrll pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 700 1.9.2.2 skrll pciide_pci_intr); 701 1.9.2.2 skrll } 702 1.9.2.2 skrll } 703
Indexes created Thu Oct 16 14:10:15 GMT 2025