piixide.c revision 1.9.2.9
1 1.9.2.9 skrll /* $NetBSD: piixide.c,v 1.9.2.9 2005/03/04 16:45:25 skrll Exp $ */ 2 1.9.2.2 skrll 3 1.9.2.2 skrll /* 4 1.9.2.2 skrll * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 1.9.2.2 skrll * 6 1.9.2.2 skrll * Redistribution and use in source and binary forms, with or without 7 1.9.2.2 skrll * modification, are permitted provided that the following conditions 8 1.9.2.2 skrll * are met: 9 1.9.2.2 skrll * 1. Redistributions of source code must retain the above copyright 10 1.9.2.2 skrll * notice, this list of conditions and the following disclaimer. 11 1.9.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.9.2.2 skrll * notice, this list of conditions and the following disclaimer in the 13 1.9.2.2 skrll * documentation and/or other materials provided with the distribution. 14 1.9.2.2 skrll * 3. All advertising materials mentioning features or use of this software 15 1.9.2.2 skrll * must display the following acknowledgement: 16 1.9.2.2 skrll * This product includes software developed by Manuel Bouyer. 17 1.9.2.2 skrll * 4. The name of the author may not be used to endorse or promote products 18 1.9.2.2 skrll * derived from this software without specific prior written permission. 19 1.9.2.2 skrll * 20 1.9.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 1.9.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 1.9.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 1.9.2.9 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 1.9.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 1.9.2.2 skrll * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.9.2.2 skrll * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 1.9.2.2 skrll * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 1.9.2.2 skrll * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 1.9.2.2 skrll * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 1.9.2.2 skrll */ 31 1.9.2.2 skrll 32 1.9.2.2 skrll #include <sys/param.h> 33 1.9.2.2 skrll #include <sys/systm.h> 34 1.9.2.2 skrll 35 1.9.2.2 skrll #include <dev/pci/pcivar.h> 36 1.9.2.2 skrll #include <dev/pci/pcidevs.h> 37 1.9.2.2 skrll #include <dev/pci/pciidereg.h> 38 1.9.2.2 skrll #include <dev/pci/pciidevar.h> 39 1.9.2.2 skrll #include <dev/pci/pciide_piix_reg.h> 40 1.9.2.2 skrll 41 1.9.2.2 skrll static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 1.9.2.3 skrll static void piix_setup_channel(struct ata_channel *); 43 1.9.2.3 skrll static void piix3_4_setup_channel(struct ata_channel *); 44 1.9.2.2 skrll static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 1.9.2.2 skrll static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 1.9.2.2 skrll static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 1.9.2.2 skrll static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 1.9.2.2 skrll 49 1.9.2.8 skrll static void piixide_powerhook(int, void *); 50 1.9.2.2 skrll static int piixide_match(struct device *, struct cfdata *, void *); 51 1.9.2.2 skrll static void piixide_attach(struct device *, struct device *, void *); 52 1.9.2.2 skrll 53 1.9.2.2 skrll static const struct pciide_product_desc pciide_intel_products[] = { 54 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82092AA, 55 1.9.2.2 skrll 0, 56 1.9.2.2 skrll "Intel 82092AA IDE controller", 57 1.9.2.2 skrll default_chip_map, 58 1.9.2.2 skrll }, 59 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82371FB_IDE, 60 1.9.2.2 skrll 0, 61 1.9.2.2 skrll "Intel 82371FB IDE controller (PIIX)", 62 1.9.2.2 skrll piix_chip_map, 63 1.9.2.2 skrll }, 64 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82371SB_IDE, 65 1.9.2.2 skrll 0, 66 1.9.2.2 skrll "Intel 82371SB IDE Interface (PIIX3)", 67 1.9.2.2 skrll piix_chip_map, 68 1.9.2.2 skrll }, 69 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82371AB_IDE, 70 1.9.2.2 skrll 0, 71 1.9.2.2 skrll "Intel 82371AB IDE controller (PIIX4)", 72 1.9.2.2 skrll piix_chip_map, 73 1.9.2.2 skrll }, 74 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82440MX_IDE, 75 1.9.2.2 skrll 0, 76 1.9.2.2 skrll "Intel 82440MX IDE controller", 77 1.9.2.2 skrll piix_chip_map 78 1.9.2.2 skrll }, 79 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801AA_IDE, 80 1.9.2.2 skrll 0, 81 1.9.2.2 skrll "Intel 82801AA IDE Controller (ICH)", 82 1.9.2.2 skrll piix_chip_map, 83 1.9.2.2 skrll }, 84 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801AB_IDE, 85 1.9.2.2 skrll 0, 86 1.9.2.2 skrll "Intel 82801AB IDE Controller (ICH0)", 87 1.9.2.2 skrll piix_chip_map, 88 1.9.2.2 skrll }, 89 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801BA_IDE, 90 1.9.2.2 skrll 0, 91 1.9.2.2 skrll "Intel 82801BA IDE Controller (ICH2)", 92 1.9.2.2 skrll piix_chip_map, 93 1.9.2.2 skrll }, 94 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801BAM_IDE, 95 1.9.2.2 skrll 0, 96 1.9.2.2 skrll "Intel 82801BAM IDE Controller (ICH2-M)", 97 1.9.2.2 skrll piix_chip_map, 98 1.9.2.2 skrll }, 99 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801CA_IDE_1, 100 1.9.2.2 skrll 0, 101 1.9.2.2 skrll "Intel 82801CA IDE Controller (ICH3)", 102 1.9.2.2 skrll piix_chip_map, 103 1.9.2.2 skrll }, 104 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801CA_IDE_2, 105 1.9.2.2 skrll 0, 106 1.9.2.2 skrll "Intel 82801CA IDE Controller (ICH3)", 107 1.9.2.2 skrll piix_chip_map, 108 1.9.2.2 skrll }, 109 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801DB_IDE, 110 1.9.2.2 skrll 0, 111 1.9.2.2 skrll "Intel 82801DB IDE Controller (ICH4)", 112 1.9.2.2 skrll piix_chip_map, 113 1.9.2.2 skrll }, 114 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801DBM_IDE, 115 1.9.2.2 skrll 0, 116 1.9.2.2 skrll "Intel 82801DBM IDE Controller (ICH4-M)", 117 1.9.2.2 skrll piix_chip_map, 118 1.9.2.2 skrll }, 119 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801EB_IDE, 120 1.9.2.2 skrll 0, 121 1.9.2.2 skrll "Intel 82801EB IDE Controller (ICH5)", 122 1.9.2.2 skrll piix_chip_map, 123 1.9.2.2 skrll }, 124 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801EB_SATA, 125 1.9.2.2 skrll 0, 126 1.9.2.2 skrll "Intel 82801EB Serial ATA Controller", 127 1.9.2.2 skrll piixsata_chip_map, 128 1.9.2.2 skrll }, 129 1.9.2.2 skrll { PCI_PRODUCT_INTEL_82801ER_SATA, 130 1.9.2.2 skrll 0, 131 1.9.2.2 skrll "Intel 82801ER Serial ATA/Raid Controller", 132 1.9.2.2 skrll piixsata_chip_map, 133 1.9.2.2 skrll }, 134 1.9.2.2 skrll { PCI_PRODUCT_INTEL_6300ESB_IDE, 135 1.9.2.2 skrll 0, 136 1.9.2.2 skrll "Intel 6300ESB IDE Controller (ICH5)", 137 1.9.2.2 skrll piix_chip_map, 138 1.9.2.2 skrll }, 139 1.9.2.2 skrll { PCI_PRODUCT_INTEL_6300ESB_SATA, 140 1.9.2.2 skrll 0, 141 1.9.2.2 skrll "Intel 6300ESB Serial ATA Controller", 142 1.9.2.2 skrll piixsata_chip_map, 143 1.9.2.2 skrll }, 144 1.9.2.7 skrll { PCI_PRODUCT_INTEL_82801FB_IDE, 145 1.9.2.7 skrll 0, 146 1.9.2.7 skrll "Intel 82801FB IDE Controller (ICH6)", 147 1.9.2.7 skrll piix_chip_map, 148 1.9.2.7 skrll }, 149 1.9.2.6 skrll { PCI_PRODUCT_INTEL_82801FB_SATA, 150 1.9.2.6 skrll 0, 151 1.9.2.6 skrll "Intel 82801FB Serial ATA/Raid Controller", 152 1.9.2.6 skrll piixsata_chip_map, 153 1.9.2.6 skrll }, 154 1.9.2.6 skrll { PCI_PRODUCT_INTEL_82801FR_SATA, 155 1.9.2.6 skrll 0, 156 1.9.2.6 skrll "Intel 82801FR Serial ATA/Raid Controller", 157 1.9.2.6 skrll piixsata_chip_map, 158 1.9.2.6 skrll }, 159 1.9.2.2 skrll { 0, 160 1.9.2.2 skrll 0, 161 1.9.2.2 skrll NULL, 162 1.9.2.2 skrll NULL 163 1.9.2.2 skrll } 164 1.9.2.2 skrll }; 165 1.9.2.2 skrll 166 1.9.2.2 skrll CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 167 1.9.2.2 skrll piixide_match, piixide_attach, NULL, NULL); 168 1.9.2.2 skrll 169 1.9.2.2 skrll static int 170 1.9.2.2 skrll piixide_match(struct device *parent, struct cfdata *match, void *aux) 171 1.9.2.2 skrll { 172 1.9.2.2 skrll struct pci_attach_args *pa = aux; 173 1.9.2.2 skrll 174 1.9.2.2 skrll if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 175 1.9.2.2 skrll if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 176 1.9.2.2 skrll return (2); 177 1.9.2.2 skrll } 178 1.9.2.2 skrll return (0); 179 1.9.2.2 skrll } 180 1.9.2.2 skrll 181 1.9.2.2 skrll static void 182 1.9.2.2 skrll piixide_attach(struct device *parent, struct device *self, void *aux) 183 1.9.2.2 skrll { 184 1.9.2.2 skrll struct pci_attach_args *pa = aux; 185 1.9.2.2 skrll struct pciide_softc *sc = (struct pciide_softc *)self; 186 1.9.2.2 skrll 187 1.9.2.2 skrll pciide_common_attach(sc, pa, 188 1.9.2.2 skrll pciide_lookup_product(pa->pa_id, pciide_intel_products)); 189 1.9.2.2 skrll 190 1.9.2.8 skrll /* Setup our powerhook */ 191 1.9.2.8 skrll sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc); 192 1.9.2.8 skrll if (sc->sc_powerhook == NULL) 193 1.9.2.8 skrll printf("%s: WARNING: unable to establish PCI power hook\n", 194 1.9.2.8 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 195 1.9.2.8 skrll } 196 1.9.2.8 skrll 197 1.9.2.8 skrll static void 198 1.9.2.8 skrll piixide_powerhook(int why, void *hdl) 199 1.9.2.8 skrll { 200 1.9.2.8 skrll struct pciide_softc *sc = (struct pciide_softc *)hdl; 201 1.9.2.8 skrll 202 1.9.2.8 skrll switch (why) { 203 1.9.2.8 skrll case PWR_SUSPEND: 204 1.9.2.8 skrll case PWR_STANDBY: 205 1.9.2.8 skrll pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 206 1.9.2.8 skrll break; 207 1.9.2.8 skrll case PWR_RESUME: 208 1.9.2.8 skrll pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 209 1.9.2.8 skrll break; 210 1.9.2.8 skrll case PWR_SOFTSUSPEND: 211 1.9.2.8 skrll case PWR_SOFTSTANDBY: 212 1.9.2.8 skrll case PWR_SOFTRESUME: 213 1.9.2.8 skrll break; 214 1.9.2.8 skrll } 215 1.9.2.8 skrll 216 1.9.2.8 skrll return; 217 1.9.2.2 skrll } 218 1.9.2.2 skrll 219 1.9.2.2 skrll static void 220 1.9.2.2 skrll piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 221 1.9.2.2 skrll { 222 1.9.2.2 skrll struct pciide_channel *cp; 223 1.9.2.2 skrll int channel; 224 1.9.2.2 skrll u_int32_t idetim; 225 1.9.2.2 skrll bus_size_t cmdsize, ctlsize; 226 1.9.2.2 skrll 227 1.9.2.2 skrll if (pciide_chipen(sc, pa) == 0) 228 1.9.2.2 skrll return; 229 1.9.2.2 skrll 230 1.9.2.2 skrll aprint_normal("%s: bus-master DMA support present", 231 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 232 1.9.2.2 skrll pciide_mapreg_dma(sc, pa); 233 1.9.2.2 skrll aprint_normal("\n"); 234 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 235 1.9.2.2 skrll if (sc->sc_dma_ok) { 236 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 237 1.9.2.2 skrll sc->sc_wdcdev.irqack = pciide_irqack; 238 1.9.2.2 skrll switch(sc->sc_pp->ide_product) { 239 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82371AB_IDE: 240 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82440MX_IDE: 241 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801AA_IDE: 242 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801AB_IDE: 243 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801BA_IDE: 244 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801BAM_IDE: 245 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801CA_IDE_1: 246 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801CA_IDE_2: 247 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801DB_IDE: 248 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801DBM_IDE: 249 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801EB_IDE: 250 1.9.2.2 skrll case PCI_PRODUCT_INTEL_6300ESB_IDE: 251 1.9.2.7 skrll case PCI_PRODUCT_INTEL_82801FB_IDE: 252 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 253 1.9.2.2 skrll } 254 1.9.2.2 skrll } 255 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 256 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 257 1.9.2.2 skrll switch(sc->sc_pp->ide_product) { 258 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801AA_IDE: 259 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 260 1.9.2.2 skrll break; 261 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801BA_IDE: 262 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801BAM_IDE: 263 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801CA_IDE_1: 264 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801CA_IDE_2: 265 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801DB_IDE: 266 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801DBM_IDE: 267 1.9.2.2 skrll case PCI_PRODUCT_INTEL_82801EB_IDE: 268 1.9.2.2 skrll case PCI_PRODUCT_INTEL_6300ESB_IDE: 269 1.9.2.7 skrll case PCI_PRODUCT_INTEL_82801FB_IDE: 270 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 271 1.9.2.2 skrll break; 272 1.9.2.2 skrll default: 273 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 274 1.9.2.2 skrll } 275 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 276 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 277 1.9.2.2 skrll else 278 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 279 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 280 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 281 1.9.2.2 skrll 282 1.9.2.3 skrll ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 283 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 284 1.9.2.2 skrll DEBUG_PROBE); 285 1.9.2.2 skrll if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 286 1.9.2.3 skrll ATADEBUG_PRINT((", sidetim=0x%x", 287 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 288 1.9.2.2 skrll DEBUG_PROBE); 289 1.9.2.3 skrll if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 290 1.9.2.3 skrll ATADEBUG_PRINT((", udamreg 0x%x", 291 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 292 1.9.2.2 skrll DEBUG_PROBE); 293 1.9.2.2 skrll } 294 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 295 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 296 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 297 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 298 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 299 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 300 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 301 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 302 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 303 1.9.2.7 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 304 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 305 1.9.2.3 skrll ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 306 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 307 1.9.2.2 skrll DEBUG_PROBE); 308 1.9.2.2 skrll } 309 1.9.2.2 skrll 310 1.9.2.2 skrll } 311 1.9.2.3 skrll ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 312 1.9.2.2 skrll 313 1.9.2.3 skrll wdc_allocate_regs(&sc->sc_wdcdev); 314 1.9.2.3 skrll 315 1.9.2.3 skrll for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 316 1.9.2.3 skrll channel++) { 317 1.9.2.2 skrll cp = &sc->pciide_channels[channel]; 318 1.9.2.2 skrll /* PIIX is compat-only */ 319 1.9.2.2 skrll if (pciide_chansetup(sc, channel, 0) == 0) 320 1.9.2.2 skrll continue; 321 1.9.2.2 skrll idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 322 1.9.2.2 skrll if ((PIIX_IDETIM_READ(idetim, channel) & 323 1.9.2.2 skrll PIIX_IDETIM_IDE) == 0) { 324 1.9.2.2 skrll #if 1 325 1.9.2.2 skrll aprint_normal("%s: %s channel ignored (disabled)\n", 326 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 327 1.9.2.3 skrll cp->ata_channel.ch_flags |= ATACH_DISABLED; 328 1.9.2.2 skrll continue; 329 1.9.2.2 skrll #else 330 1.9.2.2 skrll pcireg_t interface; 331 1.9.2.2 skrll 332 1.9.2.2 skrll idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 333 1.9.2.2 skrll channel); 334 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 335 1.9.2.2 skrll idetim); 336 1.9.2.2 skrll interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 337 1.9.2.2 skrll sc->sc_tag, PCI_CLASS_REG)); 338 1.9.2.2 skrll aprint_normal("channel %d idetim=%08x interface=%02x\n", 339 1.9.2.2 skrll channel, idetim, interface); 340 1.9.2.2 skrll #endif 341 1.9.2.2 skrll } 342 1.9.2.2 skrll /* PIIX are compat-only pciide devices */ 343 1.9.2.2 skrll pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 344 1.9.2.2 skrll } 345 1.9.2.2 skrll 346 1.9.2.3 skrll ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 347 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 348 1.9.2.2 skrll DEBUG_PROBE); 349 1.9.2.2 skrll if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 350 1.9.2.3 skrll ATADEBUG_PRINT((", sidetim=0x%x", 351 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 352 1.9.2.2 skrll DEBUG_PROBE); 353 1.9.2.3 skrll if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 354 1.9.2.3 skrll ATADEBUG_PRINT((", udamreg 0x%x", 355 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 356 1.9.2.2 skrll DEBUG_PROBE); 357 1.9.2.2 skrll } 358 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 359 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 360 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 361 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 362 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 363 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 364 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 365 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 366 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 367 1.9.2.7 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 368 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 369 1.9.2.3 skrll ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 370 1.9.2.2 skrll pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 371 1.9.2.2 skrll DEBUG_PROBE); 372 1.9.2.2 skrll } 373 1.9.2.2 skrll } 374 1.9.2.3 skrll ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 375 1.9.2.2 skrll } 376 1.9.2.2 skrll 377 1.9.2.2 skrll static void 378 1.9.2.3 skrll piix_setup_channel(struct ata_channel *chp) 379 1.9.2.2 skrll { 380 1.9.2.2 skrll u_int8_t mode[2], drive; 381 1.9.2.2 skrll u_int32_t oidetim, idetim, idedma_ctl; 382 1.9.2.3 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 383 1.9.2.3 skrll struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 384 1.9.2.3 skrll struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 385 1.9.2.2 skrll 386 1.9.2.2 skrll oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 387 1.9.2.2 skrll idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 388 1.9.2.2 skrll idedma_ctl = 0; 389 1.9.2.2 skrll 390 1.9.2.2 skrll /* set up new idetim: Enable IDE registers decode */ 391 1.9.2.2 skrll idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 392 1.9.2.2 skrll chp->ch_channel); 393 1.9.2.2 skrll 394 1.9.2.2 skrll /* setup DMA */ 395 1.9.2.2 skrll pciide_channel_dma_setup(cp); 396 1.9.2.2 skrll 397 1.9.2.2 skrll /* 398 1.9.2.2 skrll * Here we have to mess up with drives mode: PIIX can't have 399 1.9.2.2 skrll * different timings for master and slave drives. 400 1.9.2.2 skrll * We need to find the best combination. 401 1.9.2.2 skrll */ 402 1.9.2.2 skrll 403 1.9.2.2 skrll /* If both drives supports DMA, take the lower mode */ 404 1.9.2.2 skrll if ((drvp[0].drive_flags & DRIVE_DMA) && 405 1.9.2.2 skrll (drvp[1].drive_flags & DRIVE_DMA)) { 406 1.9.2.2 skrll mode[0] = mode[1] = 407 1.9.2.2 skrll min(drvp[0].DMA_mode, drvp[1].DMA_mode); 408 1.9.2.2 skrll drvp[0].DMA_mode = mode[0]; 409 1.9.2.2 skrll drvp[1].DMA_mode = mode[1]; 410 1.9.2.2 skrll goto ok; 411 1.9.2.2 skrll } 412 1.9.2.2 skrll /* 413 1.9.2.2 skrll * If only one drive supports DMA, use its mode, and 414 1.9.2.2 skrll * put the other one in PIO mode 0 if mode not compatible 415 1.9.2.2 skrll */ 416 1.9.2.2 skrll if (drvp[0].drive_flags & DRIVE_DMA) { 417 1.9.2.2 skrll mode[0] = drvp[0].DMA_mode; 418 1.9.2.2 skrll mode[1] = drvp[1].PIO_mode; 419 1.9.2.2 skrll if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 420 1.9.2.2 skrll piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 421 1.9.2.2 skrll mode[1] = drvp[1].PIO_mode = 0; 422 1.9.2.2 skrll goto ok; 423 1.9.2.2 skrll } 424 1.9.2.2 skrll if (drvp[1].drive_flags & DRIVE_DMA) { 425 1.9.2.2 skrll mode[1] = drvp[1].DMA_mode; 426 1.9.2.2 skrll mode[0] = drvp[0].PIO_mode; 427 1.9.2.2 skrll if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 428 1.9.2.2 skrll piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 429 1.9.2.2 skrll mode[0] = drvp[0].PIO_mode = 0; 430 1.9.2.2 skrll goto ok; 431 1.9.2.2 skrll } 432 1.9.2.2 skrll /* 433 1.9.2.2 skrll * If both drives are not DMA, takes the lower mode, unless 434 1.9.2.2 skrll * one of them is PIO mode < 2 435 1.9.2.2 skrll */ 436 1.9.2.2 skrll if (drvp[0].PIO_mode < 2) { 437 1.9.2.2 skrll mode[0] = drvp[0].PIO_mode = 0; 438 1.9.2.2 skrll mode[1] = drvp[1].PIO_mode; 439 1.9.2.2 skrll } else if (drvp[1].PIO_mode < 2) { 440 1.9.2.2 skrll mode[1] = drvp[1].PIO_mode = 0; 441 1.9.2.2 skrll mode[0] = drvp[0].PIO_mode; 442 1.9.2.2 skrll } else { 443 1.9.2.2 skrll mode[0] = mode[1] = 444 1.9.2.2 skrll min(drvp[1].PIO_mode, drvp[0].PIO_mode); 445 1.9.2.2 skrll drvp[0].PIO_mode = mode[0]; 446 1.9.2.2 skrll drvp[1].PIO_mode = mode[1]; 447 1.9.2.2 skrll } 448 1.9.2.2 skrll ok: /* The modes are setup */ 449 1.9.2.2 skrll for (drive = 0; drive < 2; drive++) { 450 1.9.2.2 skrll if (drvp[drive].drive_flags & DRIVE_DMA) { 451 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 452 1.9.2.2 skrll mode[drive], 1, chp->ch_channel); 453 1.9.2.2 skrll goto end; 454 1.9.2.2 skrll } 455 1.9.2.2 skrll } 456 1.9.2.2 skrll /* If we are there, none of the drives are DMA */ 457 1.9.2.2 skrll if (mode[0] >= 2) 458 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 459 1.9.2.2 skrll mode[0], 0, chp->ch_channel); 460 1.9.2.9 skrll else 461 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 462 1.9.2.2 skrll mode[1], 0, chp->ch_channel); 463 1.9.2.2 skrll end: /* 464 1.9.2.2 skrll * timing mode is now set up in the controller. Enable 465 1.9.2.2 skrll * it per-drive 466 1.9.2.2 skrll */ 467 1.9.2.2 skrll for (drive = 0; drive < 2; drive++) { 468 1.9.2.2 skrll /* If no drive, skip */ 469 1.9.2.2 skrll if ((drvp[drive].drive_flags & DRIVE) == 0) 470 1.9.2.2 skrll continue; 471 1.9.2.2 skrll idetim |= piix_setup_idetim_drvs(&drvp[drive]); 472 1.9.2.2 skrll if (drvp[drive].drive_flags & DRIVE_DMA) 473 1.9.2.2 skrll idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 474 1.9.2.2 skrll } 475 1.9.2.2 skrll if (idedma_ctl != 0) { 476 1.9.2.2 skrll /* Add software bits in status register */ 477 1.9.2.2 skrll bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 478 1.9.2.2 skrll idedma_ctl); 479 1.9.2.2 skrll } 480 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 481 1.9.2.2 skrll } 482 1.9.2.2 skrll 483 1.9.2.2 skrll static void 484 1.9.2.3 skrll piix3_4_setup_channel(struct ata_channel *chp) 485 1.9.2.2 skrll { 486 1.9.2.2 skrll struct ata_drive_datas *drvp; 487 1.9.2.2 skrll u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 488 1.9.2.3 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 489 1.9.2.3 skrll struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 490 1.9.2.2 skrll struct wdc_softc *wdc = &sc->sc_wdcdev; 491 1.9.2.3 skrll int drive, s; 492 1.9.2.2 skrll int channel = chp->ch_channel; 493 1.9.2.2 skrll 494 1.9.2.2 skrll oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 495 1.9.2.2 skrll sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 496 1.9.2.2 skrll udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 497 1.9.2.2 skrll ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 498 1.9.2.2 skrll idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 499 1.9.2.2 skrll sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 500 1.9.2.2 skrll PIIX_SIDETIM_RTC_MASK(channel)); 501 1.9.2.2 skrll idedma_ctl = 0; 502 1.9.2.2 skrll 503 1.9.2.2 skrll /* set up new idetim: Enable IDE registers decode */ 504 1.9.2.2 skrll idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 505 1.9.2.2 skrll 506 1.9.2.2 skrll /* setup DMA if needed */ 507 1.9.2.2 skrll pciide_channel_dma_setup(cp); 508 1.9.2.2 skrll 509 1.9.2.2 skrll for (drive = 0; drive < 2; drive++) { 510 1.9.2.2 skrll udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 511 1.9.2.2 skrll PIIX_UDMATIM_SET(0x3, channel, drive)); 512 1.9.2.2 skrll drvp = &chp->ch_drive[drive]; 513 1.9.2.2 skrll /* If no drive, skip */ 514 1.9.2.2 skrll if ((drvp->drive_flags & DRIVE) == 0) 515 1.9.2.2 skrll continue; 516 1.9.2.2 skrll if (((drvp->drive_flags & DRIVE_DMA) == 0 && 517 1.9.2.2 skrll (drvp->drive_flags & DRIVE_UDMA) == 0)) 518 1.9.2.2 skrll goto pio; 519 1.9.2.2 skrll 520 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 521 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 522 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 523 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 524 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 525 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 526 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 527 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 528 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 529 1.9.2.7 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 530 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 531 1.9.2.2 skrll ideconf |= PIIX_CONFIG_PINGPONG; 532 1.9.2.2 skrll } 533 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 534 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 535 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 536 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 537 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 538 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 539 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 540 1.9.2.7 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 541 1.9.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 542 1.9.2.2 skrll /* setup Ultra/100 */ 543 1.9.2.2 skrll if (drvp->UDMA_mode > 2 && 544 1.9.2.2 skrll (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 545 1.9.2.2 skrll drvp->UDMA_mode = 2; 546 1.9.2.2 skrll if (drvp->UDMA_mode > 4) { 547 1.9.2.2 skrll ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 548 1.9.2.2 skrll } else { 549 1.9.2.2 skrll ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 550 1.9.2.2 skrll if (drvp->UDMA_mode > 2) { 551 1.9.2.2 skrll ideconf |= PIIX_CONFIG_UDMA66(channel, 552 1.9.2.2 skrll drive); 553 1.9.2.2 skrll } else { 554 1.9.2.2 skrll ideconf &= ~PIIX_CONFIG_UDMA66(channel, 555 1.9.2.2 skrll drive); 556 1.9.2.2 skrll } 557 1.9.2.2 skrll } 558 1.9.2.2 skrll } 559 1.9.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 560 1.9.2.2 skrll /* setup Ultra/66 */ 561 1.9.2.2 skrll if (drvp->UDMA_mode > 2 && 562 1.9.2.2 skrll (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 563 1.9.2.2 skrll drvp->UDMA_mode = 2; 564 1.9.2.2 skrll if (drvp->UDMA_mode > 2) 565 1.9.2.2 skrll ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 566 1.9.2.2 skrll else 567 1.9.2.2 skrll ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 568 1.9.2.2 skrll } 569 1.9.2.3 skrll if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 570 1.9.2.2 skrll (drvp->drive_flags & DRIVE_UDMA)) { 571 1.9.2.2 skrll /* use Ultra/DMA */ 572 1.9.2.3 skrll s = splbio(); 573 1.9.2.2 skrll drvp->drive_flags &= ~DRIVE_DMA; 574 1.9.2.3 skrll splx(s); 575 1.9.2.2 skrll udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 576 1.9.2.2 skrll udmareg |= PIIX_UDMATIM_SET( 577 1.9.2.2 skrll piix4_sct_udma[drvp->UDMA_mode], channel, drive); 578 1.9.2.2 skrll } else { 579 1.9.2.2 skrll /* use Multiword DMA */ 580 1.9.2.3 skrll s = splbio(); 581 1.9.2.2 skrll drvp->drive_flags &= ~DRIVE_UDMA; 582 1.9.2.3 skrll splx(s); 583 1.9.2.2 skrll if (drive == 0) { 584 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 585 1.9.2.2 skrll drvp->DMA_mode, 1, channel); 586 1.9.2.2 skrll } else { 587 1.9.2.2 skrll sidetim |= piix_setup_sidetim_timings( 588 1.9.2.2 skrll drvp->DMA_mode, 1, channel); 589 1.9.2.2 skrll idetim =PIIX_IDETIM_SET(idetim, 590 1.9.2.2 skrll PIIX_IDETIM_SITRE, channel); 591 1.9.2.2 skrll } 592 1.9.2.2 skrll } 593 1.9.2.2 skrll idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 594 1.9.2.9 skrll 595 1.9.2.2 skrll pio: /* use PIO mode */ 596 1.9.2.2 skrll idetim |= piix_setup_idetim_drvs(drvp); 597 1.9.2.2 skrll if (drive == 0) { 598 1.9.2.2 skrll idetim |= piix_setup_idetim_timings( 599 1.9.2.2 skrll drvp->PIO_mode, 0, channel); 600 1.9.2.2 skrll } else { 601 1.9.2.2 skrll sidetim |= piix_setup_sidetim_timings( 602 1.9.2.2 skrll drvp->PIO_mode, 0, channel); 603 1.9.2.2 skrll idetim =PIIX_IDETIM_SET(idetim, 604 1.9.2.2 skrll PIIX_IDETIM_SITRE, channel); 605 1.9.2.2 skrll } 606 1.9.2.2 skrll } 607 1.9.2.2 skrll if (idedma_ctl != 0) { 608 1.9.2.2 skrll /* Add software bits in status register */ 609 1.9.2.2 skrll bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 610 1.9.2.2 skrll idedma_ctl); 611 1.9.2.2 skrll } 612 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 613 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 614 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 615 1.9.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 616 1.9.2.2 skrll } 617 1.9.2.2 skrll 618 1.9.2.2 skrll 619 1.9.2.2 skrll /* setup ISP and RTC fields, based on mode */ 620 1.9.2.2 skrll static u_int32_t 621 1.9.2.2 skrll piix_setup_idetim_timings(mode, dma, channel) 622 1.9.2.2 skrll u_int8_t mode; 623 1.9.2.2 skrll u_int8_t dma; 624 1.9.2.2 skrll u_int8_t channel; 625 1.9.2.2 skrll { 626 1.9.2.9 skrll 627 1.9.2.2 skrll if (dma) 628 1.9.2.2 skrll return PIIX_IDETIM_SET(0, 629 1.9.2.9 skrll PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 630 1.9.2.2 skrll PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 631 1.9.2.2 skrll channel); 632 1.9.2.9 skrll else 633 1.9.2.2 skrll return PIIX_IDETIM_SET(0, 634 1.9.2.9 skrll PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 635 1.9.2.2 skrll PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 636 1.9.2.2 skrll channel); 637 1.9.2.2 skrll } 638 1.9.2.2 skrll 639 1.9.2.2 skrll /* setup DTE, PPE, IE and TIME field based on PIO mode */ 640 1.9.2.2 skrll static u_int32_t 641 1.9.2.2 skrll piix_setup_idetim_drvs(drvp) 642 1.9.2.2 skrll struct ata_drive_datas *drvp; 643 1.9.2.2 skrll { 644 1.9.2.2 skrll u_int32_t ret = 0; 645 1.9.2.3 skrll struct ata_channel *chp = drvp->chnl_softc; 646 1.9.2.2 skrll u_int8_t channel = chp->ch_channel; 647 1.9.2.2 skrll u_int8_t drive = drvp->drive; 648 1.9.2.2 skrll 649 1.9.2.2 skrll /* 650 1.9.2.2 skrll * If drive is using UDMA, timings setups are independant 651 1.9.2.2 skrll * So just check DMA and PIO here. 652 1.9.2.2 skrll */ 653 1.9.2.2 skrll if (drvp->drive_flags & DRIVE_DMA) { 654 1.9.2.2 skrll /* if mode = DMA mode 0, use compatible timings */ 655 1.9.2.2 skrll if ((drvp->drive_flags & DRIVE_DMA) && 656 1.9.2.2 skrll drvp->DMA_mode == 0) { 657 1.9.2.2 skrll drvp->PIO_mode = 0; 658 1.9.2.2 skrll return ret; 659 1.9.2.2 skrll } 660 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 661 1.9.2.2 skrll /* 662 1.9.2.2 skrll * PIO and DMA timings are the same, use fast timings for PIO 663 1.9.2.2 skrll * too, else use compat timings. 664 1.9.2.2 skrll */ 665 1.9.2.2 skrll if ((piix_isp_pio[drvp->PIO_mode] != 666 1.9.2.2 skrll piix_isp_dma[drvp->DMA_mode]) || 667 1.9.2.2 skrll (piix_rtc_pio[drvp->PIO_mode] != 668 1.9.2.2 skrll piix_rtc_dma[drvp->DMA_mode])) 669 1.9.2.2 skrll drvp->PIO_mode = 0; 670 1.9.2.2 skrll /* if PIO mode <= 2, use compat timings for PIO */ 671 1.9.2.2 skrll if (drvp->PIO_mode <= 2) { 672 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 673 1.9.2.2 skrll channel); 674 1.9.2.2 skrll return ret; 675 1.9.2.2 skrll } 676 1.9.2.2 skrll } 677 1.9.2.2 skrll 678 1.9.2.2 skrll /* 679 1.9.2.2 skrll * Now setup PIO modes. If mode < 2, use compat timings. 680 1.9.2.2 skrll * Else enable fast timings. Enable IORDY and prefetch/post 681 1.9.2.2 skrll * if PIO mode >= 3. 682 1.9.2.2 skrll */ 683 1.9.2.2 skrll 684 1.9.2.2 skrll if (drvp->PIO_mode < 2) 685 1.9.2.2 skrll return ret; 686 1.9.2.2 skrll 687 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 688 1.9.2.2 skrll if (drvp->PIO_mode >= 3) { 689 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 690 1.9.2.2 skrll ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 691 1.9.2.2 skrll } 692 1.9.2.2 skrll return ret; 693 1.9.2.2 skrll } 694 1.9.2.2 skrll 695 1.9.2.2 skrll /* setup values in SIDETIM registers, based on mode */ 696 1.9.2.2 skrll static u_int32_t 697 1.9.2.2 skrll piix_setup_sidetim_timings(mode, dma, channel) 698 1.9.2.2 skrll u_int8_t mode; 699 1.9.2.2 skrll u_int8_t dma; 700 1.9.2.2 skrll u_int8_t channel; 701 1.9.2.2 skrll { 702 1.9.2.2 skrll if (dma) 703 1.9.2.2 skrll return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 704 1.9.2.2 skrll PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 705 1.9.2.9 skrll else 706 1.9.2.2 skrll return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 707 1.9.2.2 skrll PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 708 1.9.2.2 skrll } 709 1.9.2.2 skrll 710 1.9.2.2 skrll static void 711 1.9.2.2 skrll piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 712 1.9.2.2 skrll { 713 1.9.2.2 skrll struct pciide_channel *cp; 714 1.9.2.2 skrll bus_size_t cmdsize, ctlsize; 715 1.9.2.2 skrll pcireg_t interface; 716 1.9.2.2 skrll int channel; 717 1.9.2.2 skrll 718 1.9.2.2 skrll if (pciide_chipen(sc, pa) == 0) 719 1.9.2.2 skrll return; 720 1.9.2.2 skrll 721 1.9.2.2 skrll aprint_normal("%s: bus-master DMA support present", 722 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 723 1.9.2.2 skrll pciide_mapreg_dma(sc, pa); 724 1.9.2.2 skrll aprint_normal("\n"); 725 1.9.2.2 skrll 726 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 727 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 728 1.9.2.2 skrll if (sc->sc_dma_ok) { 729 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 730 1.9.2.2 skrll sc->sc_wdcdev.irqack = pciide_irqack; 731 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 732 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 733 1.9.2.2 skrll } 734 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 735 1.9.2.2 skrll 736 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 737 1.9.2.3 skrll sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 738 1.9.2.2 skrll 739 1.9.2.2 skrll interface = PCI_INTERFACE(pa->pa_class); 740 1.9.2.2 skrll 741 1.9.2.3 skrll wdc_allocate_regs(&sc->sc_wdcdev); 742 1.9.2.3 skrll 743 1.9.2.3 skrll for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 744 1.9.2.3 skrll channel++) { 745 1.9.2.2 skrll cp = &sc->pciide_channels[channel]; 746 1.9.2.2 skrll if (pciide_chansetup(sc, channel, interface) == 0) 747 1.9.2.2 skrll continue; 748 1.9.2.2 skrll pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 749 1.9.2.2 skrll pciide_pci_intr); 750 1.9.2.2 skrll } 751 1.9.2.2 skrll } 752
Indexes created Thu Oct 16 14:10:15 GMT 2025