piixide.c revision 1.1
1 /* $NetBSD: piixide.c,v 1.1 2003/10/08 11:51:59 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 45 void piix_setup_channel __P((struct channel_softc*)); 46 void piix3_4_setup_channel __P((struct channel_softc*)); 47 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 48 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 49 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 50 void artisea_chip_map __P((struct pciide_softc*, struct pci_attach_args *)); 51 int piixide_match __P((struct device *, struct cfdata *, void *)); 52 void piixide_attach __P((struct device *, struct device *, void *)); 53 54 const struct pciide_product_desc pciide_intel_products[] = { 55 { PCI_PRODUCT_INTEL_82092AA, 56 0, 57 "Intel 82092AA IDE controller", 58 default_chip_map, 59 }, 60 { PCI_PRODUCT_INTEL_82371FB_IDE, 61 0, 62 "Intel 82371FB IDE controller (PIIX)", 63 piix_chip_map, 64 }, 65 { PCI_PRODUCT_INTEL_82371SB_IDE, 66 0, 67 "Intel 82371SB IDE Interface (PIIX3)", 68 piix_chip_map, 69 }, 70 { PCI_PRODUCT_INTEL_82371AB_IDE, 71 0, 72 "Intel 82371AB IDE controller (PIIX4)", 73 piix_chip_map, 74 }, 75 { PCI_PRODUCT_INTEL_82440MX_IDE, 76 0, 77 "Intel 82440MX IDE controller", 78 piix_chip_map 79 }, 80 { PCI_PRODUCT_INTEL_82801AA_IDE, 81 0, 82 "Intel 82801AA IDE Controller (ICH)", 83 piix_chip_map, 84 }, 85 { PCI_PRODUCT_INTEL_82801AB_IDE, 86 0, 87 "Intel 82801AB IDE Controller (ICH0)", 88 piix_chip_map, 89 }, 90 { PCI_PRODUCT_INTEL_82801BA_IDE, 91 0, 92 "Intel 82801BA IDE Controller (ICH2)", 93 piix_chip_map, 94 }, 95 { PCI_PRODUCT_INTEL_82801BAM_IDE, 96 0, 97 "Intel 82801BAM IDE Controller (ICH2-M)", 98 piix_chip_map, 99 }, 100 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 101 0, 102 "Intel 82801CA IDE Controller (ICH3)", 103 piix_chip_map, 104 }, 105 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 106 0, 107 "Intel 82801CA IDE Controller (ICH3)", 108 piix_chip_map, 109 }, 110 { PCI_PRODUCT_INTEL_82801DB_IDE, 111 0, 112 "Intel 82801DB IDE Controller (ICH4)", 113 piix_chip_map, 114 }, 115 { PCI_PRODUCT_INTEL_82801DBM_IDE, 116 0, 117 "Intel 82801DBM IDE Controller (ICH4-M)", 118 piix_chip_map, 119 }, 120 { PCI_PRODUCT_INTEL_82801EB_IDE, 121 0, 122 "Intel 82801EB IDE Controller (ICH5)", 123 piix_chip_map, 124 }, 125 { PCI_PRODUCT_INTEL_31244, 126 0, 127 "Intel 31244 Serial ATA Controller", 128 artisea_chip_map, 129 }, 130 { PCI_PRODUCT_INTEL_82801EB_SATA, 131 0, 132 "Intel 82801EB Serial ATA Controller", 133 artisea_chip_map, 134 }, 135 { 0, 136 0, 137 NULL, 138 NULL 139 } 140 }; 141 142 143 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 144 piixide_match, piixide_attach, NULL, NULL); 145 146 int 147 piixide_match(parent, match, aux) 148 struct device *parent; 149 struct cfdata *match; 150 void *aux; 151 { 152 struct pci_attach_args *pa = aux; 153 154 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 155 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 156 return (2); 157 } 158 return (0); 159 } 160 161 void 162 piixide_attach(parent, self, aux) 163 struct device *parent, *self; 164 void *aux; 165 { 166 struct pci_attach_args *pa = aux; 167 struct pciide_softc *sc = (struct pciide_softc *)self; 168 169 pciide_common_attach(sc, pa, 170 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 171 172 } 173 174 void 175 piix_chip_map(sc, pa) 176 struct pciide_softc *sc; 177 struct pci_attach_args *pa; 178 { 179 struct pciide_channel *cp; 180 int channel; 181 u_int32_t idetim; 182 bus_size_t cmdsize, ctlsize; 183 184 if (pciide_chipen(sc, pa) == 0) 185 return; 186 187 aprint_normal("%s: bus-master DMA support present", 188 sc->sc_wdcdev.sc_dev.dv_xname); 189 pciide_mapreg_dma(sc, pa); 190 aprint_normal("\n"); 191 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 192 WDC_CAPABILITY_MODE; 193 if (sc->sc_dma_ok) { 194 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 195 sc->sc_wdcdev.irqack = pciide_irqack; 196 switch(sc->sc_pp->ide_product) { 197 case PCI_PRODUCT_INTEL_82371AB_IDE: 198 case PCI_PRODUCT_INTEL_82440MX_IDE: 199 case PCI_PRODUCT_INTEL_82801AA_IDE: 200 case PCI_PRODUCT_INTEL_82801AB_IDE: 201 case PCI_PRODUCT_INTEL_82801BA_IDE: 202 case PCI_PRODUCT_INTEL_82801BAM_IDE: 203 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 204 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 205 case PCI_PRODUCT_INTEL_82801DB_IDE: 206 case PCI_PRODUCT_INTEL_82801DBM_IDE: 207 case PCI_PRODUCT_INTEL_82801EB_IDE: 208 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 209 } 210 } 211 sc->sc_wdcdev.PIO_cap = 4; 212 sc->sc_wdcdev.DMA_cap = 2; 213 switch(sc->sc_pp->ide_product) { 214 case PCI_PRODUCT_INTEL_82801AA_IDE: 215 sc->sc_wdcdev.UDMA_cap = 4; 216 break; 217 case PCI_PRODUCT_INTEL_82801BA_IDE: 218 case PCI_PRODUCT_INTEL_82801BAM_IDE: 219 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 220 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 221 case PCI_PRODUCT_INTEL_82801DB_IDE: 222 case PCI_PRODUCT_INTEL_82801DBM_IDE: 223 case PCI_PRODUCT_INTEL_82801EB_IDE: 224 sc->sc_wdcdev.UDMA_cap = 5; 225 break; 226 default: 227 sc->sc_wdcdev.UDMA_cap = 2; 228 } 229 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 230 sc->sc_wdcdev.set_modes = piix_setup_channel; 231 else 232 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 233 sc->sc_wdcdev.channels = sc->wdc_chanarray; 234 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 235 236 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 237 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 238 DEBUG_PROBE); 239 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 240 WDCDEBUG_PRINT((", sidetim=0x%x", 241 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 242 DEBUG_PROBE); 243 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 244 WDCDEBUG_PRINT((", udamreg 0x%x", 245 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 246 DEBUG_PROBE); 247 } 248 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 249 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 250 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 251 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 252 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 253 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 254 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 255 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 256 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ) { 257 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 258 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 259 DEBUG_PROBE); 260 } 261 262 } 263 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 264 265 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 266 cp = &sc->pciide_channels[channel]; 267 /* PIIX is compat-only */ 268 if (pciide_chansetup(sc, channel, 0) == 0) 269 continue; 270 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 271 if ((PIIX_IDETIM_READ(idetim, channel) & 272 PIIX_IDETIM_IDE) == 0) { 273 #if 1 274 aprint_normal("%s: %s channel ignored (disabled)\n", 275 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 276 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 277 continue; 278 #else 279 pcireg_t interface; 280 281 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 282 channel); 283 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 284 idetim); 285 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 286 sc->sc_tag, PCI_CLASS_REG)); 287 aprint_normal("channel %d idetim=%08x interface=%02x\n", 288 channel, idetim, interface); 289 #endif 290 } 291 /* PIIX are compat-only pciide devices */ 292 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 293 } 294 295 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 296 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 297 DEBUG_PROBE); 298 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 299 WDCDEBUG_PRINT((", sidetim=0x%x", 300 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 301 DEBUG_PROBE); 302 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 303 WDCDEBUG_PRINT((", udamreg 0x%x", 304 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 305 DEBUG_PROBE); 306 } 307 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 308 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 309 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 310 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 311 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 312 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 313 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 314 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 315 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 316 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 317 DEBUG_PROBE); 318 } 319 } 320 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 321 } 322 323 void 324 piix_setup_channel(chp) 325 struct channel_softc *chp; 326 { 327 u_int8_t mode[2], drive; 328 u_int32_t oidetim, idetim, idedma_ctl; 329 struct pciide_channel *cp = (struct pciide_channel*)chp; 330 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 331 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 332 333 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 334 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 335 idedma_ctl = 0; 336 337 /* set up new idetim: Enable IDE registers decode */ 338 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 339 chp->channel); 340 341 /* setup DMA */ 342 pciide_channel_dma_setup(cp); 343 344 /* 345 * Here we have to mess up with drives mode: PIIX can't have 346 * different timings for master and slave drives. 347 * We need to find the best combination. 348 */ 349 350 /* If both drives supports DMA, take the lower mode */ 351 if ((drvp[0].drive_flags & DRIVE_DMA) && 352 (drvp[1].drive_flags & DRIVE_DMA)) { 353 mode[0] = mode[1] = 354 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 355 drvp[0].DMA_mode = mode[0]; 356 drvp[1].DMA_mode = mode[1]; 357 goto ok; 358 } 359 /* 360 * If only one drive supports DMA, use its mode, and 361 * put the other one in PIO mode 0 if mode not compatible 362 */ 363 if (drvp[0].drive_flags & DRIVE_DMA) { 364 mode[0] = drvp[0].DMA_mode; 365 mode[1] = drvp[1].PIO_mode; 366 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 367 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 368 mode[1] = drvp[1].PIO_mode = 0; 369 goto ok; 370 } 371 if (drvp[1].drive_flags & DRIVE_DMA) { 372 mode[1] = drvp[1].DMA_mode; 373 mode[0] = drvp[0].PIO_mode; 374 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 375 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 376 mode[0] = drvp[0].PIO_mode = 0; 377 goto ok; 378 } 379 /* 380 * If both drives are not DMA, takes the lower mode, unless 381 * one of them is PIO mode < 2 382 */ 383 if (drvp[0].PIO_mode < 2) { 384 mode[0] = drvp[0].PIO_mode = 0; 385 mode[1] = drvp[1].PIO_mode; 386 } else if (drvp[1].PIO_mode < 2) { 387 mode[1] = drvp[1].PIO_mode = 0; 388 mode[0] = drvp[0].PIO_mode; 389 } else { 390 mode[0] = mode[1] = 391 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 392 drvp[0].PIO_mode = mode[0]; 393 drvp[1].PIO_mode = mode[1]; 394 } 395 ok: /* The modes are setup */ 396 for (drive = 0; drive < 2; drive++) { 397 if (drvp[drive].drive_flags & DRIVE_DMA) { 398 idetim |= piix_setup_idetim_timings( 399 mode[drive], 1, chp->channel); 400 goto end; 401 } 402 } 403 /* If we are there, none of the drives are DMA */ 404 if (mode[0] >= 2) 405 idetim |= piix_setup_idetim_timings( 406 mode[0], 0, chp->channel); 407 else 408 idetim |= piix_setup_idetim_timings( 409 mode[1], 0, chp->channel); 410 end: /* 411 * timing mode is now set up in the controller. Enable 412 * it per-drive 413 */ 414 for (drive = 0; drive < 2; drive++) { 415 /* If no drive, skip */ 416 if ((drvp[drive].drive_flags & DRIVE) == 0) 417 continue; 418 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 419 if (drvp[drive].drive_flags & DRIVE_DMA) 420 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 421 } 422 if (idedma_ctl != 0) { 423 /* Add software bits in status register */ 424 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 425 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 426 idedma_ctl); 427 } 428 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 429 } 430 431 void 432 piix3_4_setup_channel(chp) 433 struct channel_softc *chp; 434 { 435 struct ata_drive_datas *drvp; 436 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 437 struct pciide_channel *cp = (struct pciide_channel*)chp; 438 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 439 int drive; 440 int channel = chp->channel; 441 442 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 443 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 444 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 445 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 446 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 447 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 448 PIIX_SIDETIM_RTC_MASK(channel)); 449 idedma_ctl = 0; 450 451 /* set up new idetim: Enable IDE registers decode */ 452 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 453 454 /* setup DMA if needed */ 455 pciide_channel_dma_setup(cp); 456 457 for (drive = 0; drive < 2; drive++) { 458 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 459 PIIX_UDMATIM_SET(0x3, channel, drive)); 460 drvp = &chp->ch_drive[drive]; 461 /* If no drive, skip */ 462 if ((drvp->drive_flags & DRIVE) == 0) 463 continue; 464 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 465 (drvp->drive_flags & DRIVE_UDMA) == 0)) 466 goto pio; 467 468 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 472 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 473 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 474 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 475 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 476 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 477 ideconf |= PIIX_CONFIG_PINGPONG; 478 } 479 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 480 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 481 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 482 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 483 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 484 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 485 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 486 /* setup Ultra/100 */ 487 if (drvp->UDMA_mode > 2 && 488 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 489 drvp->UDMA_mode = 2; 490 if (drvp->UDMA_mode > 4) { 491 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 492 } else { 493 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 494 if (drvp->UDMA_mode > 2) { 495 ideconf |= PIIX_CONFIG_UDMA66(channel, 496 drive); 497 } else { 498 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 499 drive); 500 } 501 } 502 } 503 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 504 /* setup Ultra/66 */ 505 if (drvp->UDMA_mode > 2 && 506 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 507 drvp->UDMA_mode = 2; 508 if (drvp->UDMA_mode > 2) 509 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 510 else 511 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 512 } 513 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 514 (drvp->drive_flags & DRIVE_UDMA)) { 515 /* use Ultra/DMA */ 516 drvp->drive_flags &= ~DRIVE_DMA; 517 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 518 udmareg |= PIIX_UDMATIM_SET( 519 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 520 } else { 521 /* use Multiword DMA */ 522 drvp->drive_flags &= ~DRIVE_UDMA; 523 if (drive == 0) { 524 idetim |= piix_setup_idetim_timings( 525 drvp->DMA_mode, 1, channel); 526 } else { 527 sidetim |= piix_setup_sidetim_timings( 528 drvp->DMA_mode, 1, channel); 529 idetim =PIIX_IDETIM_SET(idetim, 530 PIIX_IDETIM_SITRE, channel); 531 } 532 } 533 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 534 535 pio: /* use PIO mode */ 536 idetim |= piix_setup_idetim_drvs(drvp); 537 if (drive == 0) { 538 idetim |= piix_setup_idetim_timings( 539 drvp->PIO_mode, 0, channel); 540 } else { 541 sidetim |= piix_setup_sidetim_timings( 542 drvp->PIO_mode, 0, channel); 543 idetim =PIIX_IDETIM_SET(idetim, 544 PIIX_IDETIM_SITRE, channel); 545 } 546 } 547 if (idedma_ctl != 0) { 548 /* Add software bits in status register */ 549 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 550 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 551 idedma_ctl); 552 } 553 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 554 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 555 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 556 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 557 } 558 559 560 /* setup ISP and RTC fields, based on mode */ 561 static u_int32_t 562 piix_setup_idetim_timings(mode, dma, channel) 563 u_int8_t mode; 564 u_int8_t dma; 565 u_int8_t channel; 566 { 567 568 if (dma) 569 return PIIX_IDETIM_SET(0, 570 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 571 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 572 channel); 573 else 574 return PIIX_IDETIM_SET(0, 575 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 576 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 577 channel); 578 } 579 580 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 581 static u_int32_t 582 piix_setup_idetim_drvs(drvp) 583 struct ata_drive_datas *drvp; 584 { 585 u_int32_t ret = 0; 586 struct channel_softc *chp = drvp->chnl_softc; 587 u_int8_t channel = chp->channel; 588 u_int8_t drive = drvp->drive; 589 590 /* 591 * If drive is using UDMA, timings setups are independant 592 * So just check DMA and PIO here. 593 */ 594 if (drvp->drive_flags & DRIVE_DMA) { 595 /* if mode = DMA mode 0, use compatible timings */ 596 if ((drvp->drive_flags & DRIVE_DMA) && 597 drvp->DMA_mode == 0) { 598 drvp->PIO_mode = 0; 599 return ret; 600 } 601 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 602 /* 603 * PIO and DMA timings are the same, use fast timings for PIO 604 * too, else use compat timings. 605 */ 606 if ((piix_isp_pio[drvp->PIO_mode] != 607 piix_isp_dma[drvp->DMA_mode]) || 608 (piix_rtc_pio[drvp->PIO_mode] != 609 piix_rtc_dma[drvp->DMA_mode])) 610 drvp->PIO_mode = 0; 611 /* if PIO mode <= 2, use compat timings for PIO */ 612 if (drvp->PIO_mode <= 2) { 613 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 614 channel); 615 return ret; 616 } 617 } 618 619 /* 620 * Now setup PIO modes. If mode < 2, use compat timings. 621 * Else enable fast timings. Enable IORDY and prefetch/post 622 * if PIO mode >= 3. 623 */ 624 625 if (drvp->PIO_mode < 2) 626 return ret; 627 628 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 629 if (drvp->PIO_mode >= 3) { 630 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 631 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 632 } 633 return ret; 634 } 635 636 /* setup values in SIDETIM registers, based on mode */ 637 static u_int32_t 638 piix_setup_sidetim_timings(mode, dma, channel) 639 u_int8_t mode; 640 u_int8_t dma; 641 u_int8_t channel; 642 { 643 if (dma) 644 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 645 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 646 else 647 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 648 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 649 } 650 651 void 652 artisea_chip_map(sc, pa) 653 struct pciide_softc *sc; 654 struct pci_attach_args *pa; 655 { 656 struct pciide_channel *cp; 657 bus_size_t cmdsize, ctlsize; 658 pcireg_t interface; 659 int channel; 660 661 if (pciide_chipen(sc, pa) == 0) 662 return; 663 664 aprint_normal("%s: bus-master DMA support present", 665 sc->sc_wdcdev.sc_dev.dv_xname); 666 #ifndef PCIIDE_I31244_ENABLEDMA 667 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 668 PCI_REVISION(pa->pa_class) == 0) { 669 aprint_normal(" but disabled due to rev. 0"); 670 sc->sc_dma_ok = 0; 671 } else 672 #endif 673 pciide_mapreg_dma(sc, pa); 674 aprint_normal("\n"); 675 676 /* 677 * XXX Configure LEDs to show activity. 678 */ 679 680 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 681 WDC_CAPABILITY_MODE; 682 sc->sc_wdcdev.PIO_cap = 4; 683 if (sc->sc_dma_ok) { 684 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 685 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 686 sc->sc_wdcdev.irqack = pciide_irqack; 687 sc->sc_wdcdev.DMA_cap = 2; 688 sc->sc_wdcdev.UDMA_cap = 6; 689 } 690 sc->sc_wdcdev.set_modes = sata_setup_channel; 691 692 sc->sc_wdcdev.channels = sc->wdc_chanarray; 693 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 694 695 interface = PCI_INTERFACE(pa->pa_class); 696 697 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 698 cp = &sc->pciide_channels[channel]; 699 if (pciide_chansetup(sc, channel, interface) == 0) 700 continue; 701 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 702 pciide_pci_intr); 703 } 704 } 705
Indexes created Fri Sep 26 20:09:58 GMT 2025