piixide.c revision 1.13
1 /* $NetBSD: piixide.c,v 1.13 2004/08/19 23:25:35 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct ata_channel *); 43 static void piix3_4_setup_channel(struct ata_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static int piixide_match(struct device *, struct cfdata *, void *); 50 static void piixide_attach(struct device *, struct device *, void *); 51 52 static const struct pciide_product_desc pciide_intel_products[] = { 53 { PCI_PRODUCT_INTEL_82092AA, 54 0, 55 "Intel 82092AA IDE controller", 56 default_chip_map, 57 }, 58 { PCI_PRODUCT_INTEL_82371FB_IDE, 59 0, 60 "Intel 82371FB IDE controller (PIIX)", 61 piix_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371SB_IDE, 64 0, 65 "Intel 82371SB IDE Interface (PIIX3)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371AB_IDE, 69 0, 70 "Intel 82371AB IDE controller (PIIX4)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82440MX_IDE, 74 0, 75 "Intel 82440MX IDE controller", 76 piix_chip_map 77 }, 78 { PCI_PRODUCT_INTEL_82801AA_IDE, 79 0, 80 "Intel 82801AA IDE Controller (ICH)", 81 piix_chip_map, 82 }, 83 { PCI_PRODUCT_INTEL_82801AB_IDE, 84 0, 85 "Intel 82801AB IDE Controller (ICH0)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801BA_IDE, 89 0, 90 "Intel 82801BA IDE Controller (ICH2)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 0, 95 "Intel 82801BAM IDE Controller (ICH2-M)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 0, 100 "Intel 82801CA IDE Controller (ICH3)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801DB_IDE, 109 0, 110 "Intel 82801DB IDE Controller (ICH4)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 0, 115 "Intel 82801DBM IDE Controller (ICH4-M)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801EB_IDE, 119 0, 120 "Intel 82801EB IDE Controller (ICH5)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_SATA, 124 0, 125 "Intel 82801EB Serial ATA Controller", 126 piixsata_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801ER_SATA, 129 0, 130 "Intel 82801ER Serial ATA/Raid Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_6300ESB_IDE, 134 0, 135 "Intel 6300ESB IDE Controller (ICH5)", 136 piix_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_SATA, 139 0, 140 "Intel 6300ESB Serial ATA Controller", 141 piixsata_chip_map, 142 }, 143 { 0, 144 0, 145 NULL, 146 NULL 147 } 148 }; 149 150 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 151 piixide_match, piixide_attach, NULL, NULL); 152 153 static int 154 piixide_match(struct device *parent, struct cfdata *match, void *aux) 155 { 156 struct pci_attach_args *pa = aux; 157 158 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 159 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 160 return (2); 161 } 162 return (0); 163 } 164 165 static void 166 piixide_attach(struct device *parent, struct device *self, void *aux) 167 { 168 struct pci_attach_args *pa = aux; 169 struct pciide_softc *sc = (struct pciide_softc *)self; 170 171 pciide_common_attach(sc, pa, 172 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 173 174 } 175 176 static void 177 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 178 { 179 struct pciide_channel *cp; 180 int channel; 181 u_int32_t idetim; 182 bus_size_t cmdsize, ctlsize; 183 184 if (pciide_chipen(sc, pa) == 0) 185 return; 186 187 aprint_normal("%s: bus-master DMA support present", 188 sc->sc_wdcdev.sc_dev.dv_xname); 189 pciide_mapreg_dma(sc, pa); 190 aprint_normal("\n"); 191 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 192 if (sc->sc_dma_ok) { 193 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 194 sc->sc_wdcdev.irqack = pciide_irqack; 195 switch(sc->sc_pp->ide_product) { 196 case PCI_PRODUCT_INTEL_82371AB_IDE: 197 case PCI_PRODUCT_INTEL_82440MX_IDE: 198 case PCI_PRODUCT_INTEL_82801AA_IDE: 199 case PCI_PRODUCT_INTEL_82801AB_IDE: 200 case PCI_PRODUCT_INTEL_82801BA_IDE: 201 case PCI_PRODUCT_INTEL_82801BAM_IDE: 202 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 203 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 204 case PCI_PRODUCT_INTEL_82801DB_IDE: 205 case PCI_PRODUCT_INTEL_82801DBM_IDE: 206 case PCI_PRODUCT_INTEL_82801EB_IDE: 207 case PCI_PRODUCT_INTEL_6300ESB_IDE: 208 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 209 } 210 } 211 sc->sc_wdcdev.PIO_cap = 4; 212 sc->sc_wdcdev.DMA_cap = 2; 213 switch(sc->sc_pp->ide_product) { 214 case PCI_PRODUCT_INTEL_82801AA_IDE: 215 sc->sc_wdcdev.UDMA_cap = 4; 216 break; 217 case PCI_PRODUCT_INTEL_82801BA_IDE: 218 case PCI_PRODUCT_INTEL_82801BAM_IDE: 219 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 220 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 221 case PCI_PRODUCT_INTEL_82801DB_IDE: 222 case PCI_PRODUCT_INTEL_82801DBM_IDE: 223 case PCI_PRODUCT_INTEL_82801EB_IDE: 224 case PCI_PRODUCT_INTEL_6300ESB_IDE: 225 sc->sc_wdcdev.UDMA_cap = 5; 226 break; 227 default: 228 sc->sc_wdcdev.UDMA_cap = 2; 229 } 230 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 231 sc->sc_wdcdev.set_modes = piix_setup_channel; 232 else 233 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 234 sc->sc_wdcdev.channels = sc->wdc_chanarray; 235 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 236 237 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 238 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 239 DEBUG_PROBE); 240 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 241 ATADEBUG_PRINT((", sidetim=0x%x", 242 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 243 DEBUG_PROBE); 244 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 245 ATADEBUG_PRINT((", udamreg 0x%x", 246 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 247 DEBUG_PROBE); 248 } 249 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 250 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 251 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 252 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 253 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 254 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 255 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 256 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 257 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 258 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 259 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 260 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 261 DEBUG_PROBE); 262 } 263 264 } 265 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 266 267 wdc_allocate_regs(&sc->sc_wdcdev); 268 269 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 270 cp = &sc->pciide_channels[channel]; 271 /* PIIX is compat-only */ 272 if (pciide_chansetup(sc, channel, 0) == 0) 273 continue; 274 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 275 if ((PIIX_IDETIM_READ(idetim, channel) & 276 PIIX_IDETIM_IDE) == 0) { 277 #if 1 278 aprint_normal("%s: %s channel ignored (disabled)\n", 279 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 280 cp->ata_channel.ch_flags |= ATACH_DISABLED; 281 continue; 282 #else 283 pcireg_t interface; 284 285 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 286 channel); 287 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 288 idetim); 289 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 290 sc->sc_tag, PCI_CLASS_REG)); 291 aprint_normal("channel %d idetim=%08x interface=%02x\n", 292 channel, idetim, interface); 293 #endif 294 } 295 /* PIIX are compat-only pciide devices */ 296 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 297 } 298 299 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 300 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 301 DEBUG_PROBE); 302 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 303 ATADEBUG_PRINT((", sidetim=0x%x", 304 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 305 DEBUG_PROBE); 306 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 307 ATADEBUG_PRINT((", udamreg 0x%x", 308 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 309 DEBUG_PROBE); 310 } 311 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 312 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 313 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 314 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 315 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 316 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 317 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 318 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 319 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 320 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 321 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 322 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 323 DEBUG_PROBE); 324 } 325 } 326 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 327 } 328 329 static void 330 piix_setup_channel(struct ata_channel *chp) 331 { 332 u_int8_t mode[2], drive; 333 u_int32_t oidetim, idetim, idedma_ctl; 334 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 335 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 336 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 337 338 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 339 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 340 idedma_ctl = 0; 341 342 /* set up new idetim: Enable IDE registers decode */ 343 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 344 chp->ch_channel); 345 346 /* setup DMA */ 347 pciide_channel_dma_setup(cp); 348 349 /* 350 * Here we have to mess up with drives mode: PIIX can't have 351 * different timings for master and slave drives. 352 * We need to find the best combination. 353 */ 354 355 /* If both drives supports DMA, take the lower mode */ 356 if ((drvp[0].drive_flags & DRIVE_DMA) && 357 (drvp[1].drive_flags & DRIVE_DMA)) { 358 mode[0] = mode[1] = 359 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 360 drvp[0].DMA_mode = mode[0]; 361 drvp[1].DMA_mode = mode[1]; 362 goto ok; 363 } 364 /* 365 * If only one drive supports DMA, use its mode, and 366 * put the other one in PIO mode 0 if mode not compatible 367 */ 368 if (drvp[0].drive_flags & DRIVE_DMA) { 369 mode[0] = drvp[0].DMA_mode; 370 mode[1] = drvp[1].PIO_mode; 371 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 372 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 373 mode[1] = drvp[1].PIO_mode = 0; 374 goto ok; 375 } 376 if (drvp[1].drive_flags & DRIVE_DMA) { 377 mode[1] = drvp[1].DMA_mode; 378 mode[0] = drvp[0].PIO_mode; 379 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 380 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 381 mode[0] = drvp[0].PIO_mode = 0; 382 goto ok; 383 } 384 /* 385 * If both drives are not DMA, takes the lower mode, unless 386 * one of them is PIO mode < 2 387 */ 388 if (drvp[0].PIO_mode < 2) { 389 mode[0] = drvp[0].PIO_mode = 0; 390 mode[1] = drvp[1].PIO_mode; 391 } else if (drvp[1].PIO_mode < 2) { 392 mode[1] = drvp[1].PIO_mode = 0; 393 mode[0] = drvp[0].PIO_mode; 394 } else { 395 mode[0] = mode[1] = 396 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 397 drvp[0].PIO_mode = mode[0]; 398 drvp[1].PIO_mode = mode[1]; 399 } 400 ok: /* The modes are setup */ 401 for (drive = 0; drive < 2; drive++) { 402 if (drvp[drive].drive_flags & DRIVE_DMA) { 403 idetim |= piix_setup_idetim_timings( 404 mode[drive], 1, chp->ch_channel); 405 goto end; 406 } 407 } 408 /* If we are there, none of the drives are DMA */ 409 if (mode[0] >= 2) 410 idetim |= piix_setup_idetim_timings( 411 mode[0], 0, chp->ch_channel); 412 else 413 idetim |= piix_setup_idetim_timings( 414 mode[1], 0, chp->ch_channel); 415 end: /* 416 * timing mode is now set up in the controller. Enable 417 * it per-drive 418 */ 419 for (drive = 0; drive < 2; drive++) { 420 /* If no drive, skip */ 421 if ((drvp[drive].drive_flags & DRIVE) == 0) 422 continue; 423 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 424 if (drvp[drive].drive_flags & DRIVE_DMA) 425 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 426 } 427 if (idedma_ctl != 0) { 428 /* Add software bits in status register */ 429 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 430 idedma_ctl); 431 } 432 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 433 } 434 435 static void 436 piix3_4_setup_channel(struct ata_channel *chp) 437 { 438 struct ata_drive_datas *drvp; 439 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 440 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 441 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 442 struct wdc_softc *wdc = &sc->sc_wdcdev; 443 int drive; 444 int channel = chp->ch_channel; 445 446 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 447 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 448 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 449 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 450 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 451 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 452 PIIX_SIDETIM_RTC_MASK(channel)); 453 idedma_ctl = 0; 454 455 /* set up new idetim: Enable IDE registers decode */ 456 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 457 458 /* setup DMA if needed */ 459 pciide_channel_dma_setup(cp); 460 461 for (drive = 0; drive < 2; drive++) { 462 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 463 PIIX_UDMATIM_SET(0x3, channel, drive)); 464 drvp = &chp->ch_drive[drive]; 465 /* If no drive, skip */ 466 if ((drvp->drive_flags & DRIVE) == 0) 467 continue; 468 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 469 (drvp->drive_flags & DRIVE_UDMA) == 0)) 470 goto pio; 471 472 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 473 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 474 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 475 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 476 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 477 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 478 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 479 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 480 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 481 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 482 ideconf |= PIIX_CONFIG_PINGPONG; 483 } 484 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 485 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 486 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 487 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 488 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 489 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 490 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 491 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 492 /* setup Ultra/100 */ 493 if (drvp->UDMA_mode > 2 && 494 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 495 drvp->UDMA_mode = 2; 496 if (drvp->UDMA_mode > 4) { 497 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 498 } else { 499 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 500 if (drvp->UDMA_mode > 2) { 501 ideconf |= PIIX_CONFIG_UDMA66(channel, 502 drive); 503 } else { 504 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 505 drive); 506 } 507 } 508 } 509 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 510 /* setup Ultra/66 */ 511 if (drvp->UDMA_mode > 2 && 512 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 513 drvp->UDMA_mode = 2; 514 if (drvp->UDMA_mode > 2) 515 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 516 else 517 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 518 } 519 if ((wdc->cap & WDC_CAPABILITY_UDMA) && 520 (drvp->drive_flags & DRIVE_UDMA)) { 521 /* use Ultra/DMA */ 522 drvp->drive_flags &= ~DRIVE_DMA; 523 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 524 udmareg |= PIIX_UDMATIM_SET( 525 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 526 } else { 527 /* use Multiword DMA */ 528 drvp->drive_flags &= ~DRIVE_UDMA; 529 if (drive == 0) { 530 idetim |= piix_setup_idetim_timings( 531 drvp->DMA_mode, 1, channel); 532 } else { 533 sidetim |= piix_setup_sidetim_timings( 534 drvp->DMA_mode, 1, channel); 535 idetim =PIIX_IDETIM_SET(idetim, 536 PIIX_IDETIM_SITRE, channel); 537 } 538 } 539 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 540 541 pio: /* use PIO mode */ 542 idetim |= piix_setup_idetim_drvs(drvp); 543 if (drive == 0) { 544 idetim |= piix_setup_idetim_timings( 545 drvp->PIO_mode, 0, channel); 546 } else { 547 sidetim |= piix_setup_sidetim_timings( 548 drvp->PIO_mode, 0, channel); 549 idetim =PIIX_IDETIM_SET(idetim, 550 PIIX_IDETIM_SITRE, channel); 551 } 552 } 553 if (idedma_ctl != 0) { 554 /* Add software bits in status register */ 555 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 556 idedma_ctl); 557 } 558 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 559 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 560 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 561 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 562 } 563 564 565 /* setup ISP and RTC fields, based on mode */ 566 static u_int32_t 567 piix_setup_idetim_timings(mode, dma, channel) 568 u_int8_t mode; 569 u_int8_t dma; 570 u_int8_t channel; 571 { 572 573 if (dma) 574 return PIIX_IDETIM_SET(0, 575 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 576 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 577 channel); 578 else 579 return PIIX_IDETIM_SET(0, 580 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 581 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 582 channel); 583 } 584 585 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 586 static u_int32_t 587 piix_setup_idetim_drvs(drvp) 588 struct ata_drive_datas *drvp; 589 { 590 u_int32_t ret = 0; 591 struct ata_channel *chp = drvp->chnl_softc; 592 u_int8_t channel = chp->ch_channel; 593 u_int8_t drive = drvp->drive; 594 595 /* 596 * If drive is using UDMA, timings setups are independant 597 * So just check DMA and PIO here. 598 */ 599 if (drvp->drive_flags & DRIVE_DMA) { 600 /* if mode = DMA mode 0, use compatible timings */ 601 if ((drvp->drive_flags & DRIVE_DMA) && 602 drvp->DMA_mode == 0) { 603 drvp->PIO_mode = 0; 604 return ret; 605 } 606 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 607 /* 608 * PIO and DMA timings are the same, use fast timings for PIO 609 * too, else use compat timings. 610 */ 611 if ((piix_isp_pio[drvp->PIO_mode] != 612 piix_isp_dma[drvp->DMA_mode]) || 613 (piix_rtc_pio[drvp->PIO_mode] != 614 piix_rtc_dma[drvp->DMA_mode])) 615 drvp->PIO_mode = 0; 616 /* if PIO mode <= 2, use compat timings for PIO */ 617 if (drvp->PIO_mode <= 2) { 618 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 619 channel); 620 return ret; 621 } 622 } 623 624 /* 625 * Now setup PIO modes. If mode < 2, use compat timings. 626 * Else enable fast timings. Enable IORDY and prefetch/post 627 * if PIO mode >= 3. 628 */ 629 630 if (drvp->PIO_mode < 2) 631 return ret; 632 633 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 634 if (drvp->PIO_mode >= 3) { 635 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 636 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 637 } 638 return ret; 639 } 640 641 /* setup values in SIDETIM registers, based on mode */ 642 static u_int32_t 643 piix_setup_sidetim_timings(mode, dma, channel) 644 u_int8_t mode; 645 u_int8_t dma; 646 u_int8_t channel; 647 { 648 if (dma) 649 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 650 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 651 else 652 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 653 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 654 } 655 656 static void 657 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 658 { 659 struct pciide_channel *cp; 660 bus_size_t cmdsize, ctlsize; 661 pcireg_t interface; 662 int channel; 663 664 if (pciide_chipen(sc, pa) == 0) 665 return; 666 667 aprint_normal("%s: bus-master DMA support present", 668 sc->sc_wdcdev.sc_dev.dv_xname); 669 pciide_mapreg_dma(sc, pa); 670 aprint_normal("\n"); 671 672 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32; 673 sc->sc_wdcdev.PIO_cap = 4; 674 if (sc->sc_dma_ok) { 675 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 676 sc->sc_wdcdev.irqack = pciide_irqack; 677 sc->sc_wdcdev.DMA_cap = 2; 678 sc->sc_wdcdev.UDMA_cap = 6; 679 } 680 sc->sc_wdcdev.set_modes = sata_setup_channel; 681 682 sc->sc_wdcdev.channels = sc->wdc_chanarray; 683 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 684 685 interface = PCI_INTERFACE(pa->pa_class); 686 687 wdc_allocate_regs(&sc->sc_wdcdev); 688 689 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 690 cp = &sc->pciide_channels[channel]; 691 if (pciide_chansetup(sc, channel, interface) == 0) 692 continue; 693 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 694 pciide_pci_intr); 695 } 696 } 697
Indexes created Fri Sep 26 20:09:58 GMT 2025