piixide.c revision 1.14
1 /* $NetBSD: piixide.c,v 1.14 2004/08/20 06:39:39 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct ata_channel *); 43 static void piix3_4_setup_channel(struct ata_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static int piixide_match(struct device *, struct cfdata *, void *); 50 static void piixide_attach(struct device *, struct device *, void *); 51 52 static const struct pciide_product_desc pciide_intel_products[] = { 53 { PCI_PRODUCT_INTEL_82092AA, 54 0, 55 "Intel 82092AA IDE controller", 56 default_chip_map, 57 }, 58 { PCI_PRODUCT_INTEL_82371FB_IDE, 59 0, 60 "Intel 82371FB IDE controller (PIIX)", 61 piix_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371SB_IDE, 64 0, 65 "Intel 82371SB IDE Interface (PIIX3)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371AB_IDE, 69 0, 70 "Intel 82371AB IDE controller (PIIX4)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82440MX_IDE, 74 0, 75 "Intel 82440MX IDE controller", 76 piix_chip_map 77 }, 78 { PCI_PRODUCT_INTEL_82801AA_IDE, 79 0, 80 "Intel 82801AA IDE Controller (ICH)", 81 piix_chip_map, 82 }, 83 { PCI_PRODUCT_INTEL_82801AB_IDE, 84 0, 85 "Intel 82801AB IDE Controller (ICH0)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801BA_IDE, 89 0, 90 "Intel 82801BA IDE Controller (ICH2)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 0, 95 "Intel 82801BAM IDE Controller (ICH2-M)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 0, 100 "Intel 82801CA IDE Controller (ICH3)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801DB_IDE, 109 0, 110 "Intel 82801DB IDE Controller (ICH4)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 0, 115 "Intel 82801DBM IDE Controller (ICH4-M)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801EB_IDE, 119 0, 120 "Intel 82801EB IDE Controller (ICH5)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_SATA, 124 0, 125 "Intel 82801EB Serial ATA Controller", 126 piixsata_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801ER_SATA, 129 0, 130 "Intel 82801ER Serial ATA/Raid Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_6300ESB_IDE, 134 0, 135 "Intel 6300ESB IDE Controller (ICH5)", 136 piix_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_SATA, 139 0, 140 "Intel 6300ESB Serial ATA Controller", 141 piixsata_chip_map, 142 }, 143 { 0, 144 0, 145 NULL, 146 NULL 147 } 148 }; 149 150 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 151 piixide_match, piixide_attach, NULL, NULL); 152 153 static int 154 piixide_match(struct device *parent, struct cfdata *match, void *aux) 155 { 156 struct pci_attach_args *pa = aux; 157 158 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 159 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 160 return (2); 161 } 162 return (0); 163 } 164 165 static void 166 piixide_attach(struct device *parent, struct device *self, void *aux) 167 { 168 struct pci_attach_args *pa = aux; 169 struct pciide_softc *sc = (struct pciide_softc *)self; 170 171 pciide_common_attach(sc, pa, 172 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 173 174 } 175 176 static void 177 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 178 { 179 struct pciide_channel *cp; 180 int channel; 181 u_int32_t idetim; 182 bus_size_t cmdsize, ctlsize; 183 184 if (pciide_chipen(sc, pa) == 0) 185 return; 186 187 aprint_normal("%s: bus-master DMA support present", 188 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 189 pciide_mapreg_dma(sc, pa); 190 aprint_normal("\n"); 191 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 192 if (sc->sc_dma_ok) { 193 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 194 sc->sc_wdcdev.irqack = pciide_irqack; 195 switch(sc->sc_pp->ide_product) { 196 case PCI_PRODUCT_INTEL_82371AB_IDE: 197 case PCI_PRODUCT_INTEL_82440MX_IDE: 198 case PCI_PRODUCT_INTEL_82801AA_IDE: 199 case PCI_PRODUCT_INTEL_82801AB_IDE: 200 case PCI_PRODUCT_INTEL_82801BA_IDE: 201 case PCI_PRODUCT_INTEL_82801BAM_IDE: 202 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 203 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 204 case PCI_PRODUCT_INTEL_82801DB_IDE: 205 case PCI_PRODUCT_INTEL_82801DBM_IDE: 206 case PCI_PRODUCT_INTEL_82801EB_IDE: 207 case PCI_PRODUCT_INTEL_6300ESB_IDE: 208 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 209 } 210 } 211 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 212 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 213 switch(sc->sc_pp->ide_product) { 214 case PCI_PRODUCT_INTEL_82801AA_IDE: 215 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 216 break; 217 case PCI_PRODUCT_INTEL_82801BA_IDE: 218 case PCI_PRODUCT_INTEL_82801BAM_IDE: 219 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 220 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 221 case PCI_PRODUCT_INTEL_82801DB_IDE: 222 case PCI_PRODUCT_INTEL_82801DBM_IDE: 223 case PCI_PRODUCT_INTEL_82801EB_IDE: 224 case PCI_PRODUCT_INTEL_6300ESB_IDE: 225 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 226 break; 227 default: 228 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 229 } 230 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 231 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 232 else 233 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 234 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 235 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 236 237 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 238 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 239 DEBUG_PROBE); 240 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 241 ATADEBUG_PRINT((", sidetim=0x%x", 242 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 243 DEBUG_PROBE); 244 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 245 ATADEBUG_PRINT((", udamreg 0x%x", 246 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 247 DEBUG_PROBE); 248 } 249 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 250 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 251 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 252 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 253 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 254 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 255 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 256 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 257 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 258 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 259 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 260 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 261 DEBUG_PROBE); 262 } 263 264 } 265 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 266 267 wdc_allocate_regs(&sc->sc_wdcdev); 268 269 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 270 channel++) { 271 cp = &sc->pciide_channels[channel]; 272 /* PIIX is compat-only */ 273 if (pciide_chansetup(sc, channel, 0) == 0) 274 continue; 275 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 276 if ((PIIX_IDETIM_READ(idetim, channel) & 277 PIIX_IDETIM_IDE) == 0) { 278 #if 1 279 aprint_normal("%s: %s channel ignored (disabled)\n", 280 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 281 cp->ata_channel.ch_flags |= ATACH_DISABLED; 282 continue; 283 #else 284 pcireg_t interface; 285 286 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 287 channel); 288 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 289 idetim); 290 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 291 sc->sc_tag, PCI_CLASS_REG)); 292 aprint_normal("channel %d idetim=%08x interface=%02x\n", 293 channel, idetim, interface); 294 #endif 295 } 296 /* PIIX are compat-only pciide devices */ 297 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 298 } 299 300 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 301 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 302 DEBUG_PROBE); 303 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 304 ATADEBUG_PRINT((", sidetim=0x%x", 305 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 306 DEBUG_PROBE); 307 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 308 ATADEBUG_PRINT((", udamreg 0x%x", 309 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 310 DEBUG_PROBE); 311 } 312 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 313 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 314 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 315 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 316 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 317 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 318 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 319 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 320 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 321 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 322 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 323 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 324 DEBUG_PROBE); 325 } 326 } 327 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 328 } 329 330 static void 331 piix_setup_channel(struct ata_channel *chp) 332 { 333 u_int8_t mode[2], drive; 334 u_int32_t oidetim, idetim, idedma_ctl; 335 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 336 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 337 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 338 339 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 340 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 341 idedma_ctl = 0; 342 343 /* set up new idetim: Enable IDE registers decode */ 344 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 345 chp->ch_channel); 346 347 /* setup DMA */ 348 pciide_channel_dma_setup(cp); 349 350 /* 351 * Here we have to mess up with drives mode: PIIX can't have 352 * different timings for master and slave drives. 353 * We need to find the best combination. 354 */ 355 356 /* If both drives supports DMA, take the lower mode */ 357 if ((drvp[0].drive_flags & DRIVE_DMA) && 358 (drvp[1].drive_flags & DRIVE_DMA)) { 359 mode[0] = mode[1] = 360 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 361 drvp[0].DMA_mode = mode[0]; 362 drvp[1].DMA_mode = mode[1]; 363 goto ok; 364 } 365 /* 366 * If only one drive supports DMA, use its mode, and 367 * put the other one in PIO mode 0 if mode not compatible 368 */ 369 if (drvp[0].drive_flags & DRIVE_DMA) { 370 mode[0] = drvp[0].DMA_mode; 371 mode[1] = drvp[1].PIO_mode; 372 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 373 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 374 mode[1] = drvp[1].PIO_mode = 0; 375 goto ok; 376 } 377 if (drvp[1].drive_flags & DRIVE_DMA) { 378 mode[1] = drvp[1].DMA_mode; 379 mode[0] = drvp[0].PIO_mode; 380 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 381 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 382 mode[0] = drvp[0].PIO_mode = 0; 383 goto ok; 384 } 385 /* 386 * If both drives are not DMA, takes the lower mode, unless 387 * one of them is PIO mode < 2 388 */ 389 if (drvp[0].PIO_mode < 2) { 390 mode[0] = drvp[0].PIO_mode = 0; 391 mode[1] = drvp[1].PIO_mode; 392 } else if (drvp[1].PIO_mode < 2) { 393 mode[1] = drvp[1].PIO_mode = 0; 394 mode[0] = drvp[0].PIO_mode; 395 } else { 396 mode[0] = mode[1] = 397 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 398 drvp[0].PIO_mode = mode[0]; 399 drvp[1].PIO_mode = mode[1]; 400 } 401 ok: /* The modes are setup */ 402 for (drive = 0; drive < 2; drive++) { 403 if (drvp[drive].drive_flags & DRIVE_DMA) { 404 idetim |= piix_setup_idetim_timings( 405 mode[drive], 1, chp->ch_channel); 406 goto end; 407 } 408 } 409 /* If we are there, none of the drives are DMA */ 410 if (mode[0] >= 2) 411 idetim |= piix_setup_idetim_timings( 412 mode[0], 0, chp->ch_channel); 413 else 414 idetim |= piix_setup_idetim_timings( 415 mode[1], 0, chp->ch_channel); 416 end: /* 417 * timing mode is now set up in the controller. Enable 418 * it per-drive 419 */ 420 for (drive = 0; drive < 2; drive++) { 421 /* If no drive, skip */ 422 if ((drvp[drive].drive_flags & DRIVE) == 0) 423 continue; 424 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 425 if (drvp[drive].drive_flags & DRIVE_DMA) 426 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 427 } 428 if (idedma_ctl != 0) { 429 /* Add software bits in status register */ 430 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 431 idedma_ctl); 432 } 433 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 434 } 435 436 static void 437 piix3_4_setup_channel(struct ata_channel *chp) 438 { 439 struct ata_drive_datas *drvp; 440 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 441 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 442 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 443 struct wdc_softc *wdc = &sc->sc_wdcdev; 444 int drive; 445 int channel = chp->ch_channel; 446 447 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 448 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 449 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 450 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 451 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 452 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 453 PIIX_SIDETIM_RTC_MASK(channel)); 454 idedma_ctl = 0; 455 456 /* set up new idetim: Enable IDE registers decode */ 457 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 458 459 /* setup DMA if needed */ 460 pciide_channel_dma_setup(cp); 461 462 for (drive = 0; drive < 2; drive++) { 463 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 464 PIIX_UDMATIM_SET(0x3, channel, drive)); 465 drvp = &chp->ch_drive[drive]; 466 /* If no drive, skip */ 467 if ((drvp->drive_flags & DRIVE) == 0) 468 continue; 469 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 470 (drvp->drive_flags & DRIVE_UDMA) == 0)) 471 goto pio; 472 473 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 474 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 475 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 476 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 477 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 478 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 479 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 480 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 481 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 482 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 483 ideconf |= PIIX_CONFIG_PINGPONG; 484 } 485 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 486 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 487 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 488 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 489 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 490 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 491 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 492 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 493 /* setup Ultra/100 */ 494 if (drvp->UDMA_mode > 2 && 495 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 496 drvp->UDMA_mode = 2; 497 if (drvp->UDMA_mode > 4) { 498 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 499 } else { 500 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 501 if (drvp->UDMA_mode > 2) { 502 ideconf |= PIIX_CONFIG_UDMA66(channel, 503 drive); 504 } else { 505 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 506 drive); 507 } 508 } 509 } 510 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 511 /* setup Ultra/66 */ 512 if (drvp->UDMA_mode > 2 && 513 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 514 drvp->UDMA_mode = 2; 515 if (drvp->UDMA_mode > 2) 516 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 517 else 518 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 519 } 520 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 521 (drvp->drive_flags & DRIVE_UDMA)) { 522 /* use Ultra/DMA */ 523 drvp->drive_flags &= ~DRIVE_DMA; 524 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 525 udmareg |= PIIX_UDMATIM_SET( 526 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 527 } else { 528 /* use Multiword DMA */ 529 drvp->drive_flags &= ~DRIVE_UDMA; 530 if (drive == 0) { 531 idetim |= piix_setup_idetim_timings( 532 drvp->DMA_mode, 1, channel); 533 } else { 534 sidetim |= piix_setup_sidetim_timings( 535 drvp->DMA_mode, 1, channel); 536 idetim =PIIX_IDETIM_SET(idetim, 537 PIIX_IDETIM_SITRE, channel); 538 } 539 } 540 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 541 542 pio: /* use PIO mode */ 543 idetim |= piix_setup_idetim_drvs(drvp); 544 if (drive == 0) { 545 idetim |= piix_setup_idetim_timings( 546 drvp->PIO_mode, 0, channel); 547 } else { 548 sidetim |= piix_setup_sidetim_timings( 549 drvp->PIO_mode, 0, channel); 550 idetim =PIIX_IDETIM_SET(idetim, 551 PIIX_IDETIM_SITRE, channel); 552 } 553 } 554 if (idedma_ctl != 0) { 555 /* Add software bits in status register */ 556 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 557 idedma_ctl); 558 } 559 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 560 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 561 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 562 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 563 } 564 565 566 /* setup ISP and RTC fields, based on mode */ 567 static u_int32_t 568 piix_setup_idetim_timings(mode, dma, channel) 569 u_int8_t mode; 570 u_int8_t dma; 571 u_int8_t channel; 572 { 573 574 if (dma) 575 return PIIX_IDETIM_SET(0, 576 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 577 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 578 channel); 579 else 580 return PIIX_IDETIM_SET(0, 581 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 582 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 583 channel); 584 } 585 586 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 587 static u_int32_t 588 piix_setup_idetim_drvs(drvp) 589 struct ata_drive_datas *drvp; 590 { 591 u_int32_t ret = 0; 592 struct ata_channel *chp = drvp->chnl_softc; 593 u_int8_t channel = chp->ch_channel; 594 u_int8_t drive = drvp->drive; 595 596 /* 597 * If drive is using UDMA, timings setups are independant 598 * So just check DMA and PIO here. 599 */ 600 if (drvp->drive_flags & DRIVE_DMA) { 601 /* if mode = DMA mode 0, use compatible timings */ 602 if ((drvp->drive_flags & DRIVE_DMA) && 603 drvp->DMA_mode == 0) { 604 drvp->PIO_mode = 0; 605 return ret; 606 } 607 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 608 /* 609 * PIO and DMA timings are the same, use fast timings for PIO 610 * too, else use compat timings. 611 */ 612 if ((piix_isp_pio[drvp->PIO_mode] != 613 piix_isp_dma[drvp->DMA_mode]) || 614 (piix_rtc_pio[drvp->PIO_mode] != 615 piix_rtc_dma[drvp->DMA_mode])) 616 drvp->PIO_mode = 0; 617 /* if PIO mode <= 2, use compat timings for PIO */ 618 if (drvp->PIO_mode <= 2) { 619 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 620 channel); 621 return ret; 622 } 623 } 624 625 /* 626 * Now setup PIO modes. If mode < 2, use compat timings. 627 * Else enable fast timings. Enable IORDY and prefetch/post 628 * if PIO mode >= 3. 629 */ 630 631 if (drvp->PIO_mode < 2) 632 return ret; 633 634 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 635 if (drvp->PIO_mode >= 3) { 636 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 637 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 638 } 639 return ret; 640 } 641 642 /* setup values in SIDETIM registers, based on mode */ 643 static u_int32_t 644 piix_setup_sidetim_timings(mode, dma, channel) 645 u_int8_t mode; 646 u_int8_t dma; 647 u_int8_t channel; 648 { 649 if (dma) 650 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 651 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 652 else 653 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 654 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 655 } 656 657 static void 658 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 659 { 660 struct pciide_channel *cp; 661 bus_size_t cmdsize, ctlsize; 662 pcireg_t interface; 663 int channel; 664 665 if (pciide_chipen(sc, pa) == 0) 666 return; 667 668 aprint_normal("%s: bus-master DMA support present", 669 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 670 pciide_mapreg_dma(sc, pa); 671 aprint_normal("\n"); 672 673 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 674 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 675 if (sc->sc_dma_ok) { 676 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 677 sc->sc_wdcdev.irqack = pciide_irqack; 678 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 679 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 680 } 681 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 682 683 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 684 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 685 686 interface = PCI_INTERFACE(pa->pa_class); 687 688 wdc_allocate_regs(&sc->sc_wdcdev); 689 690 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 691 channel++) { 692 cp = &sc->pciide_channels[channel]; 693 if (pciide_chansetup(sc, channel, interface) == 0) 694 continue; 695 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 696 pciide_pci_intr); 697 } 698 } 699
Indexes created Fri Sep 26 20:09:58 GMT 2025