piixide.c revision 1.16
1 /* $NetBSD: piixide.c,v 1.16 2004/10/22 15:09:22 cube Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct ata_channel *); 43 static void piix3_4_setup_channel(struct ata_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static int piixide_match(struct device *, struct cfdata *, void *); 50 static void piixide_attach(struct device *, struct device *, void *); 51 52 static const struct pciide_product_desc pciide_intel_products[] = { 53 { PCI_PRODUCT_INTEL_82092AA, 54 0, 55 "Intel 82092AA IDE controller", 56 default_chip_map, 57 }, 58 { PCI_PRODUCT_INTEL_82371FB_IDE, 59 0, 60 "Intel 82371FB IDE controller (PIIX)", 61 piix_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371SB_IDE, 64 0, 65 "Intel 82371SB IDE Interface (PIIX3)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371AB_IDE, 69 0, 70 "Intel 82371AB IDE controller (PIIX4)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82440MX_IDE, 74 0, 75 "Intel 82440MX IDE controller", 76 piix_chip_map 77 }, 78 { PCI_PRODUCT_INTEL_82801AA_IDE, 79 0, 80 "Intel 82801AA IDE Controller (ICH)", 81 piix_chip_map, 82 }, 83 { PCI_PRODUCT_INTEL_82801AB_IDE, 84 0, 85 "Intel 82801AB IDE Controller (ICH0)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801BA_IDE, 89 0, 90 "Intel 82801BA IDE Controller (ICH2)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 0, 95 "Intel 82801BAM IDE Controller (ICH2-M)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 0, 100 "Intel 82801CA IDE Controller (ICH3)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801DB_IDE, 109 0, 110 "Intel 82801DB IDE Controller (ICH4)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 0, 115 "Intel 82801DBM IDE Controller (ICH4-M)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801EB_IDE, 119 0, 120 "Intel 82801EB IDE Controller (ICH5)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_SATA, 124 0, 125 "Intel 82801EB Serial ATA Controller", 126 piixsata_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801ER_SATA, 129 0, 130 "Intel 82801ER Serial ATA/Raid Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_6300ESB_IDE, 134 0, 135 "Intel 6300ESB IDE Controller (ICH5)", 136 piix_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_SATA, 139 0, 140 "Intel 6300ESB Serial ATA Controller", 141 piixsata_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_82801FB_SATA, 144 0, 145 "Intel 82801FB Serial ATA/Raid Controller", 146 piixsata_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_82801FR_SATA, 149 0, 150 "Intel 82801FR Serial ATA/Raid Controller", 151 piixsata_chip_map, 152 }, 153 { 0, 154 0, 155 NULL, 156 NULL 157 } 158 }; 159 160 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 161 piixide_match, piixide_attach, NULL, NULL); 162 163 static int 164 piixide_match(struct device *parent, struct cfdata *match, void *aux) 165 { 166 struct pci_attach_args *pa = aux; 167 168 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 169 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 170 return (2); 171 } 172 return (0); 173 } 174 175 static void 176 piixide_attach(struct device *parent, struct device *self, void *aux) 177 { 178 struct pci_attach_args *pa = aux; 179 struct pciide_softc *sc = (struct pciide_softc *)self; 180 181 pciide_common_attach(sc, pa, 182 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 183 184 } 185 186 static void 187 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 188 { 189 struct pciide_channel *cp; 190 int channel; 191 u_int32_t idetim; 192 bus_size_t cmdsize, ctlsize; 193 194 if (pciide_chipen(sc, pa) == 0) 195 return; 196 197 aprint_normal("%s: bus-master DMA support present", 198 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 199 pciide_mapreg_dma(sc, pa); 200 aprint_normal("\n"); 201 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 202 if (sc->sc_dma_ok) { 203 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 204 sc->sc_wdcdev.irqack = pciide_irqack; 205 switch(sc->sc_pp->ide_product) { 206 case PCI_PRODUCT_INTEL_82371AB_IDE: 207 case PCI_PRODUCT_INTEL_82440MX_IDE: 208 case PCI_PRODUCT_INTEL_82801AA_IDE: 209 case PCI_PRODUCT_INTEL_82801AB_IDE: 210 case PCI_PRODUCT_INTEL_82801BA_IDE: 211 case PCI_PRODUCT_INTEL_82801BAM_IDE: 212 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 213 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 214 case PCI_PRODUCT_INTEL_82801DB_IDE: 215 case PCI_PRODUCT_INTEL_82801DBM_IDE: 216 case PCI_PRODUCT_INTEL_82801EB_IDE: 217 case PCI_PRODUCT_INTEL_6300ESB_IDE: 218 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 219 } 220 } 221 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 222 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 223 switch(sc->sc_pp->ide_product) { 224 case PCI_PRODUCT_INTEL_82801AA_IDE: 225 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 226 break; 227 case PCI_PRODUCT_INTEL_82801BA_IDE: 228 case PCI_PRODUCT_INTEL_82801BAM_IDE: 229 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 230 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 231 case PCI_PRODUCT_INTEL_82801DB_IDE: 232 case PCI_PRODUCT_INTEL_82801DBM_IDE: 233 case PCI_PRODUCT_INTEL_82801EB_IDE: 234 case PCI_PRODUCT_INTEL_6300ESB_IDE: 235 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 236 break; 237 default: 238 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 239 } 240 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 241 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 242 else 243 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 244 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 245 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 246 247 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 248 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 249 DEBUG_PROBE); 250 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 251 ATADEBUG_PRINT((", sidetim=0x%x", 252 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 253 DEBUG_PROBE); 254 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 255 ATADEBUG_PRINT((", udamreg 0x%x", 256 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 257 DEBUG_PROBE); 258 } 259 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 260 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 261 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 262 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 263 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 264 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 265 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 266 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 267 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 268 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 269 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 270 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 271 DEBUG_PROBE); 272 } 273 274 } 275 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 276 277 wdc_allocate_regs(&sc->sc_wdcdev); 278 279 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 280 channel++) { 281 cp = &sc->pciide_channels[channel]; 282 /* PIIX is compat-only */ 283 if (pciide_chansetup(sc, channel, 0) == 0) 284 continue; 285 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 286 if ((PIIX_IDETIM_READ(idetim, channel) & 287 PIIX_IDETIM_IDE) == 0) { 288 #if 1 289 aprint_normal("%s: %s channel ignored (disabled)\n", 290 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 291 cp->ata_channel.ch_flags |= ATACH_DISABLED; 292 continue; 293 #else 294 pcireg_t interface; 295 296 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 297 channel); 298 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 299 idetim); 300 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 301 sc->sc_tag, PCI_CLASS_REG)); 302 aprint_normal("channel %d idetim=%08x interface=%02x\n", 303 channel, idetim, interface); 304 #endif 305 } 306 /* PIIX are compat-only pciide devices */ 307 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 308 } 309 310 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 311 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 312 DEBUG_PROBE); 313 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 314 ATADEBUG_PRINT((", sidetim=0x%x", 315 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 316 DEBUG_PROBE); 317 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 318 ATADEBUG_PRINT((", udamreg 0x%x", 319 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 320 DEBUG_PROBE); 321 } 322 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 323 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 324 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 325 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 326 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 327 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 328 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 329 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 330 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 331 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 332 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 333 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 334 DEBUG_PROBE); 335 } 336 } 337 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 338 } 339 340 static void 341 piix_setup_channel(struct ata_channel *chp) 342 { 343 u_int8_t mode[2], drive; 344 u_int32_t oidetim, idetim, idedma_ctl; 345 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 346 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 347 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 348 349 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 350 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 351 idedma_ctl = 0; 352 353 /* set up new idetim: Enable IDE registers decode */ 354 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 355 chp->ch_channel); 356 357 /* setup DMA */ 358 pciide_channel_dma_setup(cp); 359 360 /* 361 * Here we have to mess up with drives mode: PIIX can't have 362 * different timings for master and slave drives. 363 * We need to find the best combination. 364 */ 365 366 /* If both drives supports DMA, take the lower mode */ 367 if ((drvp[0].drive_flags & DRIVE_DMA) && 368 (drvp[1].drive_flags & DRIVE_DMA)) { 369 mode[0] = mode[1] = 370 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 371 drvp[0].DMA_mode = mode[0]; 372 drvp[1].DMA_mode = mode[1]; 373 goto ok; 374 } 375 /* 376 * If only one drive supports DMA, use its mode, and 377 * put the other one in PIO mode 0 if mode not compatible 378 */ 379 if (drvp[0].drive_flags & DRIVE_DMA) { 380 mode[0] = drvp[0].DMA_mode; 381 mode[1] = drvp[1].PIO_mode; 382 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 383 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 384 mode[1] = drvp[1].PIO_mode = 0; 385 goto ok; 386 } 387 if (drvp[1].drive_flags & DRIVE_DMA) { 388 mode[1] = drvp[1].DMA_mode; 389 mode[0] = drvp[0].PIO_mode; 390 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 391 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 392 mode[0] = drvp[0].PIO_mode = 0; 393 goto ok; 394 } 395 /* 396 * If both drives are not DMA, takes the lower mode, unless 397 * one of them is PIO mode < 2 398 */ 399 if (drvp[0].PIO_mode < 2) { 400 mode[0] = drvp[0].PIO_mode = 0; 401 mode[1] = drvp[1].PIO_mode; 402 } else if (drvp[1].PIO_mode < 2) { 403 mode[1] = drvp[1].PIO_mode = 0; 404 mode[0] = drvp[0].PIO_mode; 405 } else { 406 mode[0] = mode[1] = 407 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 408 drvp[0].PIO_mode = mode[0]; 409 drvp[1].PIO_mode = mode[1]; 410 } 411 ok: /* The modes are setup */ 412 for (drive = 0; drive < 2; drive++) { 413 if (drvp[drive].drive_flags & DRIVE_DMA) { 414 idetim |= piix_setup_idetim_timings( 415 mode[drive], 1, chp->ch_channel); 416 goto end; 417 } 418 } 419 /* If we are there, none of the drives are DMA */ 420 if (mode[0] >= 2) 421 idetim |= piix_setup_idetim_timings( 422 mode[0], 0, chp->ch_channel); 423 else 424 idetim |= piix_setup_idetim_timings( 425 mode[1], 0, chp->ch_channel); 426 end: /* 427 * timing mode is now set up in the controller. Enable 428 * it per-drive 429 */ 430 for (drive = 0; drive < 2; drive++) { 431 /* If no drive, skip */ 432 if ((drvp[drive].drive_flags & DRIVE) == 0) 433 continue; 434 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 435 if (drvp[drive].drive_flags & DRIVE_DMA) 436 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 437 } 438 if (idedma_ctl != 0) { 439 /* Add software bits in status register */ 440 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 441 idedma_ctl); 442 } 443 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 444 } 445 446 static void 447 piix3_4_setup_channel(struct ata_channel *chp) 448 { 449 struct ata_drive_datas *drvp; 450 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 451 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 452 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 453 struct wdc_softc *wdc = &sc->sc_wdcdev; 454 int drive, s; 455 int channel = chp->ch_channel; 456 457 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 458 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 459 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 460 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 461 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 462 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 463 PIIX_SIDETIM_RTC_MASK(channel)); 464 idedma_ctl = 0; 465 466 /* set up new idetim: Enable IDE registers decode */ 467 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 468 469 /* setup DMA if needed */ 470 pciide_channel_dma_setup(cp); 471 472 for (drive = 0; drive < 2; drive++) { 473 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 474 PIIX_UDMATIM_SET(0x3, channel, drive)); 475 drvp = &chp->ch_drive[drive]; 476 /* If no drive, skip */ 477 if ((drvp->drive_flags & DRIVE) == 0) 478 continue; 479 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 480 (drvp->drive_flags & DRIVE_UDMA) == 0)) 481 goto pio; 482 483 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 484 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 485 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 486 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 487 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 488 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 489 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 490 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 491 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 492 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 493 ideconf |= PIIX_CONFIG_PINGPONG; 494 } 495 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 496 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 497 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 498 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 499 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 500 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 501 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 502 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 503 /* setup Ultra/100 */ 504 if (drvp->UDMA_mode > 2 && 505 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 506 drvp->UDMA_mode = 2; 507 if (drvp->UDMA_mode > 4) { 508 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 509 } else { 510 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 511 if (drvp->UDMA_mode > 2) { 512 ideconf |= PIIX_CONFIG_UDMA66(channel, 513 drive); 514 } else { 515 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 516 drive); 517 } 518 } 519 } 520 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 521 /* setup Ultra/66 */ 522 if (drvp->UDMA_mode > 2 && 523 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 524 drvp->UDMA_mode = 2; 525 if (drvp->UDMA_mode > 2) 526 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 527 else 528 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 529 } 530 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 531 (drvp->drive_flags & DRIVE_UDMA)) { 532 /* use Ultra/DMA */ 533 s = splbio(); 534 drvp->drive_flags &= ~DRIVE_DMA; 535 splx(s); 536 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 537 udmareg |= PIIX_UDMATIM_SET( 538 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 539 } else { 540 /* use Multiword DMA */ 541 s = splbio(); 542 drvp->drive_flags &= ~DRIVE_UDMA; 543 splx(s); 544 if (drive == 0) { 545 idetim |= piix_setup_idetim_timings( 546 drvp->DMA_mode, 1, channel); 547 } else { 548 sidetim |= piix_setup_sidetim_timings( 549 drvp->DMA_mode, 1, channel); 550 idetim =PIIX_IDETIM_SET(idetim, 551 PIIX_IDETIM_SITRE, channel); 552 } 553 } 554 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 555 556 pio: /* use PIO mode */ 557 idetim |= piix_setup_idetim_drvs(drvp); 558 if (drive == 0) { 559 idetim |= piix_setup_idetim_timings( 560 drvp->PIO_mode, 0, channel); 561 } else { 562 sidetim |= piix_setup_sidetim_timings( 563 drvp->PIO_mode, 0, channel); 564 idetim =PIIX_IDETIM_SET(idetim, 565 PIIX_IDETIM_SITRE, channel); 566 } 567 } 568 if (idedma_ctl != 0) { 569 /* Add software bits in status register */ 570 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 571 idedma_ctl); 572 } 573 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 574 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 575 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 576 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 577 } 578 579 580 /* setup ISP and RTC fields, based on mode */ 581 static u_int32_t 582 piix_setup_idetim_timings(mode, dma, channel) 583 u_int8_t mode; 584 u_int8_t dma; 585 u_int8_t channel; 586 { 587 588 if (dma) 589 return PIIX_IDETIM_SET(0, 590 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 591 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 592 channel); 593 else 594 return PIIX_IDETIM_SET(0, 595 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 596 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 597 channel); 598 } 599 600 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 601 static u_int32_t 602 piix_setup_idetim_drvs(drvp) 603 struct ata_drive_datas *drvp; 604 { 605 u_int32_t ret = 0; 606 struct ata_channel *chp = drvp->chnl_softc; 607 u_int8_t channel = chp->ch_channel; 608 u_int8_t drive = drvp->drive; 609 610 /* 611 * If drive is using UDMA, timings setups are independant 612 * So just check DMA and PIO here. 613 */ 614 if (drvp->drive_flags & DRIVE_DMA) { 615 /* if mode = DMA mode 0, use compatible timings */ 616 if ((drvp->drive_flags & DRIVE_DMA) && 617 drvp->DMA_mode == 0) { 618 drvp->PIO_mode = 0; 619 return ret; 620 } 621 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 622 /* 623 * PIO and DMA timings are the same, use fast timings for PIO 624 * too, else use compat timings. 625 */ 626 if ((piix_isp_pio[drvp->PIO_mode] != 627 piix_isp_dma[drvp->DMA_mode]) || 628 (piix_rtc_pio[drvp->PIO_mode] != 629 piix_rtc_dma[drvp->DMA_mode])) 630 drvp->PIO_mode = 0; 631 /* if PIO mode <= 2, use compat timings for PIO */ 632 if (drvp->PIO_mode <= 2) { 633 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 634 channel); 635 return ret; 636 } 637 } 638 639 /* 640 * Now setup PIO modes. If mode < 2, use compat timings. 641 * Else enable fast timings. Enable IORDY and prefetch/post 642 * if PIO mode >= 3. 643 */ 644 645 if (drvp->PIO_mode < 2) 646 return ret; 647 648 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 649 if (drvp->PIO_mode >= 3) { 650 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 651 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 652 } 653 return ret; 654 } 655 656 /* setup values in SIDETIM registers, based on mode */ 657 static u_int32_t 658 piix_setup_sidetim_timings(mode, dma, channel) 659 u_int8_t mode; 660 u_int8_t dma; 661 u_int8_t channel; 662 { 663 if (dma) 664 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 665 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 666 else 667 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 668 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 669 } 670 671 static void 672 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 673 { 674 struct pciide_channel *cp; 675 bus_size_t cmdsize, ctlsize; 676 pcireg_t interface; 677 int channel; 678 679 if (pciide_chipen(sc, pa) == 0) 680 return; 681 682 aprint_normal("%s: bus-master DMA support present", 683 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 684 pciide_mapreg_dma(sc, pa); 685 aprint_normal("\n"); 686 687 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 688 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 689 if (sc->sc_dma_ok) { 690 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 691 sc->sc_wdcdev.irqack = pciide_irqack; 692 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 693 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 694 } 695 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 696 697 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 698 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 699 700 interface = PCI_INTERFACE(pa->pa_class); 701 702 wdc_allocate_regs(&sc->sc_wdcdev); 703 704 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 705 channel++) { 706 cp = &sc->pciide_channels[channel]; 707 if (pciide_chansetup(sc, channel, interface) == 0) 708 continue; 709 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 710 pciide_pci_intr); 711 } 712 } 713
Indexes created Fri Sep 26 20:09:58 GMT 2025