piixide.c revision 1.17
1 /* $NetBSD: piixide.c,v 1.17 2004/11/10 17:19:05 cube Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct ata_channel *); 43 static void piix3_4_setup_channel(struct ata_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static int piixide_match(struct device *, struct cfdata *, void *); 50 static void piixide_attach(struct device *, struct device *, void *); 51 52 static const struct pciide_product_desc pciide_intel_products[] = { 53 { PCI_PRODUCT_INTEL_82092AA, 54 0, 55 "Intel 82092AA IDE controller", 56 default_chip_map, 57 }, 58 { PCI_PRODUCT_INTEL_82371FB_IDE, 59 0, 60 "Intel 82371FB IDE controller (PIIX)", 61 piix_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371SB_IDE, 64 0, 65 "Intel 82371SB IDE Interface (PIIX3)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371AB_IDE, 69 0, 70 "Intel 82371AB IDE controller (PIIX4)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82440MX_IDE, 74 0, 75 "Intel 82440MX IDE controller", 76 piix_chip_map 77 }, 78 { PCI_PRODUCT_INTEL_82801AA_IDE, 79 0, 80 "Intel 82801AA IDE Controller (ICH)", 81 piix_chip_map, 82 }, 83 { PCI_PRODUCT_INTEL_82801AB_IDE, 84 0, 85 "Intel 82801AB IDE Controller (ICH0)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801BA_IDE, 89 0, 90 "Intel 82801BA IDE Controller (ICH2)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 0, 95 "Intel 82801BAM IDE Controller (ICH2-M)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 0, 100 "Intel 82801CA IDE Controller (ICH3)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801DB_IDE, 109 0, 110 "Intel 82801DB IDE Controller (ICH4)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 0, 115 "Intel 82801DBM IDE Controller (ICH4-M)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801EB_IDE, 119 0, 120 "Intel 82801EB IDE Controller (ICH5)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_SATA, 124 0, 125 "Intel 82801EB Serial ATA Controller", 126 piixsata_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801ER_SATA, 129 0, 130 "Intel 82801ER Serial ATA/Raid Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_6300ESB_IDE, 134 0, 135 "Intel 6300ESB IDE Controller (ICH5)", 136 piix_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_SATA, 139 0, 140 "Intel 6300ESB Serial ATA Controller", 141 piixsata_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_82801FB_IDE, 144 0, 145 "Intel 82801FB IDE Controller (ICH6)", 146 piix_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_82801FB_SATA, 149 0, 150 "Intel 82801FB Serial ATA/Raid Controller", 151 piixsata_chip_map, 152 }, 153 { PCI_PRODUCT_INTEL_82801FR_SATA, 154 0, 155 "Intel 82801FR Serial ATA/Raid Controller", 156 piixsata_chip_map, 157 }, 158 { 0, 159 0, 160 NULL, 161 NULL 162 } 163 }; 164 165 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 166 piixide_match, piixide_attach, NULL, NULL); 167 168 static int 169 piixide_match(struct device *parent, struct cfdata *match, void *aux) 170 { 171 struct pci_attach_args *pa = aux; 172 173 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 174 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 175 return (2); 176 } 177 return (0); 178 } 179 180 static void 181 piixide_attach(struct device *parent, struct device *self, void *aux) 182 { 183 struct pci_attach_args *pa = aux; 184 struct pciide_softc *sc = (struct pciide_softc *)self; 185 186 pciide_common_attach(sc, pa, 187 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 188 189 } 190 191 static void 192 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 193 { 194 struct pciide_channel *cp; 195 int channel; 196 u_int32_t idetim; 197 bus_size_t cmdsize, ctlsize; 198 199 if (pciide_chipen(sc, pa) == 0) 200 return; 201 202 aprint_normal("%s: bus-master DMA support present", 203 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 204 pciide_mapreg_dma(sc, pa); 205 aprint_normal("\n"); 206 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 207 if (sc->sc_dma_ok) { 208 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 209 sc->sc_wdcdev.irqack = pciide_irqack; 210 switch(sc->sc_pp->ide_product) { 211 case PCI_PRODUCT_INTEL_82371AB_IDE: 212 case PCI_PRODUCT_INTEL_82440MX_IDE: 213 case PCI_PRODUCT_INTEL_82801AA_IDE: 214 case PCI_PRODUCT_INTEL_82801AB_IDE: 215 case PCI_PRODUCT_INTEL_82801BA_IDE: 216 case PCI_PRODUCT_INTEL_82801BAM_IDE: 217 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 218 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 219 case PCI_PRODUCT_INTEL_82801DB_IDE: 220 case PCI_PRODUCT_INTEL_82801DBM_IDE: 221 case PCI_PRODUCT_INTEL_82801EB_IDE: 222 case PCI_PRODUCT_INTEL_6300ESB_IDE: 223 case PCI_PRODUCT_INTEL_82801FB_IDE: 224 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 225 } 226 } 227 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 228 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 229 switch(sc->sc_pp->ide_product) { 230 case PCI_PRODUCT_INTEL_82801AA_IDE: 231 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 232 break; 233 case PCI_PRODUCT_INTEL_82801BA_IDE: 234 case PCI_PRODUCT_INTEL_82801BAM_IDE: 235 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 236 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 237 case PCI_PRODUCT_INTEL_82801DB_IDE: 238 case PCI_PRODUCT_INTEL_82801DBM_IDE: 239 case PCI_PRODUCT_INTEL_82801EB_IDE: 240 case PCI_PRODUCT_INTEL_6300ESB_IDE: 241 case PCI_PRODUCT_INTEL_82801FB_IDE: 242 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 243 break; 244 default: 245 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 246 } 247 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 248 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 249 else 250 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 251 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 252 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 253 254 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 255 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 256 DEBUG_PROBE); 257 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 258 ATADEBUG_PRINT((", sidetim=0x%x", 259 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 260 DEBUG_PROBE); 261 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 262 ATADEBUG_PRINT((", udamreg 0x%x", 263 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 264 DEBUG_PROBE); 265 } 266 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 267 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 268 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 269 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 270 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 271 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 272 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 273 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 274 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 275 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 276 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 277 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 278 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 279 DEBUG_PROBE); 280 } 281 282 } 283 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 284 285 wdc_allocate_regs(&sc->sc_wdcdev); 286 287 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 288 channel++) { 289 cp = &sc->pciide_channels[channel]; 290 /* PIIX is compat-only */ 291 if (pciide_chansetup(sc, channel, 0) == 0) 292 continue; 293 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 294 if ((PIIX_IDETIM_READ(idetim, channel) & 295 PIIX_IDETIM_IDE) == 0) { 296 #if 1 297 aprint_normal("%s: %s channel ignored (disabled)\n", 298 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 299 cp->ata_channel.ch_flags |= ATACH_DISABLED; 300 continue; 301 #else 302 pcireg_t interface; 303 304 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 305 channel); 306 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 307 idetim); 308 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 309 sc->sc_tag, PCI_CLASS_REG)); 310 aprint_normal("channel %d idetim=%08x interface=%02x\n", 311 channel, idetim, interface); 312 #endif 313 } 314 /* PIIX are compat-only pciide devices */ 315 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 316 } 317 318 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 319 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 320 DEBUG_PROBE); 321 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 322 ATADEBUG_PRINT((", sidetim=0x%x", 323 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 324 DEBUG_PROBE); 325 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 326 ATADEBUG_PRINT((", udamreg 0x%x", 327 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 328 DEBUG_PROBE); 329 } 330 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 331 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 332 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 333 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 334 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 335 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 336 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 337 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 338 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 339 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 340 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 341 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 342 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 343 DEBUG_PROBE); 344 } 345 } 346 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 347 } 348 349 static void 350 piix_setup_channel(struct ata_channel *chp) 351 { 352 u_int8_t mode[2], drive; 353 u_int32_t oidetim, idetim, idedma_ctl; 354 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 355 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 356 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 357 358 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 359 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 360 idedma_ctl = 0; 361 362 /* set up new idetim: Enable IDE registers decode */ 363 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 364 chp->ch_channel); 365 366 /* setup DMA */ 367 pciide_channel_dma_setup(cp); 368 369 /* 370 * Here we have to mess up with drives mode: PIIX can't have 371 * different timings for master and slave drives. 372 * We need to find the best combination. 373 */ 374 375 /* If both drives supports DMA, take the lower mode */ 376 if ((drvp[0].drive_flags & DRIVE_DMA) && 377 (drvp[1].drive_flags & DRIVE_DMA)) { 378 mode[0] = mode[1] = 379 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 380 drvp[0].DMA_mode = mode[0]; 381 drvp[1].DMA_mode = mode[1]; 382 goto ok; 383 } 384 /* 385 * If only one drive supports DMA, use its mode, and 386 * put the other one in PIO mode 0 if mode not compatible 387 */ 388 if (drvp[0].drive_flags & DRIVE_DMA) { 389 mode[0] = drvp[0].DMA_mode; 390 mode[1] = drvp[1].PIO_mode; 391 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 392 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 393 mode[1] = drvp[1].PIO_mode = 0; 394 goto ok; 395 } 396 if (drvp[1].drive_flags & DRIVE_DMA) { 397 mode[1] = drvp[1].DMA_mode; 398 mode[0] = drvp[0].PIO_mode; 399 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 400 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 401 mode[0] = drvp[0].PIO_mode = 0; 402 goto ok; 403 } 404 /* 405 * If both drives are not DMA, takes the lower mode, unless 406 * one of them is PIO mode < 2 407 */ 408 if (drvp[0].PIO_mode < 2) { 409 mode[0] = drvp[0].PIO_mode = 0; 410 mode[1] = drvp[1].PIO_mode; 411 } else if (drvp[1].PIO_mode < 2) { 412 mode[1] = drvp[1].PIO_mode = 0; 413 mode[0] = drvp[0].PIO_mode; 414 } else { 415 mode[0] = mode[1] = 416 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 417 drvp[0].PIO_mode = mode[0]; 418 drvp[1].PIO_mode = mode[1]; 419 } 420 ok: /* The modes are setup */ 421 for (drive = 0; drive < 2; drive++) { 422 if (drvp[drive].drive_flags & DRIVE_DMA) { 423 idetim |= piix_setup_idetim_timings( 424 mode[drive], 1, chp->ch_channel); 425 goto end; 426 } 427 } 428 /* If we are there, none of the drives are DMA */ 429 if (mode[0] >= 2) 430 idetim |= piix_setup_idetim_timings( 431 mode[0], 0, chp->ch_channel); 432 else 433 idetim |= piix_setup_idetim_timings( 434 mode[1], 0, chp->ch_channel); 435 end: /* 436 * timing mode is now set up in the controller. Enable 437 * it per-drive 438 */ 439 for (drive = 0; drive < 2; drive++) { 440 /* If no drive, skip */ 441 if ((drvp[drive].drive_flags & DRIVE) == 0) 442 continue; 443 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 444 if (drvp[drive].drive_flags & DRIVE_DMA) 445 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 446 } 447 if (idedma_ctl != 0) { 448 /* Add software bits in status register */ 449 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 450 idedma_ctl); 451 } 452 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 453 } 454 455 static void 456 piix3_4_setup_channel(struct ata_channel *chp) 457 { 458 struct ata_drive_datas *drvp; 459 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 460 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 461 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 462 struct wdc_softc *wdc = &sc->sc_wdcdev; 463 int drive, s; 464 int channel = chp->ch_channel; 465 466 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 467 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 468 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 469 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 470 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 471 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 472 PIIX_SIDETIM_RTC_MASK(channel)); 473 idedma_ctl = 0; 474 475 /* set up new idetim: Enable IDE registers decode */ 476 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 477 478 /* setup DMA if needed */ 479 pciide_channel_dma_setup(cp); 480 481 for (drive = 0; drive < 2; drive++) { 482 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 483 PIIX_UDMATIM_SET(0x3, channel, drive)); 484 drvp = &chp->ch_drive[drive]; 485 /* If no drive, skip */ 486 if ((drvp->drive_flags & DRIVE) == 0) 487 continue; 488 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 489 (drvp->drive_flags & DRIVE_UDMA) == 0)) 490 goto pio; 491 492 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 493 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 494 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 495 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 496 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 497 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 498 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 499 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 500 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 501 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 502 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 503 ideconf |= PIIX_CONFIG_PINGPONG; 504 } 505 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 506 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 507 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 508 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 509 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 510 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 511 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 512 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 513 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 514 /* setup Ultra/100 */ 515 if (drvp->UDMA_mode > 2 && 516 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 517 drvp->UDMA_mode = 2; 518 if (drvp->UDMA_mode > 4) { 519 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 520 } else { 521 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 522 if (drvp->UDMA_mode > 2) { 523 ideconf |= PIIX_CONFIG_UDMA66(channel, 524 drive); 525 } else { 526 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 527 drive); 528 } 529 } 530 } 531 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 532 /* setup Ultra/66 */ 533 if (drvp->UDMA_mode > 2 && 534 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 535 drvp->UDMA_mode = 2; 536 if (drvp->UDMA_mode > 2) 537 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 538 else 539 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 540 } 541 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 542 (drvp->drive_flags & DRIVE_UDMA)) { 543 /* use Ultra/DMA */ 544 s = splbio(); 545 drvp->drive_flags &= ~DRIVE_DMA; 546 splx(s); 547 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 548 udmareg |= PIIX_UDMATIM_SET( 549 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 550 } else { 551 /* use Multiword DMA */ 552 s = splbio(); 553 drvp->drive_flags &= ~DRIVE_UDMA; 554 splx(s); 555 if (drive == 0) { 556 idetim |= piix_setup_idetim_timings( 557 drvp->DMA_mode, 1, channel); 558 } else { 559 sidetim |= piix_setup_sidetim_timings( 560 drvp->DMA_mode, 1, channel); 561 idetim =PIIX_IDETIM_SET(idetim, 562 PIIX_IDETIM_SITRE, channel); 563 } 564 } 565 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 566 567 pio: /* use PIO mode */ 568 idetim |= piix_setup_idetim_drvs(drvp); 569 if (drive == 0) { 570 idetim |= piix_setup_idetim_timings( 571 drvp->PIO_mode, 0, channel); 572 } else { 573 sidetim |= piix_setup_sidetim_timings( 574 drvp->PIO_mode, 0, channel); 575 idetim =PIIX_IDETIM_SET(idetim, 576 PIIX_IDETIM_SITRE, channel); 577 } 578 } 579 if (idedma_ctl != 0) { 580 /* Add software bits in status register */ 581 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 582 idedma_ctl); 583 } 584 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 585 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 586 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 587 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 588 } 589 590 591 /* setup ISP and RTC fields, based on mode */ 592 static u_int32_t 593 piix_setup_idetim_timings(mode, dma, channel) 594 u_int8_t mode; 595 u_int8_t dma; 596 u_int8_t channel; 597 { 598 599 if (dma) 600 return PIIX_IDETIM_SET(0, 601 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 602 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 603 channel); 604 else 605 return PIIX_IDETIM_SET(0, 606 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 607 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 608 channel); 609 } 610 611 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 612 static u_int32_t 613 piix_setup_idetim_drvs(drvp) 614 struct ata_drive_datas *drvp; 615 { 616 u_int32_t ret = 0; 617 struct ata_channel *chp = drvp->chnl_softc; 618 u_int8_t channel = chp->ch_channel; 619 u_int8_t drive = drvp->drive; 620 621 /* 622 * If drive is using UDMA, timings setups are independant 623 * So just check DMA and PIO here. 624 */ 625 if (drvp->drive_flags & DRIVE_DMA) { 626 /* if mode = DMA mode 0, use compatible timings */ 627 if ((drvp->drive_flags & DRIVE_DMA) && 628 drvp->DMA_mode == 0) { 629 drvp->PIO_mode = 0; 630 return ret; 631 } 632 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 633 /* 634 * PIO and DMA timings are the same, use fast timings for PIO 635 * too, else use compat timings. 636 */ 637 if ((piix_isp_pio[drvp->PIO_mode] != 638 piix_isp_dma[drvp->DMA_mode]) || 639 (piix_rtc_pio[drvp->PIO_mode] != 640 piix_rtc_dma[drvp->DMA_mode])) 641 drvp->PIO_mode = 0; 642 /* if PIO mode <= 2, use compat timings for PIO */ 643 if (drvp->PIO_mode <= 2) { 644 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 645 channel); 646 return ret; 647 } 648 } 649 650 /* 651 * Now setup PIO modes. If mode < 2, use compat timings. 652 * Else enable fast timings. Enable IORDY and prefetch/post 653 * if PIO mode >= 3. 654 */ 655 656 if (drvp->PIO_mode < 2) 657 return ret; 658 659 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 660 if (drvp->PIO_mode >= 3) { 661 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 662 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 663 } 664 return ret; 665 } 666 667 /* setup values in SIDETIM registers, based on mode */ 668 static u_int32_t 669 piix_setup_sidetim_timings(mode, dma, channel) 670 u_int8_t mode; 671 u_int8_t dma; 672 u_int8_t channel; 673 { 674 if (dma) 675 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 676 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 677 else 678 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 679 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 680 } 681 682 static void 683 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 684 { 685 struct pciide_channel *cp; 686 bus_size_t cmdsize, ctlsize; 687 pcireg_t interface; 688 int channel; 689 690 if (pciide_chipen(sc, pa) == 0) 691 return; 692 693 aprint_normal("%s: bus-master DMA support present", 694 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 695 pciide_mapreg_dma(sc, pa); 696 aprint_normal("\n"); 697 698 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 699 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 700 if (sc->sc_dma_ok) { 701 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 702 sc->sc_wdcdev.irqack = pciide_irqack; 703 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 704 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 705 } 706 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 707 708 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 709 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 710 711 interface = PCI_INTERFACE(pa->pa_class); 712 713 wdc_allocate_regs(&sc->sc_wdcdev); 714 715 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 716 channel++) { 717 cp = &sc->pciide_channels[channel]; 718 if (pciide_chansetup(sc, channel, interface) == 0) 719 continue; 720 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 721 pciide_pci_intr); 722 } 723 } 724
Indexes created Fri Sep 26 20:09:58 GMT 2025