piixide.c revision 1.19.2.1
1 /* $NetBSD: piixide.c,v 1.19.2.1 2005/06/21 21:23:50 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct ata_channel *); 43 static void piix3_4_setup_channel(struct ata_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static void piixide_powerhook(int, void *); 50 static int piixide_match(struct device *, struct cfdata *, void *); 51 static void piixide_attach(struct device *, struct device *, void *); 52 53 static const struct pciide_product_desc pciide_intel_products[] = { 54 { PCI_PRODUCT_INTEL_82092AA, 55 0, 56 "Intel 82092AA IDE controller", 57 default_chip_map, 58 }, 59 { PCI_PRODUCT_INTEL_82371FB_IDE, 60 0, 61 "Intel 82371FB IDE controller (PIIX)", 62 piix_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371SB_IDE, 65 0, 66 "Intel 82371SB IDE Interface (PIIX3)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371AB_IDE, 70 0, 71 "Intel 82371AB IDE controller (PIIX4)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82440MX_IDE, 75 0, 76 "Intel 82440MX IDE controller", 77 piix_chip_map 78 }, 79 { PCI_PRODUCT_INTEL_82801AA_IDE, 80 0, 81 "Intel 82801AA IDE Controller (ICH)", 82 piix_chip_map, 83 }, 84 { PCI_PRODUCT_INTEL_82801AB_IDE, 85 0, 86 "Intel 82801AB IDE Controller (ICH0)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801BA_IDE, 90 0, 91 "Intel 82801BA IDE Controller (ICH2)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BAM_IDE, 95 0, 96 "Intel 82801BAM IDE Controller (ICH2-M)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 100 0, 101 "Intel 82801CA IDE Controller (ICH3)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801DB_IDE, 110 0, 111 "Intel 82801DB IDE Controller (ICH4)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DBM_IDE, 115 0, 116 "Intel 82801DBM IDE Controller (ICH4-M)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801EB_IDE, 120 0, 121 "Intel 82801EB IDE Controller (ICH5)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_SATA, 125 0, 126 "Intel 82801EB Serial ATA Controller", 127 piixsata_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801ER_SATA, 130 0, 131 "Intel 82801ER Serial ATA/Raid Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_6300ESB_IDE, 135 0, 136 "Intel 6300ESB IDE Controller (ICH5)", 137 piix_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_SATA, 140 0, 141 "Intel 6300ESB Serial ATA Controller", 142 piixsata_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_82801FB_IDE, 145 0, 146 "Intel 82801FB IDE Controller (ICH6)", 147 piix_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_82801FB_SATA, 150 0, 151 "Intel 82801FB Serial ATA/Raid Controller", 152 piixsata_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FR_SATA, 155 0, 156 "Intel 82801FR Serial ATA/Raid Controller", 157 piixsata_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FBM_SATA, 160 0, 161 "Intel 82801FBM Serial ATA Controller (ICH6)", 162 piixsata_chip_map, 163 }, 164 { 0, 165 0, 166 NULL, 167 NULL 168 } 169 }; 170 171 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 172 piixide_match, piixide_attach, NULL, NULL); 173 174 static int 175 piixide_match(struct device *parent, struct cfdata *match, void *aux) 176 { 177 struct pci_attach_args *pa = aux; 178 179 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 180 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 181 return (2); 182 } 183 return (0); 184 } 185 186 static void 187 piixide_attach(struct device *parent, struct device *self, void *aux) 188 { 189 struct pci_attach_args *pa = aux; 190 struct pciide_softc *sc = (struct pciide_softc *)self; 191 192 pciide_common_attach(sc, pa, 193 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 194 195 /* Setup our powerhook */ 196 sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc); 197 if (sc->sc_powerhook == NULL) 198 printf("%s: WARNING: unable to establish PCI power hook\n", 199 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 200 } 201 202 static void 203 piixide_powerhook(int why, void *hdl) 204 { 205 struct pciide_softc *sc = (struct pciide_softc *)hdl; 206 207 switch (why) { 208 case PWR_SUSPEND: 209 case PWR_STANDBY: 210 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 211 break; 212 case PWR_RESUME: 213 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 214 break; 215 case PWR_SOFTSUSPEND: 216 case PWR_SOFTSTANDBY: 217 case PWR_SOFTRESUME: 218 break; 219 } 220 221 return; 222 } 223 224 static void 225 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 226 { 227 struct pciide_channel *cp; 228 int channel; 229 u_int32_t idetim; 230 bus_size_t cmdsize, ctlsize; 231 232 if (pciide_chipen(sc, pa) == 0) 233 return; 234 235 aprint_normal("%s: bus-master DMA support present", 236 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 237 pciide_mapreg_dma(sc, pa); 238 aprint_normal("\n"); 239 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 240 if (sc->sc_dma_ok) { 241 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 242 sc->sc_wdcdev.irqack = pciide_irqack; 243 switch(sc->sc_pp->ide_product) { 244 case PCI_PRODUCT_INTEL_82371AB_IDE: 245 case PCI_PRODUCT_INTEL_82440MX_IDE: 246 case PCI_PRODUCT_INTEL_82801AA_IDE: 247 case PCI_PRODUCT_INTEL_82801AB_IDE: 248 case PCI_PRODUCT_INTEL_82801BA_IDE: 249 case PCI_PRODUCT_INTEL_82801BAM_IDE: 250 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 251 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 252 case PCI_PRODUCT_INTEL_82801DB_IDE: 253 case PCI_PRODUCT_INTEL_82801DBM_IDE: 254 case PCI_PRODUCT_INTEL_82801EB_IDE: 255 case PCI_PRODUCT_INTEL_6300ESB_IDE: 256 case PCI_PRODUCT_INTEL_82801FB_IDE: 257 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 258 } 259 } 260 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 261 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 262 switch(sc->sc_pp->ide_product) { 263 case PCI_PRODUCT_INTEL_82801AA_IDE: 264 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 265 break; 266 case PCI_PRODUCT_INTEL_82801BA_IDE: 267 case PCI_PRODUCT_INTEL_82801BAM_IDE: 268 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 269 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 270 case PCI_PRODUCT_INTEL_82801DB_IDE: 271 case PCI_PRODUCT_INTEL_82801DBM_IDE: 272 case PCI_PRODUCT_INTEL_82801EB_IDE: 273 case PCI_PRODUCT_INTEL_6300ESB_IDE: 274 case PCI_PRODUCT_INTEL_82801FB_IDE: 275 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 276 break; 277 default: 278 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 279 } 280 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 281 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 282 else 283 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 284 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 285 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 286 287 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 288 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 289 DEBUG_PROBE); 290 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 291 ATADEBUG_PRINT((", sidetim=0x%x", 292 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 293 DEBUG_PROBE); 294 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 295 ATADEBUG_PRINT((", udamreg 0x%x", 296 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 297 DEBUG_PROBE); 298 } 299 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 300 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 301 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 302 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 303 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 304 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 305 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 306 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 307 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 308 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 309 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 310 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 311 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 312 DEBUG_PROBE); 313 } 314 315 } 316 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 317 318 wdc_allocate_regs(&sc->sc_wdcdev); 319 320 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 321 channel++) { 322 cp = &sc->pciide_channels[channel]; 323 /* PIIX is compat-only */ 324 if (pciide_chansetup(sc, channel, 0) == 0) 325 continue; 326 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 327 if ((PIIX_IDETIM_READ(idetim, channel) & 328 PIIX_IDETIM_IDE) == 0) { 329 #if 1 330 aprint_normal("%s: %s channel ignored (disabled)\n", 331 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 332 cp->ata_channel.ch_flags |= ATACH_DISABLED; 333 continue; 334 #else 335 pcireg_t interface; 336 337 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 338 channel); 339 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 340 idetim); 341 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 342 sc->sc_tag, PCI_CLASS_REG)); 343 aprint_normal("channel %d idetim=%08x interface=%02x\n", 344 channel, idetim, interface); 345 #endif 346 } 347 /* PIIX are compat-only pciide devices */ 348 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 349 } 350 351 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 352 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 353 DEBUG_PROBE); 354 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 355 ATADEBUG_PRINT((", sidetim=0x%x", 356 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 357 DEBUG_PROBE); 358 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 359 ATADEBUG_PRINT((", udamreg 0x%x", 360 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 361 DEBUG_PROBE); 362 } 363 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 364 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 365 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 366 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 367 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 368 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 369 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 370 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 371 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 372 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 373 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 374 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 375 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 376 DEBUG_PROBE); 377 } 378 } 379 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 380 } 381 382 static void 383 piix_setup_channel(struct ata_channel *chp) 384 { 385 u_int8_t mode[2], drive; 386 u_int32_t oidetim, idetim, idedma_ctl; 387 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 388 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 389 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 390 391 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 392 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 393 idedma_ctl = 0; 394 395 /* set up new idetim: Enable IDE registers decode */ 396 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 397 chp->ch_channel); 398 399 /* setup DMA */ 400 pciide_channel_dma_setup(cp); 401 402 /* 403 * Here we have to mess up with drives mode: PIIX can't have 404 * different timings for master and slave drives. 405 * We need to find the best combination. 406 */ 407 408 /* If both drives supports DMA, take the lower mode */ 409 if ((drvp[0].drive_flags & DRIVE_DMA) && 410 (drvp[1].drive_flags & DRIVE_DMA)) { 411 mode[0] = mode[1] = 412 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 413 drvp[0].DMA_mode = mode[0]; 414 drvp[1].DMA_mode = mode[1]; 415 goto ok; 416 } 417 /* 418 * If only one drive supports DMA, use its mode, and 419 * put the other one in PIO mode 0 if mode not compatible 420 */ 421 if (drvp[0].drive_flags & DRIVE_DMA) { 422 mode[0] = drvp[0].DMA_mode; 423 mode[1] = drvp[1].PIO_mode; 424 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 425 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 426 mode[1] = drvp[1].PIO_mode = 0; 427 goto ok; 428 } 429 if (drvp[1].drive_flags & DRIVE_DMA) { 430 mode[1] = drvp[1].DMA_mode; 431 mode[0] = drvp[0].PIO_mode; 432 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 433 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 434 mode[0] = drvp[0].PIO_mode = 0; 435 goto ok; 436 } 437 /* 438 * If both drives are not DMA, takes the lower mode, unless 439 * one of them is PIO mode < 2 440 */ 441 if (drvp[0].PIO_mode < 2) { 442 mode[0] = drvp[0].PIO_mode = 0; 443 mode[1] = drvp[1].PIO_mode; 444 } else if (drvp[1].PIO_mode < 2) { 445 mode[1] = drvp[1].PIO_mode = 0; 446 mode[0] = drvp[0].PIO_mode; 447 } else { 448 mode[0] = mode[1] = 449 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 450 drvp[0].PIO_mode = mode[0]; 451 drvp[1].PIO_mode = mode[1]; 452 } 453 ok: /* The modes are setup */ 454 for (drive = 0; drive < 2; drive++) { 455 if (drvp[drive].drive_flags & DRIVE_DMA) { 456 idetim |= piix_setup_idetim_timings( 457 mode[drive], 1, chp->ch_channel); 458 goto end; 459 } 460 } 461 /* If we are there, none of the drives are DMA */ 462 if (mode[0] >= 2) 463 idetim |= piix_setup_idetim_timings( 464 mode[0], 0, chp->ch_channel); 465 else 466 idetim |= piix_setup_idetim_timings( 467 mode[1], 0, chp->ch_channel); 468 end: /* 469 * timing mode is now set up in the controller. Enable 470 * it per-drive 471 */ 472 for (drive = 0; drive < 2; drive++) { 473 /* If no drive, skip */ 474 if ((drvp[drive].drive_flags & DRIVE) == 0) 475 continue; 476 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 477 if (drvp[drive].drive_flags & DRIVE_DMA) 478 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 479 } 480 if (idedma_ctl != 0) { 481 /* Add software bits in status register */ 482 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 483 idedma_ctl); 484 } 485 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 486 } 487 488 static void 489 piix3_4_setup_channel(struct ata_channel *chp) 490 { 491 struct ata_drive_datas *drvp; 492 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 493 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 494 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 495 struct wdc_softc *wdc = &sc->sc_wdcdev; 496 int drive, s; 497 int channel = chp->ch_channel; 498 499 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 500 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 501 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 502 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 503 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 504 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 505 PIIX_SIDETIM_RTC_MASK(channel)); 506 idedma_ctl = 0; 507 508 /* set up new idetim: Enable IDE registers decode */ 509 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 510 511 /* setup DMA if needed */ 512 pciide_channel_dma_setup(cp); 513 514 for (drive = 0; drive < 2; drive++) { 515 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 516 PIIX_UDMATIM_SET(0x3, channel, drive)); 517 drvp = &chp->ch_drive[drive]; 518 /* If no drive, skip */ 519 if ((drvp->drive_flags & DRIVE) == 0) 520 continue; 521 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 522 (drvp->drive_flags & DRIVE_UDMA) == 0)) 523 goto pio; 524 525 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 526 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 527 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 528 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 529 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 530 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 531 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 532 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 533 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 534 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 535 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 536 ideconf |= PIIX_CONFIG_PINGPONG; 537 } 538 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 539 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 540 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 541 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 542 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 543 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 544 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 545 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 546 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 547 /* setup Ultra/100 */ 548 if (drvp->UDMA_mode > 2 && 549 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 550 drvp->UDMA_mode = 2; 551 if (drvp->UDMA_mode > 4) { 552 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 553 } else { 554 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 555 if (drvp->UDMA_mode > 2) { 556 ideconf |= PIIX_CONFIG_UDMA66(channel, 557 drive); 558 } else { 559 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 560 drive); 561 } 562 } 563 } 564 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 565 /* setup Ultra/66 */ 566 if (drvp->UDMA_mode > 2 && 567 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 568 drvp->UDMA_mode = 2; 569 if (drvp->UDMA_mode > 2) 570 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 571 else 572 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 573 } 574 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 575 (drvp->drive_flags & DRIVE_UDMA)) { 576 /* use Ultra/DMA */ 577 s = splbio(); 578 drvp->drive_flags &= ~DRIVE_DMA; 579 splx(s); 580 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 581 udmareg |= PIIX_UDMATIM_SET( 582 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 583 } else { 584 /* use Multiword DMA */ 585 s = splbio(); 586 drvp->drive_flags &= ~DRIVE_UDMA; 587 splx(s); 588 if (drive == 0) { 589 idetim |= piix_setup_idetim_timings( 590 drvp->DMA_mode, 1, channel); 591 } else { 592 sidetim |= piix_setup_sidetim_timings( 593 drvp->DMA_mode, 1, channel); 594 idetim =PIIX_IDETIM_SET(idetim, 595 PIIX_IDETIM_SITRE, channel); 596 } 597 } 598 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 599 600 pio: /* use PIO mode */ 601 idetim |= piix_setup_idetim_drvs(drvp); 602 if (drive == 0) { 603 idetim |= piix_setup_idetim_timings( 604 drvp->PIO_mode, 0, channel); 605 } else { 606 sidetim |= piix_setup_sidetim_timings( 607 drvp->PIO_mode, 0, channel); 608 idetim =PIIX_IDETIM_SET(idetim, 609 PIIX_IDETIM_SITRE, channel); 610 } 611 } 612 if (idedma_ctl != 0) { 613 /* Add software bits in status register */ 614 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 615 idedma_ctl); 616 } 617 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 618 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 619 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 620 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 621 } 622 623 624 /* setup ISP and RTC fields, based on mode */ 625 static u_int32_t 626 piix_setup_idetim_timings(mode, dma, channel) 627 u_int8_t mode; 628 u_int8_t dma; 629 u_int8_t channel; 630 { 631 632 if (dma) 633 return PIIX_IDETIM_SET(0, 634 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 635 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 636 channel); 637 else 638 return PIIX_IDETIM_SET(0, 639 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 640 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 641 channel); 642 } 643 644 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 645 static u_int32_t 646 piix_setup_idetim_drvs(drvp) 647 struct ata_drive_datas *drvp; 648 { 649 u_int32_t ret = 0; 650 struct ata_channel *chp = drvp->chnl_softc; 651 u_int8_t channel = chp->ch_channel; 652 u_int8_t drive = drvp->drive; 653 654 /* 655 * If drive is using UDMA, timings setups are independant 656 * So just check DMA and PIO here. 657 */ 658 if (drvp->drive_flags & DRIVE_DMA) { 659 /* if mode = DMA mode 0, use compatible timings */ 660 if ((drvp->drive_flags & DRIVE_DMA) && 661 drvp->DMA_mode == 0) { 662 drvp->PIO_mode = 0; 663 return ret; 664 } 665 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 666 /* 667 * PIO and DMA timings are the same, use fast timings for PIO 668 * too, else use compat timings. 669 */ 670 if ((piix_isp_pio[drvp->PIO_mode] != 671 piix_isp_dma[drvp->DMA_mode]) || 672 (piix_rtc_pio[drvp->PIO_mode] != 673 piix_rtc_dma[drvp->DMA_mode])) 674 drvp->PIO_mode = 0; 675 /* if PIO mode <= 2, use compat timings for PIO */ 676 if (drvp->PIO_mode <= 2) { 677 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 678 channel); 679 return ret; 680 } 681 } 682 683 /* 684 * Now setup PIO modes. If mode < 2, use compat timings. 685 * Else enable fast timings. Enable IORDY and prefetch/post 686 * if PIO mode >= 3. 687 */ 688 689 if (drvp->PIO_mode < 2) 690 return ret; 691 692 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 693 if (drvp->PIO_mode >= 3) { 694 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 695 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 696 } 697 return ret; 698 } 699 700 /* setup values in SIDETIM registers, based on mode */ 701 static u_int32_t 702 piix_setup_sidetim_timings(mode, dma, channel) 703 u_int8_t mode; 704 u_int8_t dma; 705 u_int8_t channel; 706 { 707 if (dma) 708 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 709 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 710 else 711 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 712 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 713 } 714 715 static void 716 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 717 { 718 struct pciide_channel *cp; 719 bus_size_t cmdsize, ctlsize; 720 pcireg_t interface; 721 int channel; 722 723 if (pciide_chipen(sc, pa) == 0) 724 return; 725 726 aprint_normal("%s: bus-master DMA support present", 727 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 728 pciide_mapreg_dma(sc, pa); 729 aprint_normal("\n"); 730 731 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 732 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 733 if (sc->sc_dma_ok) { 734 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 735 sc->sc_wdcdev.irqack = pciide_irqack; 736 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 737 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 738 } 739 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 740 741 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 742 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 743 744 interface = PCI_INTERFACE(pa->pa_class); 745 746 wdc_allocate_regs(&sc->sc_wdcdev); 747 748 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 749 channel++) { 750 cp = &sc->pciide_channels[channel]; 751 if (pciide_chansetup(sc, channel, interface) == 0) 752 continue; 753 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 754 pciide_pci_intr); 755 } 756 } 757
Indexes created Wed Oct 15 16:09:53 GMT 2025