piixide.c revision 1.19.2.3
1 /* $NetBSD: piixide.c,v 1.19.2.3 2005/07/23 14:51:55 riz Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct ata_channel *); 43 static void piix3_4_setup_channel(struct ata_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static void piixide_powerhook(int, void *); 50 static int piixide_match(struct device *, struct cfdata *, void *); 51 static void piixide_attach(struct device *, struct device *, void *); 52 53 static const struct pciide_product_desc pciide_intel_products[] = { 54 { PCI_PRODUCT_INTEL_82092AA, 55 0, 56 "Intel 82092AA IDE controller", 57 default_chip_map, 58 }, 59 { PCI_PRODUCT_INTEL_82371FB_IDE, 60 0, 61 "Intel 82371FB IDE controller (PIIX)", 62 piix_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371SB_IDE, 65 0, 66 "Intel 82371SB IDE Interface (PIIX3)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371AB_IDE, 70 0, 71 "Intel 82371AB IDE controller (PIIX4)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82440MX_IDE, 75 0, 76 "Intel 82440MX IDE controller", 77 piix_chip_map 78 }, 79 { PCI_PRODUCT_INTEL_82801AA_IDE, 80 0, 81 "Intel 82801AA IDE Controller (ICH)", 82 piix_chip_map, 83 }, 84 { PCI_PRODUCT_INTEL_82801AB_IDE, 85 0, 86 "Intel 82801AB IDE Controller (ICH0)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801BA_IDE, 90 0, 91 "Intel 82801BA IDE Controller (ICH2)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BAM_IDE, 95 0, 96 "Intel 82801BAM IDE Controller (ICH2-M)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 100 0, 101 "Intel 82801CA IDE Controller (ICH3)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801DB_IDE, 110 0, 111 "Intel 82801DB IDE Controller (ICH4)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DBM_IDE, 115 0, 116 "Intel 82801DBM IDE Controller (ICH4-M)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801EB_IDE, 120 0, 121 "Intel 82801EB IDE Controller (ICH5)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_SATA, 125 0, 126 "Intel 82801EB Serial ATA Controller", 127 piixsata_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801ER_SATA, 130 0, 131 "Intel 82801ER Serial ATA/Raid Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_6300ESB_IDE, 135 0, 136 "Intel 6300ESB IDE Controller (ICH5)", 137 piix_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_SATA, 140 0, 141 "Intel 6300ESB Serial ATA Controller", 142 piixsata_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_6300ESB_RAID, 145 0, 146 "Intel 6300ESB Serial ATA/RAID Controller", 147 piixsata_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_82801FB_IDE, 150 0, 151 "Intel 82801FB IDE Controller (ICH6)", 152 piix_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FB_SATA, 155 0, 156 "Intel 82801FB Serial ATA/Raid Controller", 157 piixsata_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FR_SATA, 160 0, 161 "Intel 82801FR Serial ATA/Raid Controller", 162 piixsata_chip_map, 163 }, 164 { PCI_PRODUCT_INTEL_82801FBM_SATA, 165 0, 166 "Intel 82801FBM Serial ATA Controller (ICH6)", 167 piixsata_chip_map, 168 }, 169 { PCI_PRODUCT_INTEL_82801G_IDE, 170 0, 171 "Intel 82801GB/GR IDE Controller (ICH7)", 172 piix_chip_map, 173 }, 174 { PCI_PRODUCT_INTEL_82801G_SATA, 175 0, 176 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 177 piixsata_chip_map, 178 }, 179 { 0, 180 0, 181 NULL, 182 NULL 183 } 184 }; 185 186 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 187 piixide_match, piixide_attach, NULL, NULL); 188 189 static int 190 piixide_match(struct device *parent, struct cfdata *match, void *aux) 191 { 192 struct pci_attach_args *pa = aux; 193 194 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 195 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 196 return (2); 197 } 198 return (0); 199 } 200 201 static void 202 piixide_attach(struct device *parent, struct device *self, void *aux) 203 { 204 struct pci_attach_args *pa = aux; 205 struct pciide_softc *sc = (struct pciide_softc *)self; 206 207 pciide_common_attach(sc, pa, 208 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 209 210 /* Setup our powerhook */ 211 sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc); 212 if (sc->sc_powerhook == NULL) 213 printf("%s: WARNING: unable to establish PCI power hook\n", 214 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 215 } 216 217 static void 218 piixide_powerhook(int why, void *hdl) 219 { 220 struct pciide_softc *sc = (struct pciide_softc *)hdl; 221 222 switch (why) { 223 case PWR_SUSPEND: 224 case PWR_STANDBY: 225 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 226 break; 227 case PWR_RESUME: 228 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 229 break; 230 case PWR_SOFTSUSPEND: 231 case PWR_SOFTSTANDBY: 232 case PWR_SOFTRESUME: 233 break; 234 } 235 236 return; 237 } 238 239 static void 240 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 241 { 242 struct pciide_channel *cp; 243 int channel; 244 u_int32_t idetim; 245 bus_size_t cmdsize, ctlsize; 246 247 if (pciide_chipen(sc, pa) == 0) 248 return; 249 250 aprint_normal("%s: bus-master DMA support present", 251 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 252 pciide_mapreg_dma(sc, pa); 253 aprint_normal("\n"); 254 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 255 if (sc->sc_dma_ok) { 256 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 257 sc->sc_wdcdev.irqack = pciide_irqack; 258 switch(sc->sc_pp->ide_product) { 259 case PCI_PRODUCT_INTEL_82371AB_IDE: 260 case PCI_PRODUCT_INTEL_82440MX_IDE: 261 case PCI_PRODUCT_INTEL_82801AA_IDE: 262 case PCI_PRODUCT_INTEL_82801AB_IDE: 263 case PCI_PRODUCT_INTEL_82801BA_IDE: 264 case PCI_PRODUCT_INTEL_82801BAM_IDE: 265 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 266 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 267 case PCI_PRODUCT_INTEL_82801DB_IDE: 268 case PCI_PRODUCT_INTEL_82801DBM_IDE: 269 case PCI_PRODUCT_INTEL_82801EB_IDE: 270 case PCI_PRODUCT_INTEL_6300ESB_IDE: 271 case PCI_PRODUCT_INTEL_82801FB_IDE: 272 case PCI_PRODUCT_INTEL_82801G_IDE: 273 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 274 } 275 } 276 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 277 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 278 switch(sc->sc_pp->ide_product) { 279 case PCI_PRODUCT_INTEL_82801AA_IDE: 280 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 281 break; 282 case PCI_PRODUCT_INTEL_82801BA_IDE: 283 case PCI_PRODUCT_INTEL_82801BAM_IDE: 284 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 285 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 286 case PCI_PRODUCT_INTEL_82801DB_IDE: 287 case PCI_PRODUCT_INTEL_82801DBM_IDE: 288 case PCI_PRODUCT_INTEL_82801EB_IDE: 289 case PCI_PRODUCT_INTEL_6300ESB_IDE: 290 case PCI_PRODUCT_INTEL_82801FB_IDE: 291 case PCI_PRODUCT_INTEL_82801G_IDE: 292 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 293 break; 294 default: 295 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 296 } 297 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 298 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 299 else 300 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 301 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 302 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 303 304 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 305 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 306 DEBUG_PROBE); 307 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 308 ATADEBUG_PRINT((", sidetim=0x%x", 309 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 310 DEBUG_PROBE); 311 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 312 ATADEBUG_PRINT((", udamreg 0x%x", 313 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 314 DEBUG_PROBE); 315 } 316 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 317 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 318 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 319 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 320 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 321 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 322 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 323 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 324 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 325 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 326 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 327 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 328 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 329 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 330 DEBUG_PROBE); 331 } 332 333 } 334 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 335 336 wdc_allocate_regs(&sc->sc_wdcdev); 337 338 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 339 channel++) { 340 cp = &sc->pciide_channels[channel]; 341 /* PIIX is compat-only */ 342 if (pciide_chansetup(sc, channel, 0) == 0) 343 continue; 344 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 345 if ((PIIX_IDETIM_READ(idetim, channel) & 346 PIIX_IDETIM_IDE) == 0) { 347 #if 1 348 aprint_normal("%s: %s channel ignored (disabled)\n", 349 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 350 cp->ata_channel.ch_flags |= ATACH_DISABLED; 351 continue; 352 #else 353 pcireg_t interface; 354 355 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 356 channel); 357 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 358 idetim); 359 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 360 sc->sc_tag, PCI_CLASS_REG)); 361 aprint_normal("channel %d idetim=%08x interface=%02x\n", 362 channel, idetim, interface); 363 #endif 364 } 365 /* PIIX are compat-only pciide devices */ 366 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 367 } 368 369 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 370 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 371 DEBUG_PROBE); 372 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 373 ATADEBUG_PRINT((", sidetim=0x%x", 374 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 375 DEBUG_PROBE); 376 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 377 ATADEBUG_PRINT((", udamreg 0x%x", 378 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 379 DEBUG_PROBE); 380 } 381 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 382 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 383 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 384 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 385 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 386 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 387 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 388 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 389 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 390 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 391 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 392 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 393 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 394 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 395 DEBUG_PROBE); 396 } 397 } 398 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 399 } 400 401 static void 402 piix_setup_channel(struct ata_channel *chp) 403 { 404 u_int8_t mode[2], drive; 405 u_int32_t oidetim, idetim, idedma_ctl; 406 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 407 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 408 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 409 410 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 411 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 412 idedma_ctl = 0; 413 414 /* set up new idetim: Enable IDE registers decode */ 415 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 416 chp->ch_channel); 417 418 /* setup DMA */ 419 pciide_channel_dma_setup(cp); 420 421 /* 422 * Here we have to mess up with drives mode: PIIX can't have 423 * different timings for master and slave drives. 424 * We need to find the best combination. 425 */ 426 427 /* If both drives supports DMA, take the lower mode */ 428 if ((drvp[0].drive_flags & DRIVE_DMA) && 429 (drvp[1].drive_flags & DRIVE_DMA)) { 430 mode[0] = mode[1] = 431 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 432 drvp[0].DMA_mode = mode[0]; 433 drvp[1].DMA_mode = mode[1]; 434 goto ok; 435 } 436 /* 437 * If only one drive supports DMA, use its mode, and 438 * put the other one in PIO mode 0 if mode not compatible 439 */ 440 if (drvp[0].drive_flags & DRIVE_DMA) { 441 mode[0] = drvp[0].DMA_mode; 442 mode[1] = drvp[1].PIO_mode; 443 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 444 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 445 mode[1] = drvp[1].PIO_mode = 0; 446 goto ok; 447 } 448 if (drvp[1].drive_flags & DRIVE_DMA) { 449 mode[1] = drvp[1].DMA_mode; 450 mode[0] = drvp[0].PIO_mode; 451 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 452 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 453 mode[0] = drvp[0].PIO_mode = 0; 454 goto ok; 455 } 456 /* 457 * If both drives are not DMA, takes the lower mode, unless 458 * one of them is PIO mode < 2 459 */ 460 if (drvp[0].PIO_mode < 2) { 461 mode[0] = drvp[0].PIO_mode = 0; 462 mode[1] = drvp[1].PIO_mode; 463 } else if (drvp[1].PIO_mode < 2) { 464 mode[1] = drvp[1].PIO_mode = 0; 465 mode[0] = drvp[0].PIO_mode; 466 } else { 467 mode[0] = mode[1] = 468 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 469 drvp[0].PIO_mode = mode[0]; 470 drvp[1].PIO_mode = mode[1]; 471 } 472 ok: /* The modes are setup */ 473 for (drive = 0; drive < 2; drive++) { 474 if (drvp[drive].drive_flags & DRIVE_DMA) { 475 idetim |= piix_setup_idetim_timings( 476 mode[drive], 1, chp->ch_channel); 477 goto end; 478 } 479 } 480 /* If we are there, none of the drives are DMA */ 481 if (mode[0] >= 2) 482 idetim |= piix_setup_idetim_timings( 483 mode[0], 0, chp->ch_channel); 484 else 485 idetim |= piix_setup_idetim_timings( 486 mode[1], 0, chp->ch_channel); 487 end: /* 488 * timing mode is now set up in the controller. Enable 489 * it per-drive 490 */ 491 for (drive = 0; drive < 2; drive++) { 492 /* If no drive, skip */ 493 if ((drvp[drive].drive_flags & DRIVE) == 0) 494 continue; 495 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 496 if (drvp[drive].drive_flags & DRIVE_DMA) 497 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 498 } 499 if (idedma_ctl != 0) { 500 /* Add software bits in status register */ 501 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 502 idedma_ctl); 503 } 504 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 505 } 506 507 static void 508 piix3_4_setup_channel(struct ata_channel *chp) 509 { 510 struct ata_drive_datas *drvp; 511 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 512 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 513 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 514 struct wdc_softc *wdc = &sc->sc_wdcdev; 515 int drive, s; 516 int channel = chp->ch_channel; 517 518 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 519 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 520 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 521 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 522 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 523 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 524 PIIX_SIDETIM_RTC_MASK(channel)); 525 idedma_ctl = 0; 526 527 /* set up new idetim: Enable IDE registers decode */ 528 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 529 530 /* setup DMA if needed */ 531 pciide_channel_dma_setup(cp); 532 533 for (drive = 0; drive < 2; drive++) { 534 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 535 PIIX_UDMATIM_SET(0x3, channel, drive)); 536 drvp = &chp->ch_drive[drive]; 537 /* If no drive, skip */ 538 if ((drvp->drive_flags & DRIVE) == 0) 539 continue; 540 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 541 (drvp->drive_flags & DRIVE_UDMA) == 0)) 542 goto pio; 543 544 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 545 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 546 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 547 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 548 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 549 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 550 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 551 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 552 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 553 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 554 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 555 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 556 ideconf |= PIIX_CONFIG_PINGPONG; 557 } 558 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 559 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 560 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 561 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 562 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 563 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 564 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 565 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 566 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 567 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 568 /* setup Ultra/100 */ 569 if (drvp->UDMA_mode > 2 && 570 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 571 drvp->UDMA_mode = 2; 572 if (drvp->UDMA_mode > 4) { 573 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 574 } else { 575 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 576 if (drvp->UDMA_mode > 2) { 577 ideconf |= PIIX_CONFIG_UDMA66(channel, 578 drive); 579 } else { 580 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 581 drive); 582 } 583 } 584 } 585 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 586 /* setup Ultra/66 */ 587 if (drvp->UDMA_mode > 2 && 588 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 589 drvp->UDMA_mode = 2; 590 if (drvp->UDMA_mode > 2) 591 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 592 else 593 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 594 } 595 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 596 (drvp->drive_flags & DRIVE_UDMA)) { 597 /* use Ultra/DMA */ 598 s = splbio(); 599 drvp->drive_flags &= ~DRIVE_DMA; 600 splx(s); 601 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 602 udmareg |= PIIX_UDMATIM_SET( 603 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 604 } else { 605 /* use Multiword DMA */ 606 s = splbio(); 607 drvp->drive_flags &= ~DRIVE_UDMA; 608 splx(s); 609 if (drive == 0) { 610 idetim |= piix_setup_idetim_timings( 611 drvp->DMA_mode, 1, channel); 612 } else { 613 sidetim |= piix_setup_sidetim_timings( 614 drvp->DMA_mode, 1, channel); 615 idetim =PIIX_IDETIM_SET(idetim, 616 PIIX_IDETIM_SITRE, channel); 617 } 618 } 619 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 620 621 pio: /* use PIO mode */ 622 idetim |= piix_setup_idetim_drvs(drvp); 623 if (drive == 0) { 624 idetim |= piix_setup_idetim_timings( 625 drvp->PIO_mode, 0, channel); 626 } else { 627 sidetim |= piix_setup_sidetim_timings( 628 drvp->PIO_mode, 0, channel); 629 idetim =PIIX_IDETIM_SET(idetim, 630 PIIX_IDETIM_SITRE, channel); 631 } 632 } 633 if (idedma_ctl != 0) { 634 /* Add software bits in status register */ 635 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 636 idedma_ctl); 637 } 638 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 639 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 640 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 641 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 642 } 643 644 645 /* setup ISP and RTC fields, based on mode */ 646 static u_int32_t 647 piix_setup_idetim_timings(mode, dma, channel) 648 u_int8_t mode; 649 u_int8_t dma; 650 u_int8_t channel; 651 { 652 653 if (dma) 654 return PIIX_IDETIM_SET(0, 655 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 656 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 657 channel); 658 else 659 return PIIX_IDETIM_SET(0, 660 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 661 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 662 channel); 663 } 664 665 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 666 static u_int32_t 667 piix_setup_idetim_drvs(drvp) 668 struct ata_drive_datas *drvp; 669 { 670 u_int32_t ret = 0; 671 struct ata_channel *chp = drvp->chnl_softc; 672 u_int8_t channel = chp->ch_channel; 673 u_int8_t drive = drvp->drive; 674 675 /* 676 * If drive is using UDMA, timings setups are independant 677 * So just check DMA and PIO here. 678 */ 679 if (drvp->drive_flags & DRIVE_DMA) { 680 /* if mode = DMA mode 0, use compatible timings */ 681 if ((drvp->drive_flags & DRIVE_DMA) && 682 drvp->DMA_mode == 0) { 683 drvp->PIO_mode = 0; 684 return ret; 685 } 686 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 687 /* 688 * PIO and DMA timings are the same, use fast timings for PIO 689 * too, else use compat timings. 690 */ 691 if ((piix_isp_pio[drvp->PIO_mode] != 692 piix_isp_dma[drvp->DMA_mode]) || 693 (piix_rtc_pio[drvp->PIO_mode] != 694 piix_rtc_dma[drvp->DMA_mode])) 695 drvp->PIO_mode = 0; 696 /* if PIO mode <= 2, use compat timings for PIO */ 697 if (drvp->PIO_mode <= 2) { 698 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 699 channel); 700 return ret; 701 } 702 } 703 704 /* 705 * Now setup PIO modes. If mode < 2, use compat timings. 706 * Else enable fast timings. Enable IORDY and prefetch/post 707 * if PIO mode >= 3. 708 */ 709 710 if (drvp->PIO_mode < 2) 711 return ret; 712 713 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 714 if (drvp->PIO_mode >= 3) { 715 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 716 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 717 } 718 return ret; 719 } 720 721 /* setup values in SIDETIM registers, based on mode */ 722 static u_int32_t 723 piix_setup_sidetim_timings(mode, dma, channel) 724 u_int8_t mode; 725 u_int8_t dma; 726 u_int8_t channel; 727 { 728 if (dma) 729 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 730 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 731 else 732 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 733 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 734 } 735 736 static void 737 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 738 { 739 struct pciide_channel *cp; 740 bus_size_t cmdsize, ctlsize; 741 pcireg_t interface, cmdsts; 742 int channel; 743 744 if (pciide_chipen(sc, pa) == 0) 745 return; 746 747 aprint_normal("%s: bus-master DMA support present", 748 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 749 pciide_mapreg_dma(sc, pa); 750 aprint_normal("\n"); 751 752 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 753 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 754 if (sc->sc_dma_ok) { 755 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 756 sc->sc_wdcdev.irqack = pciide_irqack; 757 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 758 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 759 } 760 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 761 762 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 763 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 764 765 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 766 cmdsts &= ~0x0400; 767 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 768 769 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 770 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 771 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 772 773 interface = PCI_INTERFACE(pa->pa_class); 774 775 wdc_allocate_regs(&sc->sc_wdcdev); 776 777 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 778 channel++) { 779 cp = &sc->pciide_channels[channel]; 780 if (pciide_chansetup(sc, channel, interface) == 0) 781 continue; 782 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 783 pciide_pci_intr); 784 } 785 } 786
Indexes created Wed Oct 15 16:09:53 GMT 2025