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piixide.c revision 1.19.2.5
      1 /*	$NetBSD: piixide.c,v 1.19.2.5 2008/04/08 21:29:46 jdc Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Manuel Bouyer.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/param.h>
     33 #include <sys/systm.h>
     34 
     35 #include <dev/pci/pcivar.h>
     36 #include <dev/pci/pcidevs.h>
     37 #include <dev/pci/pciidereg.h>
     38 #include <dev/pci/pciidevar.h>
     39 #include <dev/pci/pciide_piix_reg.h>
     40 
     41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *);
     42 static void piix_setup_channel(struct ata_channel *);
     43 static void piix3_4_setup_channel(struct ata_channel *);
     44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t);
     45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *);
     46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t);
     47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *);
     48 
     49 static void piixide_powerhook(int, void *);
     50 static int  piixide_match(struct device *, struct cfdata *, void *);
     51 static void piixide_attach(struct device *, struct device *, void *);
     52 
     53 static const struct pciide_product_desc pciide_intel_products[] =  {
     54 	{ PCI_PRODUCT_INTEL_82092AA,
     55 	  0,
     56 	  "Intel 82092AA IDE controller",
     57 	  default_chip_map,
     58 	},
     59 	{ PCI_PRODUCT_INTEL_82371FB_IDE,
     60 	  0,
     61 	  "Intel 82371FB IDE controller (PIIX)",
     62 	  piix_chip_map,
     63 	},
     64 	{ PCI_PRODUCT_INTEL_82371SB_IDE,
     65 	  0,
     66 	  "Intel 82371SB IDE Interface (PIIX3)",
     67 	  piix_chip_map,
     68 	},
     69 	{ PCI_PRODUCT_INTEL_82371AB_IDE,
     70 	  0,
     71 	  "Intel 82371AB IDE controller (PIIX4)",
     72 	  piix_chip_map,
     73 	},
     74 	{ PCI_PRODUCT_INTEL_82440MX_IDE,
     75 	  0,
     76 	  "Intel 82440MX IDE controller",
     77 	  piix_chip_map
     78 	},
     79 	{ PCI_PRODUCT_INTEL_82801AA_IDE,
     80 	  0,
     81 	  "Intel 82801AA IDE Controller (ICH)",
     82 	  piix_chip_map,
     83 	},
     84 	{ PCI_PRODUCT_INTEL_82801AB_IDE,
     85 	  0,
     86 	  "Intel 82801AB IDE Controller (ICH0)",
     87 	  piix_chip_map,
     88 	},
     89 	{ PCI_PRODUCT_INTEL_82801BA_IDE,
     90 	  0,
     91 	  "Intel 82801BA IDE Controller (ICH2)",
     92 	  piix_chip_map,
     93 	},
     94 	{ PCI_PRODUCT_INTEL_82801BAM_IDE,
     95 	  0,
     96 	  "Intel 82801BAM IDE Controller (ICH2-M)",
     97 	  piix_chip_map,
     98 	},
     99 	{ PCI_PRODUCT_INTEL_82801CA_IDE_1,
    100 	  0,
    101 	  "Intel 82801CA IDE Controller (ICH3)",
    102 	  piix_chip_map,
    103 	},
    104 	{ PCI_PRODUCT_INTEL_82801CA_IDE_2,
    105 	  0,
    106 	  "Intel 82801CA IDE Controller (ICH3)",
    107 	  piix_chip_map,
    108 	},
    109 	{ PCI_PRODUCT_INTEL_82801DB_IDE,
    110 	  0,
    111 	  "Intel 82801DB IDE Controller (ICH4)",
    112 	  piix_chip_map,
    113 	},
    114 	{ PCI_PRODUCT_INTEL_82801DBM_IDE,
    115 	  0,
    116 	  "Intel 82801DBM IDE Controller (ICH4-M)",
    117 	  piix_chip_map,
    118 	},
    119 	{ PCI_PRODUCT_INTEL_82801EB_IDE,
    120 	  0,
    121 	  "Intel 82801EB IDE Controller (ICH5)",
    122 	  piix_chip_map,
    123 	},
    124 	{ PCI_PRODUCT_INTEL_82801EB_SATA,
    125 	  0,
    126 	  "Intel 82801EB Serial ATA Controller",
    127 	  piixsata_chip_map,
    128 	},
    129 	{ PCI_PRODUCT_INTEL_82801ER_SATA,
    130 	  0,
    131 	  "Intel 82801ER Serial ATA/Raid Controller",
    132 	  piixsata_chip_map,
    133 	},
    134 	{ PCI_PRODUCT_INTEL_6300ESB_IDE,
    135 	  0,
    136 	  "Intel 6300ESB IDE Controller (ICH5)",
    137 	  piix_chip_map,
    138 	},
    139 	{ PCI_PRODUCT_INTEL_6300ESB_SATA,
    140 	  0,
    141 	  "Intel 6300ESB Serial ATA Controller",
    142 	  piixsata_chip_map,
    143 	},
    144 	{ PCI_PRODUCT_INTEL_6300ESB_RAID,
    145 	  0,
    146 	  "Intel 6300ESB Serial ATA/RAID Controller",
    147 	  piixsata_chip_map,
    148 	},
    149 	{ PCI_PRODUCT_INTEL_82801FB_IDE,
    150 	  0,
    151 	  "Intel 82801FB IDE Controller (ICH6)",
    152 	  piix_chip_map,
    153 	},
    154 	{ PCI_PRODUCT_INTEL_82801FB_SATA,
    155 	  0,
    156 	  "Intel 82801FB Serial ATA/Raid Controller",
    157 	  piixsata_chip_map,
    158 	},
    159 	{ PCI_PRODUCT_INTEL_82801FR_SATA,
    160 	  0,
    161 	  "Intel 82801FR Serial ATA/Raid Controller",
    162 	  piixsata_chip_map,
    163 	},
    164 	{ PCI_PRODUCT_INTEL_82801FBM_SATA,
    165 	  0,
    166 	  "Intel 82801FBM Serial ATA Controller (ICH6)",
    167 	  piixsata_chip_map,
    168 	},
    169 	{ PCI_PRODUCT_INTEL_82801G_IDE,
    170 	  0,
    171 	  "Intel 82801GB/GR IDE Controller (ICH7)",
    172 	  piix_chip_map,
    173 	},
    174 	{ PCI_PRODUCT_INTEL_82801G_SATA,
    175 	  0,
    176 	  "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)",
    177 	  piixsata_chip_map,
    178 	},
    179 	{ PCI_PRODUCT_INTEL_63XXESB_IDE,
    180 	  0,
    181 	  "Intel 631xESB/632xESB IDE Controller",
    182 	  piix_chip_map,
    183 	},
    184 	{ PCI_PRODUCT_INTEL_63XXESB_SATA,
    185 	  0,
    186 	  "Intel 631xESB/632xESB Serial ATA Controller",
    187 	  piixsata_chip_map,
    188 	},
    189 	{ 0,
    190 	  0,
    191 	  NULL,
    192 	  NULL
    193 	}
    194 };
    195 
    196 CFATTACH_DECL(piixide, sizeof(struct pciide_softc),
    197     piixide_match, piixide_attach, NULL, NULL);
    198 
    199 static int
    200 piixide_match(struct device *parent, struct cfdata *match, void *aux)
    201 {
    202 	struct pci_attach_args *pa = aux;
    203 
    204 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
    205 		if (pciide_lookup_product(pa->pa_id, pciide_intel_products))
    206 			return (2);
    207 	}
    208 	return (0);
    209 }
    210 
    211 static void
    212 piixide_attach(struct device *parent, struct device *self, void *aux)
    213 {
    214 	struct pci_attach_args *pa = aux;
    215 	struct pciide_softc *sc = (struct pciide_softc *)self;
    216 
    217 	pciide_common_attach(sc, pa,
    218 	    pciide_lookup_product(pa->pa_id, pciide_intel_products));
    219 
    220 	/* Setup our powerhook */
    221 	sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc);
    222 	if (sc->sc_powerhook == NULL)
    223 		printf("%s: WARNING: unable to establish PCI power hook\n",
    224 		    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    225 }
    226 
    227 static void
    228 piixide_powerhook(int why, void *hdl)
    229 {
    230 	struct pciide_softc *sc = (struct pciide_softc *)hdl;
    231 
    232 	switch (why) {
    233 	case PWR_SUSPEND:
    234 	case PWR_STANDBY:
    235 		pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf);
    236 		break;
    237 	case PWR_RESUME:
    238 		pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf);
    239 		break;
    240 	case PWR_SOFTSUSPEND:
    241 	case PWR_SOFTSTANDBY:
    242 	case PWR_SOFTRESUME:
    243 		break;
    244 	}
    245 
    246 	return;
    247 }
    248 
    249 static void
    250 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
    251 {
    252 	struct pciide_channel *cp;
    253 	int channel;
    254 	u_int32_t idetim;
    255 	bus_size_t cmdsize, ctlsize;
    256 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
    257 
    258 	if (pciide_chipen(sc, pa) == 0)
    259 		return;
    260 
    261 	aprint_normal("%s: bus-master DMA support present",
    262 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    263 	pciide_mapreg_dma(sc, pa);
    264 	aprint_normal("\n");
    265 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    266 	if (sc->sc_dma_ok) {
    267 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
    268 		sc->sc_wdcdev.irqack = pciide_irqack;
    269 		switch(sc->sc_pp->ide_product) {
    270 		case PCI_PRODUCT_INTEL_82371AB_IDE:
    271 		case PCI_PRODUCT_INTEL_82440MX_IDE:
    272 		case PCI_PRODUCT_INTEL_82801AA_IDE:
    273 		case PCI_PRODUCT_INTEL_82801AB_IDE:
    274 		case PCI_PRODUCT_INTEL_82801BA_IDE:
    275 		case PCI_PRODUCT_INTEL_82801BAM_IDE:
    276 		case PCI_PRODUCT_INTEL_82801CA_IDE_1:
    277 		case PCI_PRODUCT_INTEL_82801CA_IDE_2:
    278 		case PCI_PRODUCT_INTEL_82801DB_IDE:
    279 		case PCI_PRODUCT_INTEL_82801DBM_IDE:
    280 		case PCI_PRODUCT_INTEL_82801EB_IDE:
    281 		case PCI_PRODUCT_INTEL_6300ESB_IDE:
    282 		case PCI_PRODUCT_INTEL_82801FB_IDE:
    283 		case PCI_PRODUCT_INTEL_82801G_IDE:
    284 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
    285 		}
    286 	}
    287 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    288 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    289 	switch(sc->sc_pp->ide_product) {
    290 	case PCI_PRODUCT_INTEL_82801AA_IDE:
    291 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    292 		break;
    293 	case PCI_PRODUCT_INTEL_82801BA_IDE:
    294 	case PCI_PRODUCT_INTEL_82801BAM_IDE:
    295 	case PCI_PRODUCT_INTEL_82801CA_IDE_1:
    296 	case PCI_PRODUCT_INTEL_82801CA_IDE_2:
    297 	case PCI_PRODUCT_INTEL_82801DB_IDE:
    298 	case PCI_PRODUCT_INTEL_82801DBM_IDE:
    299 	case PCI_PRODUCT_INTEL_82801EB_IDE:
    300 	case PCI_PRODUCT_INTEL_6300ESB_IDE:
    301 	case PCI_PRODUCT_INTEL_82801FB_IDE:
    302 	case PCI_PRODUCT_INTEL_82801G_IDE:
    303 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    304 		break;
    305 	default:
    306 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
    307 	}
    308 	if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE)
    309 		sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel;
    310 	else
    311 		sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel;
    312 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    313 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    314 
    315 	ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x",
    316 	    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
    317 	    DEBUG_PROBE);
    318 	if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
    319 		ATADEBUG_PRINT((", sidetim=0x%x",
    320 		    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
    321 		    DEBUG_PROBE);
    322 		if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
    323 			ATADEBUG_PRINT((", udamreg 0x%x",
    324 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
    325 			    DEBUG_PROBE);
    326 		}
    327 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
    328 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
    329 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
    330 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
    331 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
    332 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
    333 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
    334 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
    335 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
    336 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
    337 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
    338 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) {
    339 			ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
    340 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
    341 			    DEBUG_PROBE);
    342 		}
    343 
    344 	}
    345 	ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
    346 
    347 	wdc_allocate_regs(&sc->sc_wdcdev);
    348 
    349 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    350 	     channel++) {
    351 		cp = &sc->pciide_channels[channel];
    352 		if (pciide_chansetup(sc, channel, interface) == 0)
    353 			continue;
    354 		idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
    355 		if ((PIIX_IDETIM_READ(idetim, channel) &
    356 		    PIIX_IDETIM_IDE) == 0) {
    357 #if 1
    358 			aprint_normal("%s: %s channel ignored (disabled)\n",
    359 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
    360 			cp->ata_channel.ch_flags |= ATACH_DISABLED;
    361 			continue;
    362 #else
    363 			pcireg_t interface;
    364 
    365 			idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
    366 			    channel);
    367 			pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
    368 			    idetim);
    369 			interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
    370 			    sc->sc_tag, PCI_CLASS_REG));
    371 			aprint_normal("channel %d idetim=%08x interface=%02x\n",
    372 			    channel, idetim, interface);
    373 #endif
    374 		}
    375 		pciide_mapchan(pa, cp, interface,
    376 		    &cmdsize, &ctlsize, pciide_pci_intr);
    377 	}
    378 
    379 	ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
    380 	    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
    381 	    DEBUG_PROBE);
    382 	if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
    383 		ATADEBUG_PRINT((", sidetim=0x%x",
    384 		    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
    385 		    DEBUG_PROBE);
    386 		if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
    387 			ATADEBUG_PRINT((", udamreg 0x%x",
    388 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
    389 			    DEBUG_PROBE);
    390 		}
    391 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
    392 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
    393 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
    394 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
    395 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
    396 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
    397 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
    398 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
    399 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
    400 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
    401 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
    402 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) {
    403 			ATADEBUG_PRINT((", IDE_CONTROL 0x%x",
    404 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
    405 			    DEBUG_PROBE);
    406 		}
    407 	}
    408 	ATADEBUG_PRINT(("\n"), DEBUG_PROBE);
    409 }
    410 
    411 static void
    412 piix_setup_channel(struct ata_channel *chp)
    413 {
    414 	u_int8_t mode[2], drive;
    415 	u_int32_t oidetim, idetim, idedma_ctl;
    416 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    417 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    418 	struct ata_drive_datas *drvp = cp->ata_channel.ch_drive;
    419 
    420 	oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
    421 	idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel);
    422 	idedma_ctl = 0;
    423 
    424 	/* set up new idetim: Enable IDE registers decode */
    425 	idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
    426 	    chp->ch_channel);
    427 
    428 	/* setup DMA */
    429 	pciide_channel_dma_setup(cp);
    430 
    431 	/*
    432 	 * Here we have to mess up with drives mode: PIIX can't have
    433 	 * different timings for master and slave drives.
    434 	 * We need to find the best combination.
    435 	 */
    436 
    437 	/* If both drives supports DMA, take the lower mode */
    438 	if ((drvp[0].drive_flags & DRIVE_DMA) &&
    439 	    (drvp[1].drive_flags & DRIVE_DMA)) {
    440 		mode[0] = mode[1] =
    441 		    min(drvp[0].DMA_mode, drvp[1].DMA_mode);
    442 		    drvp[0].DMA_mode = mode[0];
    443 		    drvp[1].DMA_mode = mode[1];
    444 		goto ok;
    445 	}
    446 	/*
    447 	 * If only one drive supports DMA, use its mode, and
    448 	 * put the other one in PIO mode 0 if mode not compatible
    449 	 */
    450 	if (drvp[0].drive_flags & DRIVE_DMA) {
    451 		mode[0] = drvp[0].DMA_mode;
    452 		mode[1] = drvp[1].PIO_mode;
    453 		if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] ||
    454 		    piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]])
    455 			mode[1] = drvp[1].PIO_mode = 0;
    456 		goto ok;
    457 	}
    458 	if (drvp[1].drive_flags & DRIVE_DMA) {
    459 		mode[1] = drvp[1].DMA_mode;
    460 		mode[0] = drvp[0].PIO_mode;
    461 		if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] ||
    462 		    piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]])
    463 			mode[0] = drvp[0].PIO_mode = 0;
    464 		goto ok;
    465 	}
    466 	/*
    467 	 * If both drives are not DMA, takes the lower mode, unless
    468 	 * one of them is PIO mode < 2
    469 	 */
    470 	if (drvp[0].PIO_mode < 2) {
    471 		mode[0] = drvp[0].PIO_mode = 0;
    472 		mode[1] = drvp[1].PIO_mode;
    473 	} else if (drvp[1].PIO_mode < 2) {
    474 		mode[1] = drvp[1].PIO_mode = 0;
    475 		mode[0] = drvp[0].PIO_mode;
    476 	} else {
    477 		mode[0] = mode[1] =
    478 		    min(drvp[1].PIO_mode, drvp[0].PIO_mode);
    479 		drvp[0].PIO_mode = mode[0];
    480 		drvp[1].PIO_mode = mode[1];
    481 	}
    482 ok:	/* The modes are setup */
    483 	for (drive = 0; drive < 2; drive++) {
    484 		if (drvp[drive].drive_flags & DRIVE_DMA) {
    485 			idetim |= piix_setup_idetim_timings(
    486 			    mode[drive], 1, chp->ch_channel);
    487 			goto end;
    488 		}
    489 	}
    490 	/* If we are there, none of the drives are DMA */
    491 	if (mode[0] >= 2)
    492 		idetim |= piix_setup_idetim_timings(
    493 		    mode[0], 0, chp->ch_channel);
    494 	else
    495 		idetim |= piix_setup_idetim_timings(
    496 		    mode[1], 0, chp->ch_channel);
    497 end:	/*
    498 	 * timing mode is now set up in the controller. Enable
    499 	 * it per-drive
    500 	 */
    501 	for (drive = 0; drive < 2; drive++) {
    502 		/* If no drive, skip */
    503 		if ((drvp[drive].drive_flags & DRIVE) == 0)
    504 			continue;
    505 		idetim |= piix_setup_idetim_drvs(&drvp[drive]);
    506 		if (drvp[drive].drive_flags & DRIVE_DMA)
    507 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    508 	}
    509 	if (idedma_ctl != 0) {
    510 		/* Add software bits in status register */
    511 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    512 		    idedma_ctl);
    513 	}
    514 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
    515 }
    516 
    517 static void
    518 piix3_4_setup_channel(struct ata_channel *chp)
    519 {
    520 	struct ata_drive_datas *drvp;
    521 	u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl;
    522 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    523 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    524 	struct wdc_softc *wdc = &sc->sc_wdcdev;
    525 	int drive, s;
    526 	int channel = chp->ch_channel;
    527 
    528 	oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
    529 	sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM);
    530 	udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG);
    531 	ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG);
    532 	idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel);
    533 	sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) |
    534 	    PIIX_SIDETIM_RTC_MASK(channel));
    535 	idedma_ctl = 0;
    536 
    537 	/* set up new idetim: Enable IDE registers decode */
    538 	idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel);
    539 
    540 	/* setup DMA if needed */
    541 	pciide_channel_dma_setup(cp);
    542 
    543 	for (drive = 0; drive < 2; drive++) {
    544 		udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) |
    545 		    PIIX_UDMATIM_SET(0x3, channel, drive));
    546 		drvp = &chp->ch_drive[drive];
    547 		/* If no drive, skip */
    548 		if ((drvp->drive_flags & DRIVE) == 0)
    549 			continue;
    550 		if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
    551 		    (drvp->drive_flags & DRIVE_UDMA) == 0))
    552 			goto pio;
    553 
    554 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
    555 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
    556 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
    557 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
    558 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
    559 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
    560 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
    561 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
    562 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
    563 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
    564 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
    565 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) {
    566 			ideconf |= PIIX_CONFIG_PINGPONG;
    567 		}
    568 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
    569 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
    570 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
    571 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
    572 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
    573 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
    574 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
    575 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
    576 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE ||
    577 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) {
    578 			/* setup Ultra/100 */
    579 			if (drvp->UDMA_mode > 2 &&
    580 			    (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
    581 				drvp->UDMA_mode = 2;
    582 			if (drvp->UDMA_mode > 4) {
    583 				ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
    584 			} else {
    585 				ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
    586 				if (drvp->UDMA_mode > 2) {
    587 					ideconf |= PIIX_CONFIG_UDMA66(channel,
    588 					    drive);
    589 				} else {
    590 					ideconf &= ~PIIX_CONFIG_UDMA66(channel,
    591 					    drive);
    592 				}
    593 			}
    594 		}
    595 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) {
    596 			/* setup Ultra/66 */
    597 			if (drvp->UDMA_mode > 2 &&
    598 			    (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
    599 				drvp->UDMA_mode = 2;
    600 			if (drvp->UDMA_mode > 2)
    601 				ideconf |= PIIX_CONFIG_UDMA66(channel, drive);
    602 			else
    603 				ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive);
    604 		}
    605 		if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) &&
    606 		    (drvp->drive_flags & DRIVE_UDMA)) {
    607 			/* use Ultra/DMA */
    608 			s = splbio();
    609 			drvp->drive_flags &= ~DRIVE_DMA;
    610 			splx(s);
    611 			udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive);
    612 			udmareg |= PIIX_UDMATIM_SET(
    613 			    piix4_sct_udma[drvp->UDMA_mode], channel, drive);
    614 		} else {
    615 			/* use Multiword DMA */
    616 			s = splbio();
    617 			drvp->drive_flags &= ~DRIVE_UDMA;
    618 			splx(s);
    619 			if (drive == 0) {
    620 				idetim |= piix_setup_idetim_timings(
    621 				    drvp->DMA_mode, 1, channel);
    622 			} else {
    623 				sidetim |= piix_setup_sidetim_timings(
    624 					drvp->DMA_mode, 1, channel);
    625 				idetim =PIIX_IDETIM_SET(idetim,
    626 				    PIIX_IDETIM_SITRE, channel);
    627 			}
    628 		}
    629 		idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    630 
    631 pio:		/* use PIO mode */
    632 		idetim |= piix_setup_idetim_drvs(drvp);
    633 		if (drive == 0) {
    634 			idetim |= piix_setup_idetim_timings(
    635 			    drvp->PIO_mode, 0, channel);
    636 		} else {
    637 			sidetim |= piix_setup_sidetim_timings(
    638 				drvp->PIO_mode, 0, channel);
    639 			idetim =PIIX_IDETIM_SET(idetim,
    640 			    PIIX_IDETIM_SITRE, channel);
    641 		}
    642 	}
    643 	if (idedma_ctl != 0) {
    644 		/* Add software bits in status register */
    645 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    646 		    idedma_ctl);
    647 	}
    648 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
    649 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim);
    650 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg);
    651 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf);
    652 }
    653 
    654 
    655 /* setup ISP and RTC fields, based on mode */
    656 static u_int32_t
    657 piix_setup_idetim_timings(mode, dma, channel)
    658 	u_int8_t mode;
    659 	u_int8_t dma;
    660 	u_int8_t channel;
    661 {
    662 
    663 	if (dma)
    664 		return PIIX_IDETIM_SET(0,
    665 		    PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) |
    666 		    PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]),
    667 		    channel);
    668 	else
    669 		return PIIX_IDETIM_SET(0,
    670 		    PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) |
    671 		    PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]),
    672 		    channel);
    673 }
    674 
    675 /* setup DTE, PPE, IE and TIME field based on PIO mode */
    676 static u_int32_t
    677 piix_setup_idetim_drvs(drvp)
    678 	struct ata_drive_datas *drvp;
    679 {
    680 	u_int32_t ret = 0;
    681 	struct ata_channel *chp = drvp->chnl_softc;
    682 	u_int8_t channel = chp->ch_channel;
    683 	u_int8_t drive = drvp->drive;
    684 
    685 	/*
    686 	 * If drive is using UDMA, timings setups are independant
    687 	 * So just check DMA and PIO here.
    688 	 */
    689 	if (drvp->drive_flags & DRIVE_DMA) {
    690 		/* if mode = DMA mode 0, use compatible timings */
    691 		if ((drvp->drive_flags & DRIVE_DMA) &&
    692 		    drvp->DMA_mode == 0) {
    693 			drvp->PIO_mode = 0;
    694 			return ret;
    695 		}
    696 		ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
    697 		/*
    698 		 * PIO and DMA timings are the same, use fast timings for PIO
    699 		 * too, else use compat timings.
    700 		 */
    701 		if ((piix_isp_pio[drvp->PIO_mode] !=
    702 		    piix_isp_dma[drvp->DMA_mode]) ||
    703 		    (piix_rtc_pio[drvp->PIO_mode] !=
    704 		    piix_rtc_dma[drvp->DMA_mode]))
    705 			drvp->PIO_mode = 0;
    706 		/* if PIO mode <= 2, use compat timings for PIO */
    707 		if (drvp->PIO_mode <= 2) {
    708 			ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive),
    709 			    channel);
    710 			return ret;
    711 		}
    712 	}
    713 
    714 	/*
    715 	 * Now setup PIO modes. If mode < 2, use compat timings.
    716 	 * Else enable fast timings. Enable IORDY and prefetch/post
    717 	 * if PIO mode >= 3.
    718 	 */
    719 
    720 	if (drvp->PIO_mode < 2)
    721 		return ret;
    722 
    723 	ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
    724 	if (drvp->PIO_mode >= 3) {
    725 		ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel);
    726 		ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel);
    727 	}
    728 	return ret;
    729 }
    730 
    731 /* setup values in SIDETIM registers, based on mode */
    732 static u_int32_t
    733 piix_setup_sidetim_timings(mode, dma, channel)
    734 	u_int8_t mode;
    735 	u_int8_t dma;
    736 	u_int8_t channel;
    737 {
    738 	if (dma)
    739 		return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) |
    740 		    PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel);
    741 	else
    742 		return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) |
    743 		    PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel);
    744 }
    745 
    746 static void
    747 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
    748 {
    749 	struct pciide_channel *cp;
    750 	bus_size_t cmdsize, ctlsize;
    751 	pcireg_t interface, cmdsts;
    752 	int channel;
    753 
    754 	if (pciide_chipen(sc, pa) == 0)
    755 		return;
    756 
    757 	aprint_normal("%s: bus-master DMA support present",
    758 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    759 	pciide_mapreg_dma(sc, pa);
    760 	aprint_normal("\n");
    761 
    762 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    763 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    764 	if (sc->sc_dma_ok) {
    765 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
    766 		sc->sc_wdcdev.irqack = pciide_irqack;
    767 		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    768 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    769 	}
    770 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
    771 
    772 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    773 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
    774 
    775 	cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
    776 	cmdsts &= ~0x0400;
    777 	pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts);
    778 
    779 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
    780 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
    781 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
    782 
    783 	interface = PCI_INTERFACE(pa->pa_class);
    784 
    785 	wdc_allocate_regs(&sc->sc_wdcdev);
    786 
    787 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
    788 	     channel++) {
    789 		cp = &sc->pciide_channels[channel];
    790 		if (pciide_chansetup(sc, channel, interface) == 0)
    791 			continue;
    792 		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
    793 		    pciide_pci_intr);
    794 	}
    795 }
    796