piixide.c revision 1.24
1 /* $NetBSD: piixide.c,v 1.24 2005/08/10 13:23:38 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.24 2005/08/10 13:23:38 bouyer Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 52 static void piixide_powerhook(int, void *); 53 static int piixide_match(struct device *, struct cfdata *, void *); 54 static void piixide_attach(struct device *, struct device *, void *); 55 56 static const struct pciide_product_desc pciide_intel_products[] = { 57 { PCI_PRODUCT_INTEL_82092AA, 58 0, 59 "Intel 82092AA IDE controller", 60 default_chip_map, 61 }, 62 { PCI_PRODUCT_INTEL_82371FB_IDE, 63 0, 64 "Intel 82371FB IDE controller (PIIX)", 65 piix_chip_map, 66 }, 67 { PCI_PRODUCT_INTEL_82371SB_IDE, 68 0, 69 "Intel 82371SB IDE Interface (PIIX3)", 70 piix_chip_map, 71 }, 72 { PCI_PRODUCT_INTEL_82371AB_IDE, 73 0, 74 "Intel 82371AB IDE controller (PIIX4)", 75 piix_chip_map, 76 }, 77 { PCI_PRODUCT_INTEL_82440MX_IDE, 78 0, 79 "Intel 82440MX IDE controller", 80 piix_chip_map 81 }, 82 { PCI_PRODUCT_INTEL_82801AA_IDE, 83 0, 84 "Intel 82801AA IDE Controller (ICH)", 85 piix_chip_map, 86 }, 87 { PCI_PRODUCT_INTEL_82801AB_IDE, 88 0, 89 "Intel 82801AB IDE Controller (ICH0)", 90 piix_chip_map, 91 }, 92 { PCI_PRODUCT_INTEL_82801BA_IDE, 93 0, 94 "Intel 82801BA IDE Controller (ICH2)", 95 piix_chip_map, 96 }, 97 { PCI_PRODUCT_INTEL_82801BAM_IDE, 98 0, 99 "Intel 82801BAM IDE Controller (ICH2-M)", 100 piix_chip_map, 101 }, 102 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 103 0, 104 "Intel 82801CA IDE Controller (ICH3)", 105 piix_chip_map, 106 }, 107 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 108 0, 109 "Intel 82801CA IDE Controller (ICH3)", 110 piix_chip_map, 111 }, 112 { PCI_PRODUCT_INTEL_82801DB_IDE, 113 0, 114 "Intel 82801DB IDE Controller (ICH4)", 115 piix_chip_map, 116 }, 117 { PCI_PRODUCT_INTEL_82801DBM_IDE, 118 0, 119 "Intel 82801DBM IDE Controller (ICH4-M)", 120 piix_chip_map, 121 }, 122 { PCI_PRODUCT_INTEL_82801EB_IDE, 123 0, 124 "Intel 82801EB IDE Controller (ICH5)", 125 piix_chip_map, 126 }, 127 { PCI_PRODUCT_INTEL_82801EB_SATA, 128 0, 129 "Intel 82801EB Serial ATA Controller", 130 piixsata_chip_map, 131 }, 132 { PCI_PRODUCT_INTEL_82801ER_SATA, 133 0, 134 "Intel 82801ER Serial ATA/Raid Controller", 135 piixsata_chip_map, 136 }, 137 { PCI_PRODUCT_INTEL_6300ESB_IDE, 138 0, 139 "Intel 6300ESB IDE Controller (ICH5)", 140 piix_chip_map, 141 }, 142 { PCI_PRODUCT_INTEL_6300ESB_SATA, 143 0, 144 "Intel 6300ESB Serial ATA Controller", 145 piixsata_chip_map, 146 }, 147 { PCI_PRODUCT_INTEL_6300ESB_RAID, 148 0, 149 "Intel 6300ESB Serial ATA/RAID Controller", 150 piixsata_chip_map, 151 }, 152 { PCI_PRODUCT_INTEL_82801FB_IDE, 153 0, 154 "Intel 82801FB IDE Controller (ICH6)", 155 piix_chip_map, 156 }, 157 { PCI_PRODUCT_INTEL_82801FB_SATA, 158 0, 159 "Intel 82801FB Serial ATA/Raid Controller", 160 piixsata_chip_map, 161 }, 162 { PCI_PRODUCT_INTEL_82801FR_SATA, 163 0, 164 "Intel 82801FR Serial ATA/Raid Controller", 165 piixsata_chip_map, 166 }, 167 { PCI_PRODUCT_INTEL_82801FBM_SATA, 168 0, 169 "Intel 82801FBM Serial ATA Controller (ICH6)", 170 piixsata_chip_map, 171 }, 172 { PCI_PRODUCT_INTEL_82801G_IDE, 173 0, 174 "Intel 82801GB/GR IDE Controller (ICH7)", 175 piix_chip_map, 176 }, 177 { PCI_PRODUCT_INTEL_82801G_SATA, 178 0, 179 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 180 piixsata_chip_map, 181 }, 182 { 0, 183 0, 184 NULL, 185 NULL 186 } 187 }; 188 189 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 190 piixide_match, piixide_attach, NULL, NULL); 191 192 static int 193 piixide_match(struct device *parent, struct cfdata *match, void *aux) 194 { 195 struct pci_attach_args *pa = aux; 196 197 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 198 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 199 return (2); 200 } 201 return (0); 202 } 203 204 static void 205 piixide_attach(struct device *parent, struct device *self, void *aux) 206 { 207 struct pci_attach_args *pa = aux; 208 struct pciide_softc *sc = (struct pciide_softc *)self; 209 210 pciide_common_attach(sc, pa, 211 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 212 213 /* Setup our powerhook */ 214 sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc); 215 if (sc->sc_powerhook == NULL) 216 printf("%s: WARNING: unable to establish PCI power hook\n", 217 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 218 } 219 220 static void 221 piixide_powerhook(int why, void *hdl) 222 { 223 struct pciide_softc *sc = (struct pciide_softc *)hdl; 224 225 switch (why) { 226 case PWR_SUSPEND: 227 case PWR_STANDBY: 228 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 229 break; 230 case PWR_RESUME: 231 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 232 break; 233 case PWR_SOFTSUSPEND: 234 case PWR_SOFTSTANDBY: 235 case PWR_SOFTRESUME: 236 break; 237 } 238 239 return; 240 } 241 242 static void 243 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 244 { 245 struct pciide_channel *cp; 246 int channel; 247 u_int32_t idetim; 248 bus_size_t cmdsize, ctlsize; 249 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 250 251 if (pciide_chipen(sc, pa) == 0) 252 return; 253 254 aprint_normal("%s: bus-master DMA support present", 255 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 256 pciide_mapreg_dma(sc, pa); 257 aprint_normal("\n"); 258 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 259 if (sc->sc_dma_ok) { 260 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 261 sc->sc_wdcdev.irqack = pciide_irqack; 262 switch(sc->sc_pp->ide_product) { 263 case PCI_PRODUCT_INTEL_82371AB_IDE: 264 case PCI_PRODUCT_INTEL_82440MX_IDE: 265 case PCI_PRODUCT_INTEL_82801AA_IDE: 266 case PCI_PRODUCT_INTEL_82801AB_IDE: 267 case PCI_PRODUCT_INTEL_82801BA_IDE: 268 case PCI_PRODUCT_INTEL_82801BAM_IDE: 269 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 270 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 271 case PCI_PRODUCT_INTEL_82801DB_IDE: 272 case PCI_PRODUCT_INTEL_82801DBM_IDE: 273 case PCI_PRODUCT_INTEL_82801EB_IDE: 274 case PCI_PRODUCT_INTEL_6300ESB_IDE: 275 case PCI_PRODUCT_INTEL_82801FB_IDE: 276 case PCI_PRODUCT_INTEL_82801G_IDE: 277 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 278 } 279 } 280 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 281 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 282 switch(sc->sc_pp->ide_product) { 283 case PCI_PRODUCT_INTEL_82801AA_IDE: 284 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 285 break; 286 case PCI_PRODUCT_INTEL_82801BA_IDE: 287 case PCI_PRODUCT_INTEL_82801BAM_IDE: 288 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 289 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 290 case PCI_PRODUCT_INTEL_82801DB_IDE: 291 case PCI_PRODUCT_INTEL_82801DBM_IDE: 292 case PCI_PRODUCT_INTEL_82801EB_IDE: 293 case PCI_PRODUCT_INTEL_6300ESB_IDE: 294 case PCI_PRODUCT_INTEL_82801FB_IDE: 295 case PCI_PRODUCT_INTEL_82801G_IDE: 296 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 297 break; 298 default: 299 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 300 } 301 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 302 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 303 else 304 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 305 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 306 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 307 308 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 309 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 310 DEBUG_PROBE); 311 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 312 ATADEBUG_PRINT((", sidetim=0x%x", 313 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 314 DEBUG_PROBE); 315 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 316 ATADEBUG_PRINT((", udamreg 0x%x", 317 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 318 DEBUG_PROBE); 319 } 320 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 321 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 322 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 323 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 324 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 325 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 326 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 327 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 328 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 329 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 330 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 331 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 332 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 333 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 334 DEBUG_PROBE); 335 } 336 337 } 338 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 339 340 wdc_allocate_regs(&sc->sc_wdcdev); 341 342 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 343 channel++) { 344 cp = &sc->pciide_channels[channel]; 345 if (pciide_chansetup(sc, channel, interface) == 0) 346 continue; 347 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 348 if ((PIIX_IDETIM_READ(idetim, channel) & 349 PIIX_IDETIM_IDE) == 0) { 350 #if 1 351 aprint_normal("%s: %s channel ignored (disabled)\n", 352 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 353 cp->ata_channel.ch_flags |= ATACH_DISABLED; 354 continue; 355 #else 356 pcireg_t interface; 357 358 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 359 channel); 360 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 361 idetim); 362 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 363 sc->sc_tag, PCI_CLASS_REG)); 364 aprint_normal("channel %d idetim=%08x interface=%02x\n", 365 channel, idetim, interface); 366 #endif 367 } 368 pciide_mapchan(pa, cp, interface, 369 &cmdsize, &ctlsize, pciide_pci_intr); 370 } 371 372 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 373 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 374 DEBUG_PROBE); 375 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 376 ATADEBUG_PRINT((", sidetim=0x%x", 377 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 378 DEBUG_PROBE); 379 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 380 ATADEBUG_PRINT((", udamreg 0x%x", 381 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 382 DEBUG_PROBE); 383 } 384 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 385 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 386 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 387 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 388 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 389 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 390 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 391 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 392 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 393 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 394 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 395 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 396 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 397 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 398 DEBUG_PROBE); 399 } 400 } 401 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 402 } 403 404 static void 405 piix_setup_channel(struct ata_channel *chp) 406 { 407 u_int8_t mode[2], drive; 408 u_int32_t oidetim, idetim, idedma_ctl; 409 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 410 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 411 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 412 413 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 414 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 415 idedma_ctl = 0; 416 417 /* set up new idetim: Enable IDE registers decode */ 418 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 419 chp->ch_channel); 420 421 /* setup DMA */ 422 pciide_channel_dma_setup(cp); 423 424 /* 425 * Here we have to mess up with drives mode: PIIX can't have 426 * different timings for master and slave drives. 427 * We need to find the best combination. 428 */ 429 430 /* If both drives supports DMA, take the lower mode */ 431 if ((drvp[0].drive_flags & DRIVE_DMA) && 432 (drvp[1].drive_flags & DRIVE_DMA)) { 433 mode[0] = mode[1] = 434 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 435 drvp[0].DMA_mode = mode[0]; 436 drvp[1].DMA_mode = mode[1]; 437 goto ok; 438 } 439 /* 440 * If only one drive supports DMA, use its mode, and 441 * put the other one in PIO mode 0 if mode not compatible 442 */ 443 if (drvp[0].drive_flags & DRIVE_DMA) { 444 mode[0] = drvp[0].DMA_mode; 445 mode[1] = drvp[1].PIO_mode; 446 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 447 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 448 mode[1] = drvp[1].PIO_mode = 0; 449 goto ok; 450 } 451 if (drvp[1].drive_flags & DRIVE_DMA) { 452 mode[1] = drvp[1].DMA_mode; 453 mode[0] = drvp[0].PIO_mode; 454 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 455 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 456 mode[0] = drvp[0].PIO_mode = 0; 457 goto ok; 458 } 459 /* 460 * If both drives are not DMA, takes the lower mode, unless 461 * one of them is PIO mode < 2 462 */ 463 if (drvp[0].PIO_mode < 2) { 464 mode[0] = drvp[0].PIO_mode = 0; 465 mode[1] = drvp[1].PIO_mode; 466 } else if (drvp[1].PIO_mode < 2) { 467 mode[1] = drvp[1].PIO_mode = 0; 468 mode[0] = drvp[0].PIO_mode; 469 } else { 470 mode[0] = mode[1] = 471 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 472 drvp[0].PIO_mode = mode[0]; 473 drvp[1].PIO_mode = mode[1]; 474 } 475 ok: /* The modes are setup */ 476 for (drive = 0; drive < 2; drive++) { 477 if (drvp[drive].drive_flags & DRIVE_DMA) { 478 idetim |= piix_setup_idetim_timings( 479 mode[drive], 1, chp->ch_channel); 480 goto end; 481 } 482 } 483 /* If we are there, none of the drives are DMA */ 484 if (mode[0] >= 2) 485 idetim |= piix_setup_idetim_timings( 486 mode[0], 0, chp->ch_channel); 487 else 488 idetim |= piix_setup_idetim_timings( 489 mode[1], 0, chp->ch_channel); 490 end: /* 491 * timing mode is now set up in the controller. Enable 492 * it per-drive 493 */ 494 for (drive = 0; drive < 2; drive++) { 495 /* If no drive, skip */ 496 if ((drvp[drive].drive_flags & DRIVE) == 0) 497 continue; 498 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 499 if (drvp[drive].drive_flags & DRIVE_DMA) 500 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 501 } 502 if (idedma_ctl != 0) { 503 /* Add software bits in status register */ 504 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 505 idedma_ctl); 506 } 507 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 508 } 509 510 static void 511 piix3_4_setup_channel(struct ata_channel *chp) 512 { 513 struct ata_drive_datas *drvp; 514 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 515 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 516 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 517 struct wdc_softc *wdc = &sc->sc_wdcdev; 518 int drive, s; 519 int channel = chp->ch_channel; 520 521 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 522 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 523 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 524 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 525 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 526 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 527 PIIX_SIDETIM_RTC_MASK(channel)); 528 idedma_ctl = 0; 529 530 /* set up new idetim: Enable IDE registers decode */ 531 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 532 533 /* setup DMA if needed */ 534 pciide_channel_dma_setup(cp); 535 536 for (drive = 0; drive < 2; drive++) { 537 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 538 PIIX_UDMATIM_SET(0x3, channel, drive)); 539 drvp = &chp->ch_drive[drive]; 540 /* If no drive, skip */ 541 if ((drvp->drive_flags & DRIVE) == 0) 542 continue; 543 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 544 (drvp->drive_flags & DRIVE_UDMA) == 0)) 545 goto pio; 546 547 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 548 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 549 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 550 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 551 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 552 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 553 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 554 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 555 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 556 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 557 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 558 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 559 ideconf |= PIIX_CONFIG_PINGPONG; 560 } 561 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 562 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 563 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 564 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 565 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 566 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 567 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 568 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 569 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 570 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 571 /* setup Ultra/100 */ 572 if (drvp->UDMA_mode > 2 && 573 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 574 drvp->UDMA_mode = 2; 575 if (drvp->UDMA_mode > 4) { 576 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 577 } else { 578 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 579 if (drvp->UDMA_mode > 2) { 580 ideconf |= PIIX_CONFIG_UDMA66(channel, 581 drive); 582 } else { 583 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 584 drive); 585 } 586 } 587 } 588 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 589 /* setup Ultra/66 */ 590 if (drvp->UDMA_mode > 2 && 591 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 592 drvp->UDMA_mode = 2; 593 if (drvp->UDMA_mode > 2) 594 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 595 else 596 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 597 } 598 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 599 (drvp->drive_flags & DRIVE_UDMA)) { 600 /* use Ultra/DMA */ 601 s = splbio(); 602 drvp->drive_flags &= ~DRIVE_DMA; 603 splx(s); 604 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 605 udmareg |= PIIX_UDMATIM_SET( 606 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 607 } else { 608 /* use Multiword DMA */ 609 s = splbio(); 610 drvp->drive_flags &= ~DRIVE_UDMA; 611 splx(s); 612 if (drive == 0) { 613 idetim |= piix_setup_idetim_timings( 614 drvp->DMA_mode, 1, channel); 615 } else { 616 sidetim |= piix_setup_sidetim_timings( 617 drvp->DMA_mode, 1, channel); 618 idetim =PIIX_IDETIM_SET(idetim, 619 PIIX_IDETIM_SITRE, channel); 620 } 621 } 622 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 623 624 pio: /* use PIO mode */ 625 idetim |= piix_setup_idetim_drvs(drvp); 626 if (drive == 0) { 627 idetim |= piix_setup_idetim_timings( 628 drvp->PIO_mode, 0, channel); 629 } else { 630 sidetim |= piix_setup_sidetim_timings( 631 drvp->PIO_mode, 0, channel); 632 idetim =PIIX_IDETIM_SET(idetim, 633 PIIX_IDETIM_SITRE, channel); 634 } 635 } 636 if (idedma_ctl != 0) { 637 /* Add software bits in status register */ 638 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 639 idedma_ctl); 640 } 641 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 642 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 643 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 644 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 645 } 646 647 648 /* setup ISP and RTC fields, based on mode */ 649 static u_int32_t 650 piix_setup_idetim_timings(mode, dma, channel) 651 u_int8_t mode; 652 u_int8_t dma; 653 u_int8_t channel; 654 { 655 656 if (dma) 657 return PIIX_IDETIM_SET(0, 658 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 659 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 660 channel); 661 else 662 return PIIX_IDETIM_SET(0, 663 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 664 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 665 channel); 666 } 667 668 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 669 static u_int32_t 670 piix_setup_idetim_drvs(drvp) 671 struct ata_drive_datas *drvp; 672 { 673 u_int32_t ret = 0; 674 struct ata_channel *chp = drvp->chnl_softc; 675 u_int8_t channel = chp->ch_channel; 676 u_int8_t drive = drvp->drive; 677 678 /* 679 * If drive is using UDMA, timings setups are independant 680 * So just check DMA and PIO here. 681 */ 682 if (drvp->drive_flags & DRIVE_DMA) { 683 /* if mode = DMA mode 0, use compatible timings */ 684 if ((drvp->drive_flags & DRIVE_DMA) && 685 drvp->DMA_mode == 0) { 686 drvp->PIO_mode = 0; 687 return ret; 688 } 689 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 690 /* 691 * PIO and DMA timings are the same, use fast timings for PIO 692 * too, else use compat timings. 693 */ 694 if ((piix_isp_pio[drvp->PIO_mode] != 695 piix_isp_dma[drvp->DMA_mode]) || 696 (piix_rtc_pio[drvp->PIO_mode] != 697 piix_rtc_dma[drvp->DMA_mode])) 698 drvp->PIO_mode = 0; 699 /* if PIO mode <= 2, use compat timings for PIO */ 700 if (drvp->PIO_mode <= 2) { 701 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 702 channel); 703 return ret; 704 } 705 } 706 707 /* 708 * Now setup PIO modes. If mode < 2, use compat timings. 709 * Else enable fast timings. Enable IORDY and prefetch/post 710 * if PIO mode >= 3. 711 */ 712 713 if (drvp->PIO_mode < 2) 714 return ret; 715 716 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 717 if (drvp->PIO_mode >= 3) { 718 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 719 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 720 } 721 return ret; 722 } 723 724 /* setup values in SIDETIM registers, based on mode */ 725 static u_int32_t 726 piix_setup_sidetim_timings(mode, dma, channel) 727 u_int8_t mode; 728 u_int8_t dma; 729 u_int8_t channel; 730 { 731 if (dma) 732 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 733 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 734 else 735 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 736 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 737 } 738 739 static void 740 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 741 { 742 struct pciide_channel *cp; 743 bus_size_t cmdsize, ctlsize; 744 pcireg_t interface, cmdsts; 745 int channel; 746 747 if (pciide_chipen(sc, pa) == 0) 748 return; 749 750 aprint_normal("%s: bus-master DMA support present", 751 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 752 pciide_mapreg_dma(sc, pa); 753 aprint_normal("\n"); 754 755 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 756 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 757 if (sc->sc_dma_ok) { 758 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 759 sc->sc_wdcdev.irqack = pciide_irqack; 760 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 761 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 762 } 763 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 764 765 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 766 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 767 768 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 769 cmdsts &= ~0x0400; 770 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 771 772 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 773 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 774 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 775 776 interface = PCI_INTERFACE(pa->pa_class); 777 778 wdc_allocate_regs(&sc->sc_wdcdev); 779 780 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 781 channel++) { 782 cp = &sc->pciide_channels[channel]; 783 if (pciide_chansetup(sc, channel, interface) == 0) 784 continue; 785 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 786 pciide_pci_intr); 787 } 788 } 789
Indexes created Fri Sep 26 20:09:58 GMT 2025