piixide.c revision 1.25.4.1
1 /* $NetBSD: piixide.c,v 1.25.4.1 2006/09/09 02:52:19 rpaulo Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.25.4.1 2006/09/09 02:52:19 rpaulo Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 52 static void piixide_powerhook(int, void *); 53 static int piixide_match(struct device *, struct cfdata *, void *); 54 static void piixide_attach(struct device *, struct device *, void *); 55 56 static const struct pciide_product_desc pciide_intel_products[] = { 57 { PCI_PRODUCT_INTEL_82092AA, 58 0, 59 "Intel 82092AA IDE controller", 60 default_chip_map, 61 }, 62 { PCI_PRODUCT_INTEL_82371FB_IDE, 63 0, 64 "Intel 82371FB IDE controller (PIIX)", 65 piix_chip_map, 66 }, 67 { PCI_PRODUCT_INTEL_82371SB_IDE, 68 0, 69 "Intel 82371SB IDE Interface (PIIX3)", 70 piix_chip_map, 71 }, 72 { PCI_PRODUCT_INTEL_82371AB_IDE, 73 0, 74 "Intel 82371AB IDE controller (PIIX4)", 75 piix_chip_map, 76 }, 77 { PCI_PRODUCT_INTEL_82440MX_IDE, 78 0, 79 "Intel 82440MX IDE controller", 80 piix_chip_map 81 }, 82 { PCI_PRODUCT_INTEL_82801AA_IDE, 83 0, 84 "Intel 82801AA IDE Controller (ICH)", 85 piix_chip_map, 86 }, 87 { PCI_PRODUCT_INTEL_82801AB_IDE, 88 0, 89 "Intel 82801AB IDE Controller (ICH0)", 90 piix_chip_map, 91 }, 92 { PCI_PRODUCT_INTEL_82801BA_IDE, 93 0, 94 "Intel 82801BA IDE Controller (ICH2)", 95 piix_chip_map, 96 }, 97 { PCI_PRODUCT_INTEL_82801BAM_IDE, 98 0, 99 "Intel 82801BAM IDE Controller (ICH2-M)", 100 piix_chip_map, 101 }, 102 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 103 0, 104 "Intel 82801CA IDE Controller (ICH3)", 105 piix_chip_map, 106 }, 107 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 108 0, 109 "Intel 82801CA IDE Controller (ICH3)", 110 piix_chip_map, 111 }, 112 { PCI_PRODUCT_INTEL_82801DB_IDE, 113 0, 114 "Intel 82801DB IDE Controller (ICH4)", 115 piix_chip_map, 116 }, 117 { PCI_PRODUCT_INTEL_82801DBM_IDE, 118 0, 119 "Intel 82801DBM IDE Controller (ICH4-M)", 120 piix_chip_map, 121 }, 122 { PCI_PRODUCT_INTEL_82801EB_IDE, 123 0, 124 "Intel 82801EB IDE Controller (ICH5)", 125 piix_chip_map, 126 }, 127 { PCI_PRODUCT_INTEL_82801EB_SATA, 128 0, 129 "Intel 82801EB Serial ATA Controller", 130 piixsata_chip_map, 131 }, 132 { PCI_PRODUCT_INTEL_82801ER_SATA, 133 0, 134 "Intel 82801ER Serial ATA/Raid Controller", 135 piixsata_chip_map, 136 }, 137 { PCI_PRODUCT_INTEL_6300ESB_IDE, 138 0, 139 "Intel 6300ESB IDE Controller (ICH5)", 140 piix_chip_map, 141 }, 142 { PCI_PRODUCT_INTEL_6300ESB_SATA, 143 0, 144 "Intel 6300ESB Serial ATA Controller", 145 piixsata_chip_map, 146 }, 147 { PCI_PRODUCT_INTEL_6300ESB_RAID, 148 0, 149 "Intel 6300ESB Serial ATA/RAID Controller", 150 piixsata_chip_map, 151 }, 152 { PCI_PRODUCT_INTEL_82801FB_IDE, 153 0, 154 "Intel 82801FB IDE Controller (ICH6)", 155 piix_chip_map, 156 }, 157 { PCI_PRODUCT_INTEL_82801FB_SATA, 158 0, 159 "Intel 82801FB Serial ATA/Raid Controller", 160 piixsata_chip_map, 161 }, 162 { PCI_PRODUCT_INTEL_82801FR_SATA, 163 0, 164 "Intel 82801FR Serial ATA/Raid Controller", 165 piixsata_chip_map, 166 }, 167 { PCI_PRODUCT_INTEL_82801FBM_SATA, 168 0, 169 "Intel 82801FBM Serial ATA Controller (ICH6)", 170 piixsata_chip_map, 171 }, 172 { PCI_PRODUCT_INTEL_82801G_IDE, 173 0, 174 "Intel 82801GB/GR IDE Controller (ICH7)", 175 piix_chip_map, 176 }, 177 { PCI_PRODUCT_INTEL_82801G_SATA, 178 0, 179 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 180 piixsata_chip_map, 181 }, 182 { PCI_PRODUCT_INTEL_82801GBM_SATA, 183 0, 184 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 185 piixsata_chip_map, 186 }, 187 { PCI_PRODUCT_INTEL_82801H_SATA_1, 188 0, 189 "Intel 82801H Serial ATA Controller (ICH8)", 190 piixsata_chip_map, 191 }, 192 { PCI_PRODUCT_INTEL_82801H_SATA_AHCI6, 193 0, 194 "Intel 82801H AHCI Controller (ICH8)", 195 piixsata_chip_map, 196 }, 197 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 198 0, 199 "Intel 82801H Serial ATA RAID Controller (ICH8)", 200 piixsata_chip_map, 201 }, 202 { PCI_PRODUCT_INTEL_82801H_SATA_AHCI4, 203 0, 204 "Intel 82801H Serial ATA Controller (ICH8)", 205 piixsata_chip_map, 206 }, 207 { PCI_PRODUCT_INTEL_82801H_SATA_2, 208 0, 209 "Intel 82801H Serial ATA Controller (ICH8)", 210 piixsata_chip_map, 211 }, 212 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 213 0, 214 "Intel 82801HBM Serial ATA Controller (ICH8M)", 215 piixsata_chip_map, 216 }, 217 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 218 0, 219 "Intel 82801HBM Serial ATA Controller (ICH8M)", 220 piixsata_chip_map, 221 }, 222 { PCI_PRODUCT_INTEL_63XXESB_IDE, 223 0, 224 "Intel 631xESB/632xESB IDE Controller", 225 piix_chip_map, 226 }, 227 { PCI_PRODUCT_INTEL_63XXESB_SATA, 228 0, 229 "Intel 631xESB/632xESB Serial ATA Controller", 230 piixsata_chip_map, 231 }, 232 { 0, 233 0, 234 NULL, 235 NULL 236 } 237 }; 238 239 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 240 piixide_match, piixide_attach, NULL, NULL); 241 242 static int 243 piixide_match(struct device *parent, struct cfdata *match, void *aux) 244 { 245 struct pci_attach_args *pa = aux; 246 247 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 248 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 249 return (2); 250 } 251 return (0); 252 } 253 254 static void 255 piixide_attach(struct device *parent, struct device *self, void *aux) 256 { 257 struct pci_attach_args *pa = aux; 258 struct pciide_softc *sc = (struct pciide_softc *)self; 259 260 pciide_common_attach(sc, pa, 261 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 262 263 /* Setup our powerhook */ 264 sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc); 265 if (sc->sc_powerhook == NULL) 266 printf("%s: WARNING: unable to establish PCI power hook\n", 267 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 268 } 269 270 static void 271 piixide_powerhook(int why, void *hdl) 272 { 273 struct pciide_softc *sc = (struct pciide_softc *)hdl; 274 275 switch (why) { 276 case PWR_SUSPEND: 277 case PWR_STANDBY: 278 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 279 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 280 PIIX_IDETIM); 281 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 282 PIIX_UDMATIM); 283 break; 284 case PWR_RESUME: 285 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 286 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 287 sc->sc_idetim); 288 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 289 sc->sc_udmatim); 290 break; 291 case PWR_SOFTSUSPEND: 292 case PWR_SOFTSTANDBY: 293 case PWR_SOFTRESUME: 294 break; 295 } 296 297 return; 298 } 299 300 static void 301 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 302 { 303 struct pciide_channel *cp; 304 int channel; 305 u_int32_t idetim; 306 bus_size_t cmdsize, ctlsize; 307 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 308 309 if (pciide_chipen(sc, pa) == 0) 310 return; 311 312 aprint_normal("%s: bus-master DMA support present", 313 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 314 pciide_mapreg_dma(sc, pa); 315 aprint_normal("\n"); 316 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 317 if (sc->sc_dma_ok) { 318 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 319 sc->sc_wdcdev.irqack = pciide_irqack; 320 switch(sc->sc_pp->ide_product) { 321 case PCI_PRODUCT_INTEL_82371AB_IDE: 322 case PCI_PRODUCT_INTEL_82440MX_IDE: 323 case PCI_PRODUCT_INTEL_82801AA_IDE: 324 case PCI_PRODUCT_INTEL_82801AB_IDE: 325 case PCI_PRODUCT_INTEL_82801BA_IDE: 326 case PCI_PRODUCT_INTEL_82801BAM_IDE: 327 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 328 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 329 case PCI_PRODUCT_INTEL_82801DB_IDE: 330 case PCI_PRODUCT_INTEL_82801DBM_IDE: 331 case PCI_PRODUCT_INTEL_82801EB_IDE: 332 case PCI_PRODUCT_INTEL_6300ESB_IDE: 333 case PCI_PRODUCT_INTEL_82801FB_IDE: 334 case PCI_PRODUCT_INTEL_82801G_IDE: 335 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 336 } 337 } 338 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 339 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 340 switch(sc->sc_pp->ide_product) { 341 case PCI_PRODUCT_INTEL_82801AA_IDE: 342 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 343 break; 344 case PCI_PRODUCT_INTEL_82801BA_IDE: 345 case PCI_PRODUCT_INTEL_82801BAM_IDE: 346 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 347 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 348 case PCI_PRODUCT_INTEL_82801DB_IDE: 349 case PCI_PRODUCT_INTEL_82801DBM_IDE: 350 case PCI_PRODUCT_INTEL_82801EB_IDE: 351 case PCI_PRODUCT_INTEL_6300ESB_IDE: 352 case PCI_PRODUCT_INTEL_82801FB_IDE: 353 case PCI_PRODUCT_INTEL_82801G_IDE: 354 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 355 break; 356 default: 357 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 358 } 359 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 360 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 361 else 362 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 363 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 364 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 365 366 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 367 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 368 DEBUG_PROBE); 369 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 370 ATADEBUG_PRINT((", sidetim=0x%x", 371 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 372 DEBUG_PROBE); 373 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 374 ATADEBUG_PRINT((", udamreg 0x%x", 375 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 376 DEBUG_PROBE); 377 } 378 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 379 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 380 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 381 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 382 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 383 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 384 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 385 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 386 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 387 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 388 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 389 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 390 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 391 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 392 DEBUG_PROBE); 393 } 394 395 } 396 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 397 398 wdc_allocate_regs(&sc->sc_wdcdev); 399 400 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 401 channel++) { 402 cp = &sc->pciide_channels[channel]; 403 if (pciide_chansetup(sc, channel, interface) == 0) 404 continue; 405 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 406 if ((PIIX_IDETIM_READ(idetim, channel) & 407 PIIX_IDETIM_IDE) == 0) { 408 #if 1 409 aprint_normal("%s: %s channel ignored (disabled)\n", 410 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 411 cp->ata_channel.ch_flags |= ATACH_DISABLED; 412 continue; 413 #else 414 pcireg_t interface; 415 416 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 417 channel); 418 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 419 idetim); 420 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 421 sc->sc_tag, PCI_CLASS_REG)); 422 aprint_normal("channel %d idetim=%08x interface=%02x\n", 423 channel, idetim, interface); 424 #endif 425 } 426 pciide_mapchan(pa, cp, interface, 427 &cmdsize, &ctlsize, pciide_pci_intr); 428 } 429 430 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 431 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 432 DEBUG_PROBE); 433 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 434 ATADEBUG_PRINT((", sidetim=0x%x", 435 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 436 DEBUG_PROBE); 437 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 438 ATADEBUG_PRINT((", udamreg 0x%x", 439 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 440 DEBUG_PROBE); 441 } 442 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 443 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 444 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 445 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 446 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 447 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 448 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 449 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 450 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 451 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 452 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 453 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 454 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 455 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 456 DEBUG_PROBE); 457 } 458 } 459 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 460 } 461 462 static void 463 piix_setup_channel(struct ata_channel *chp) 464 { 465 u_int8_t mode[2], drive; 466 u_int32_t oidetim, idetim, idedma_ctl; 467 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 468 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 469 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 470 471 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 472 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 473 idedma_ctl = 0; 474 475 /* set up new idetim: Enable IDE registers decode */ 476 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 477 chp->ch_channel); 478 479 /* setup DMA */ 480 pciide_channel_dma_setup(cp); 481 482 /* 483 * Here we have to mess up with drives mode: PIIX can't have 484 * different timings for master and slave drives. 485 * We need to find the best combination. 486 */ 487 488 /* If both drives supports DMA, take the lower mode */ 489 if ((drvp[0].drive_flags & DRIVE_DMA) && 490 (drvp[1].drive_flags & DRIVE_DMA)) { 491 mode[0] = mode[1] = 492 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 493 drvp[0].DMA_mode = mode[0]; 494 drvp[1].DMA_mode = mode[1]; 495 goto ok; 496 } 497 /* 498 * If only one drive supports DMA, use its mode, and 499 * put the other one in PIO mode 0 if mode not compatible 500 */ 501 if (drvp[0].drive_flags & DRIVE_DMA) { 502 mode[0] = drvp[0].DMA_mode; 503 mode[1] = drvp[1].PIO_mode; 504 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 505 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 506 mode[1] = drvp[1].PIO_mode = 0; 507 goto ok; 508 } 509 if (drvp[1].drive_flags & DRIVE_DMA) { 510 mode[1] = drvp[1].DMA_mode; 511 mode[0] = drvp[0].PIO_mode; 512 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 513 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 514 mode[0] = drvp[0].PIO_mode = 0; 515 goto ok; 516 } 517 /* 518 * If both drives are not DMA, takes the lower mode, unless 519 * one of them is PIO mode < 2 520 */ 521 if (drvp[0].PIO_mode < 2) { 522 mode[0] = drvp[0].PIO_mode = 0; 523 mode[1] = drvp[1].PIO_mode; 524 } else if (drvp[1].PIO_mode < 2) { 525 mode[1] = drvp[1].PIO_mode = 0; 526 mode[0] = drvp[0].PIO_mode; 527 } else { 528 mode[0] = mode[1] = 529 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 530 drvp[0].PIO_mode = mode[0]; 531 drvp[1].PIO_mode = mode[1]; 532 } 533 ok: /* The modes are setup */ 534 for (drive = 0; drive < 2; drive++) { 535 if (drvp[drive].drive_flags & DRIVE_DMA) { 536 idetim |= piix_setup_idetim_timings( 537 mode[drive], 1, chp->ch_channel); 538 goto end; 539 } 540 } 541 /* If we are there, none of the drives are DMA */ 542 if (mode[0] >= 2) 543 idetim |= piix_setup_idetim_timings( 544 mode[0], 0, chp->ch_channel); 545 else 546 idetim |= piix_setup_idetim_timings( 547 mode[1], 0, chp->ch_channel); 548 end: /* 549 * timing mode is now set up in the controller. Enable 550 * it per-drive 551 */ 552 for (drive = 0; drive < 2; drive++) { 553 /* If no drive, skip */ 554 if ((drvp[drive].drive_flags & DRIVE) == 0) 555 continue; 556 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 557 if (drvp[drive].drive_flags & DRIVE_DMA) 558 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 559 } 560 if (idedma_ctl != 0) { 561 /* Add software bits in status register */ 562 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 563 idedma_ctl); 564 } 565 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 566 } 567 568 static void 569 piix3_4_setup_channel(struct ata_channel *chp) 570 { 571 struct ata_drive_datas *drvp; 572 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 573 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 574 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 575 struct wdc_softc *wdc = &sc->sc_wdcdev; 576 int drive, s; 577 int channel = chp->ch_channel; 578 579 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 580 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 581 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 582 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 583 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 584 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 585 PIIX_SIDETIM_RTC_MASK(channel)); 586 idedma_ctl = 0; 587 588 /* set up new idetim: Enable IDE registers decode */ 589 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 590 591 /* setup DMA if needed */ 592 pciide_channel_dma_setup(cp); 593 594 for (drive = 0; drive < 2; drive++) { 595 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 596 PIIX_UDMATIM_SET(0x3, channel, drive)); 597 drvp = &chp->ch_drive[drive]; 598 /* If no drive, skip */ 599 if ((drvp->drive_flags & DRIVE) == 0) 600 continue; 601 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 602 (drvp->drive_flags & DRIVE_UDMA) == 0)) 603 goto pio; 604 605 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 606 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 607 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 608 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 609 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 610 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 611 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 612 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 613 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 614 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 615 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 616 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 617 ideconf |= PIIX_CONFIG_PINGPONG; 618 } 619 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 620 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 621 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 622 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 623 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 624 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 625 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 626 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 629 /* setup Ultra/100 */ 630 if (drvp->UDMA_mode > 2 && 631 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 632 drvp->UDMA_mode = 2; 633 if (drvp->UDMA_mode > 4) { 634 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 635 } else { 636 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 637 if (drvp->UDMA_mode > 2) { 638 ideconf |= PIIX_CONFIG_UDMA66(channel, 639 drive); 640 } else { 641 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 642 drive); 643 } 644 } 645 } 646 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 647 /* setup Ultra/66 */ 648 if (drvp->UDMA_mode > 2 && 649 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 650 drvp->UDMA_mode = 2; 651 if (drvp->UDMA_mode > 2) 652 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 653 else 654 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 655 } 656 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 657 (drvp->drive_flags & DRIVE_UDMA)) { 658 /* use Ultra/DMA */ 659 s = splbio(); 660 drvp->drive_flags &= ~DRIVE_DMA; 661 splx(s); 662 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 663 udmareg |= PIIX_UDMATIM_SET( 664 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 665 } else { 666 /* use Multiword DMA */ 667 s = splbio(); 668 drvp->drive_flags &= ~DRIVE_UDMA; 669 splx(s); 670 if (drive == 0) { 671 idetim |= piix_setup_idetim_timings( 672 drvp->DMA_mode, 1, channel); 673 } else { 674 sidetim |= piix_setup_sidetim_timings( 675 drvp->DMA_mode, 1, channel); 676 idetim =PIIX_IDETIM_SET(idetim, 677 PIIX_IDETIM_SITRE, channel); 678 } 679 } 680 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 681 682 pio: /* use PIO mode */ 683 idetim |= piix_setup_idetim_drvs(drvp); 684 if (drive == 0) { 685 idetim |= piix_setup_idetim_timings( 686 drvp->PIO_mode, 0, channel); 687 } else { 688 sidetim |= piix_setup_sidetim_timings( 689 drvp->PIO_mode, 0, channel); 690 idetim =PIIX_IDETIM_SET(idetim, 691 PIIX_IDETIM_SITRE, channel); 692 } 693 } 694 if (idedma_ctl != 0) { 695 /* Add software bits in status register */ 696 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 697 idedma_ctl); 698 } 699 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 700 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 701 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 702 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 703 } 704 705 706 /* setup ISP and RTC fields, based on mode */ 707 static u_int32_t 708 piix_setup_idetim_timings(mode, dma, channel) 709 u_int8_t mode; 710 u_int8_t dma; 711 u_int8_t channel; 712 { 713 714 if (dma) 715 return PIIX_IDETIM_SET(0, 716 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 717 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 718 channel); 719 else 720 return PIIX_IDETIM_SET(0, 721 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 722 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 723 channel); 724 } 725 726 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 727 static u_int32_t 728 piix_setup_idetim_drvs(drvp) 729 struct ata_drive_datas *drvp; 730 { 731 u_int32_t ret = 0; 732 struct ata_channel *chp = drvp->chnl_softc; 733 u_int8_t channel = chp->ch_channel; 734 u_int8_t drive = drvp->drive; 735 736 /* 737 * If drive is using UDMA, timings setups are independant 738 * So just check DMA and PIO here. 739 */ 740 if (drvp->drive_flags & DRIVE_DMA) { 741 /* if mode = DMA mode 0, use compatible timings */ 742 if ((drvp->drive_flags & DRIVE_DMA) && 743 drvp->DMA_mode == 0) { 744 drvp->PIO_mode = 0; 745 return ret; 746 } 747 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 748 /* 749 * PIO and DMA timings are the same, use fast timings for PIO 750 * too, else use compat timings. 751 */ 752 if ((piix_isp_pio[drvp->PIO_mode] != 753 piix_isp_dma[drvp->DMA_mode]) || 754 (piix_rtc_pio[drvp->PIO_mode] != 755 piix_rtc_dma[drvp->DMA_mode])) 756 drvp->PIO_mode = 0; 757 /* if PIO mode <= 2, use compat timings for PIO */ 758 if (drvp->PIO_mode <= 2) { 759 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 760 channel); 761 return ret; 762 } 763 } 764 765 /* 766 * Now setup PIO modes. If mode < 2, use compat timings. 767 * Else enable fast timings. Enable IORDY and prefetch/post 768 * if PIO mode >= 3. 769 */ 770 771 if (drvp->PIO_mode < 2) 772 return ret; 773 774 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 775 if (drvp->PIO_mode >= 3) { 776 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 777 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 778 } 779 return ret; 780 } 781 782 /* setup values in SIDETIM registers, based on mode */ 783 static u_int32_t 784 piix_setup_sidetim_timings(mode, dma, channel) 785 u_int8_t mode; 786 u_int8_t dma; 787 u_int8_t channel; 788 { 789 if (dma) 790 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 791 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 792 else 793 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 794 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 795 } 796 797 static void 798 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 799 { 800 struct pciide_channel *cp; 801 bus_size_t cmdsize, ctlsize; 802 pcireg_t interface, cmdsts; 803 int channel, ich = 0; 804 uint8_t reg; 805 806 if (pciide_chipen(sc, pa) == 0) 807 return; 808 809 aprint_normal("%s: bus-master DMA support present", 810 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 811 pciide_mapreg_dma(sc, pa); 812 aprint_normal("\n"); 813 814 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 815 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 816 if (sc->sc_dma_ok) { 817 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 818 sc->sc_wdcdev.irqack = pciide_irqack; 819 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 820 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 821 } 822 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 823 824 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 825 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 826 827 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 828 cmdsts &= ~0x0400; 829 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 830 831 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 832 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 833 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 834 835 interface = PCI_INTERFACE(pa->pa_class); 836 837 switch (sc->sc_pp->ide_product) { 838 case PCI_PRODUCT_INTEL_6300ESB_SATA: 839 case PCI_PRODUCT_INTEL_6300ESB_RAID: 840 case PCI_PRODUCT_INTEL_63XXESB_SATA: 841 case PCI_PRODUCT_INTEL_82801EB_SATA: 842 case PCI_PRODUCT_INTEL_82801ER_SATA: 843 ich = 5; 844 break; 845 case PCI_PRODUCT_INTEL_82801FB_SATA: 846 case PCI_PRODUCT_INTEL_82801FR_SATA: 847 case PCI_PRODUCT_INTEL_82801FBM_SATA: 848 ich = 6; 849 break; 850 case PCI_PRODUCT_INTEL_82801G_SATA: 851 case PCI_PRODUCT_INTEL_82801G_SATA_AHCI: 852 case PCI_PRODUCT_INTEL_82801G_SATA_RAID: 853 case PCI_PRODUCT_INTEL_82801GBM_SATA: 854 case PCI_PRODUCT_INTEL_82801GBM_AHCI: 855 case PCI_PRODUCT_INTEL_82801GHM_RAID: 856 ich = 7; 857 break; 858 case PCI_PRODUCT_INTEL_82801H_SATA_1: 859 case PCI_PRODUCT_INTEL_82801H_SATA_AHCI6: 860 case PCI_PRODUCT_INTEL_82801H_SATA_RAID: 861 case PCI_PRODUCT_INTEL_82801H_SATA_AHCI4: 862 case PCI_PRODUCT_INTEL_82801H_SATA_2: 863 case PCI_PRODUCT_INTEL_82801HBM_SATA_1: 864 case PCI_PRODUCT_INTEL_82801HBM_SATA_2: 865 ich = 8; 866 break; 867 } 868 869 /* 870 * Put the SATA portion of controllers that don't operate in combined 871 * mode into native PCI modes so the maximum number of devices can be 872 * used. Intel calls this "enhanced mode". 873 */ 874 875 if (ich == 5) { 876 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP); 877 if ((reg & ICH5_SATA_MAP_COMBINED) == 0) { 878 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 879 ICH5_SATA_PI); 880 reg |= ICH5_SATA_PI_PRI_NATIVE | 881 ICH5_SATA_PI_SEC_NATIVE; 882 pciide_pci_write(pa->pa_pc, pa->pa_tag, 883 ICH5_SATA_PI, reg); 884 interface |= PCIIDE_INTERFACE_PCI(0) | 885 PCIIDE_INTERFACE_PCI(1); 886 } 887 } else { 888 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP) & 889 ICH6_SATA_MAP_CMB_MASK; 890 if (reg != ICH6_SATA_MAP_CMB_PRI && 891 reg != ICH6_SATA_MAP_CMB_SEC) { 892 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 893 ICH5_SATA_PI); 894 reg |= ICH5_SATA_PI_PRI_NATIVE | 895 ICH5_SATA_PI_SEC_NATIVE; 896 897 pciide_pci_write(pa->pa_pc, pa->pa_tag, 898 ICH5_SATA_PI, reg); 899 interface |= PCIIDE_INTERFACE_PCI(0) | 900 PCIIDE_INTERFACE_PCI(1); 901 902 /* 903 * Ask for SATA IDE Mode, we don't need to do this 904 * for the combined mode case as combined mode is 905 * only allowed in IDE Mode. 906 */ 907 908 if (ich >= 7) { 909 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, 910 ICH5_SATA_MAP) & ~ICH7_SATA_MAP_SMS_MASK; 911 pciide_pci_write(pa->pa_pc, pa->pa_tag, 912 ICH5_SATA_MAP, reg); 913 } 914 } 915 } 916 917 wdc_allocate_regs(&sc->sc_wdcdev); 918 919 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 920 channel++) { 921 cp = &sc->pciide_channels[channel]; 922 if (pciide_chansetup(sc, channel, interface) == 0) 923 continue; 924 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 925 pciide_pci_intr); 926 } 927 } 928
Indexes created Fri Oct 17 00:09:41 GMT 2025