piixide.c revision 1.25.8.3
1 /* $NetBSD: piixide.c,v 1.25.8.3 2006/08/11 15:44:26 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.25.8.3 2006/08/11 15:44:26 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 52 static void piixide_powerhook(int, void *); 53 static int piixide_match(struct device *, struct cfdata *, void *); 54 static void piixide_attach(struct device *, struct device *, void *); 55 56 static const struct pciide_product_desc pciide_intel_products[] = { 57 { PCI_PRODUCT_INTEL_82092AA, 58 0, 59 "Intel 82092AA IDE controller", 60 default_chip_map, 61 }, 62 { PCI_PRODUCT_INTEL_82371FB_IDE, 63 0, 64 "Intel 82371FB IDE controller (PIIX)", 65 piix_chip_map, 66 }, 67 { PCI_PRODUCT_INTEL_82371SB_IDE, 68 0, 69 "Intel 82371SB IDE Interface (PIIX3)", 70 piix_chip_map, 71 }, 72 { PCI_PRODUCT_INTEL_82371AB_IDE, 73 0, 74 "Intel 82371AB IDE controller (PIIX4)", 75 piix_chip_map, 76 }, 77 { PCI_PRODUCT_INTEL_82440MX_IDE, 78 0, 79 "Intel 82440MX IDE controller", 80 piix_chip_map 81 }, 82 { PCI_PRODUCT_INTEL_82801AA_IDE, 83 0, 84 "Intel 82801AA IDE Controller (ICH)", 85 piix_chip_map, 86 }, 87 { PCI_PRODUCT_INTEL_82801AB_IDE, 88 0, 89 "Intel 82801AB IDE Controller (ICH0)", 90 piix_chip_map, 91 }, 92 { PCI_PRODUCT_INTEL_82801BA_IDE, 93 0, 94 "Intel 82801BA IDE Controller (ICH2)", 95 piix_chip_map, 96 }, 97 { PCI_PRODUCT_INTEL_82801BAM_IDE, 98 0, 99 "Intel 82801BAM IDE Controller (ICH2-M)", 100 piix_chip_map, 101 }, 102 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 103 0, 104 "Intel 82801CA IDE Controller (ICH3)", 105 piix_chip_map, 106 }, 107 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 108 0, 109 "Intel 82801CA IDE Controller (ICH3)", 110 piix_chip_map, 111 }, 112 { PCI_PRODUCT_INTEL_82801DB_IDE, 113 0, 114 "Intel 82801DB IDE Controller (ICH4)", 115 piix_chip_map, 116 }, 117 { PCI_PRODUCT_INTEL_82801DBM_IDE, 118 0, 119 "Intel 82801DBM IDE Controller (ICH4-M)", 120 piix_chip_map, 121 }, 122 { PCI_PRODUCT_INTEL_82801EB_IDE, 123 0, 124 "Intel 82801EB IDE Controller (ICH5)", 125 piix_chip_map, 126 }, 127 { PCI_PRODUCT_INTEL_82801EB_SATA, 128 0, 129 "Intel 82801EB Serial ATA Controller", 130 piixsata_chip_map, 131 }, 132 { PCI_PRODUCT_INTEL_82801ER_SATA, 133 0, 134 "Intel 82801ER Serial ATA/Raid Controller", 135 piixsata_chip_map, 136 }, 137 { PCI_PRODUCT_INTEL_6300ESB_IDE, 138 0, 139 "Intel 6300ESB IDE Controller (ICH5)", 140 piix_chip_map, 141 }, 142 { PCI_PRODUCT_INTEL_6300ESB_SATA, 143 0, 144 "Intel 6300ESB Serial ATA Controller", 145 piixsata_chip_map, 146 }, 147 { PCI_PRODUCT_INTEL_6300ESB_RAID, 148 0, 149 "Intel 6300ESB Serial ATA/RAID Controller", 150 piixsata_chip_map, 151 }, 152 { PCI_PRODUCT_INTEL_82801FB_IDE, 153 0, 154 "Intel 82801FB IDE Controller (ICH6)", 155 piix_chip_map, 156 }, 157 { PCI_PRODUCT_INTEL_82801FB_SATA, 158 0, 159 "Intel 82801FB Serial ATA/Raid Controller", 160 piixsata_chip_map, 161 }, 162 { PCI_PRODUCT_INTEL_82801FR_SATA, 163 0, 164 "Intel 82801FR Serial ATA/Raid Controller", 165 piixsata_chip_map, 166 }, 167 { PCI_PRODUCT_INTEL_82801FBM_SATA, 168 0, 169 "Intel 82801FBM Serial ATA Controller (ICH6)", 170 piixsata_chip_map, 171 }, 172 { PCI_PRODUCT_INTEL_82801G_IDE, 173 0, 174 "Intel 82801GB/GR IDE Controller (ICH7)", 175 piix_chip_map, 176 }, 177 { PCI_PRODUCT_INTEL_82801G_SATA, 178 0, 179 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 180 piixsata_chip_map, 181 }, 182 { PCI_PRODUCT_INTEL_82801GBM_SATA, 183 0, 184 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 185 piixsata_chip_map, 186 }, 187 { PCI_PRODUCT_INTEL_63XXESB_IDE, 188 0, 189 "Intel 631xESB/632xESB IDE Controller", 190 piix_chip_map, 191 }, 192 { PCI_PRODUCT_INTEL_63XXESB_SATA, 193 0, 194 "Intel 631xESB/632xESB Serial ATA Controller", 195 piixsata_chip_map, 196 }, 197 { 0, 198 0, 199 NULL, 200 NULL 201 } 202 }; 203 204 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 205 piixide_match, piixide_attach, NULL, NULL); 206 207 static int 208 piixide_match(struct device *parent, struct cfdata *match, void *aux) 209 { 210 struct pci_attach_args *pa = aux; 211 212 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 213 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 214 return (2); 215 } 216 return (0); 217 } 218 219 static void 220 piixide_attach(struct device *parent, struct device *self, void *aux) 221 { 222 struct pci_attach_args *pa = aux; 223 struct pciide_softc *sc = (struct pciide_softc *)self; 224 225 pciide_common_attach(sc, pa, 226 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 227 228 /* Setup our powerhook */ 229 sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc); 230 if (sc->sc_powerhook == NULL) 231 printf("%s: WARNING: unable to establish PCI power hook\n", 232 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 233 } 234 235 static void 236 piixide_powerhook(int why, void *hdl) 237 { 238 struct pciide_softc *sc = (struct pciide_softc *)hdl; 239 240 switch (why) { 241 case PWR_SUSPEND: 242 case PWR_STANDBY: 243 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 244 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 245 PIIX_IDETIM); 246 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 247 PIIX_UDMATIM); 248 break; 249 case PWR_RESUME: 250 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 251 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 252 sc->sc_idetim); 253 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 254 sc->sc_udmatim); 255 break; 256 case PWR_SOFTSUSPEND: 257 case PWR_SOFTSTANDBY: 258 case PWR_SOFTRESUME: 259 break; 260 } 261 262 return; 263 } 264 265 static void 266 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 267 { 268 struct pciide_channel *cp; 269 int channel; 270 u_int32_t idetim; 271 bus_size_t cmdsize, ctlsize; 272 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 273 274 if (pciide_chipen(sc, pa) == 0) 275 return; 276 277 aprint_normal("%s: bus-master DMA support present", 278 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 279 pciide_mapreg_dma(sc, pa); 280 aprint_normal("\n"); 281 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 282 if (sc->sc_dma_ok) { 283 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 284 sc->sc_wdcdev.irqack = pciide_irqack; 285 switch(sc->sc_pp->ide_product) { 286 case PCI_PRODUCT_INTEL_82371AB_IDE: 287 case PCI_PRODUCT_INTEL_82440MX_IDE: 288 case PCI_PRODUCT_INTEL_82801AA_IDE: 289 case PCI_PRODUCT_INTEL_82801AB_IDE: 290 case PCI_PRODUCT_INTEL_82801BA_IDE: 291 case PCI_PRODUCT_INTEL_82801BAM_IDE: 292 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 293 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 294 case PCI_PRODUCT_INTEL_82801DB_IDE: 295 case PCI_PRODUCT_INTEL_82801DBM_IDE: 296 case PCI_PRODUCT_INTEL_82801EB_IDE: 297 case PCI_PRODUCT_INTEL_6300ESB_IDE: 298 case PCI_PRODUCT_INTEL_82801FB_IDE: 299 case PCI_PRODUCT_INTEL_82801G_IDE: 300 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 301 } 302 } 303 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 304 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 305 switch(sc->sc_pp->ide_product) { 306 case PCI_PRODUCT_INTEL_82801AA_IDE: 307 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 308 break; 309 case PCI_PRODUCT_INTEL_82801BA_IDE: 310 case PCI_PRODUCT_INTEL_82801BAM_IDE: 311 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 312 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 313 case PCI_PRODUCT_INTEL_82801DB_IDE: 314 case PCI_PRODUCT_INTEL_82801DBM_IDE: 315 case PCI_PRODUCT_INTEL_82801EB_IDE: 316 case PCI_PRODUCT_INTEL_6300ESB_IDE: 317 case PCI_PRODUCT_INTEL_82801FB_IDE: 318 case PCI_PRODUCT_INTEL_82801G_IDE: 319 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 320 break; 321 default: 322 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 323 } 324 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 325 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 326 else 327 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 328 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 329 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 330 331 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 332 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 333 DEBUG_PROBE); 334 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 335 ATADEBUG_PRINT((", sidetim=0x%x", 336 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 337 DEBUG_PROBE); 338 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 339 ATADEBUG_PRINT((", udamreg 0x%x", 340 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 341 DEBUG_PROBE); 342 } 343 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 344 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 345 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 346 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 347 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 348 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 349 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 350 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 351 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 352 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 353 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 354 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 355 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 356 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 357 DEBUG_PROBE); 358 } 359 360 } 361 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 362 363 wdc_allocate_regs(&sc->sc_wdcdev); 364 365 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 366 channel++) { 367 cp = &sc->pciide_channels[channel]; 368 if (pciide_chansetup(sc, channel, interface) == 0) 369 continue; 370 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 371 if ((PIIX_IDETIM_READ(idetim, channel) & 372 PIIX_IDETIM_IDE) == 0) { 373 #if 1 374 aprint_normal("%s: %s channel ignored (disabled)\n", 375 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 376 cp->ata_channel.ch_flags |= ATACH_DISABLED; 377 continue; 378 #else 379 pcireg_t interface; 380 381 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 382 channel); 383 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 384 idetim); 385 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 386 sc->sc_tag, PCI_CLASS_REG)); 387 aprint_normal("channel %d idetim=%08x interface=%02x\n", 388 channel, idetim, interface); 389 #endif 390 } 391 pciide_mapchan(pa, cp, interface, 392 &cmdsize, &ctlsize, pciide_pci_intr); 393 } 394 395 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 396 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 397 DEBUG_PROBE); 398 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 399 ATADEBUG_PRINT((", sidetim=0x%x", 400 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 401 DEBUG_PROBE); 402 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 403 ATADEBUG_PRINT((", udamreg 0x%x", 404 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 405 DEBUG_PROBE); 406 } 407 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 408 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 409 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 410 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 411 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 412 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 413 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 414 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 415 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 416 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 417 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 418 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 419 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 420 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 421 DEBUG_PROBE); 422 } 423 } 424 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 425 } 426 427 static void 428 piix_setup_channel(struct ata_channel *chp) 429 { 430 u_int8_t mode[2], drive; 431 u_int32_t oidetim, idetim, idedma_ctl; 432 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 433 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 434 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 435 436 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 437 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 438 idedma_ctl = 0; 439 440 /* set up new idetim: Enable IDE registers decode */ 441 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 442 chp->ch_channel); 443 444 /* setup DMA */ 445 pciide_channel_dma_setup(cp); 446 447 /* 448 * Here we have to mess up with drives mode: PIIX can't have 449 * different timings for master and slave drives. 450 * We need to find the best combination. 451 */ 452 453 /* If both drives supports DMA, take the lower mode */ 454 if ((drvp[0].drive_flags & DRIVE_DMA) && 455 (drvp[1].drive_flags & DRIVE_DMA)) { 456 mode[0] = mode[1] = 457 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 458 drvp[0].DMA_mode = mode[0]; 459 drvp[1].DMA_mode = mode[1]; 460 goto ok; 461 } 462 /* 463 * If only one drive supports DMA, use its mode, and 464 * put the other one in PIO mode 0 if mode not compatible 465 */ 466 if (drvp[0].drive_flags & DRIVE_DMA) { 467 mode[0] = drvp[0].DMA_mode; 468 mode[1] = drvp[1].PIO_mode; 469 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 470 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 471 mode[1] = drvp[1].PIO_mode = 0; 472 goto ok; 473 } 474 if (drvp[1].drive_flags & DRIVE_DMA) { 475 mode[1] = drvp[1].DMA_mode; 476 mode[0] = drvp[0].PIO_mode; 477 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 478 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 479 mode[0] = drvp[0].PIO_mode = 0; 480 goto ok; 481 } 482 /* 483 * If both drives are not DMA, takes the lower mode, unless 484 * one of them is PIO mode < 2 485 */ 486 if (drvp[0].PIO_mode < 2) { 487 mode[0] = drvp[0].PIO_mode = 0; 488 mode[1] = drvp[1].PIO_mode; 489 } else if (drvp[1].PIO_mode < 2) { 490 mode[1] = drvp[1].PIO_mode = 0; 491 mode[0] = drvp[0].PIO_mode; 492 } else { 493 mode[0] = mode[1] = 494 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 495 drvp[0].PIO_mode = mode[0]; 496 drvp[1].PIO_mode = mode[1]; 497 } 498 ok: /* The modes are setup */ 499 for (drive = 0; drive < 2; drive++) { 500 if (drvp[drive].drive_flags & DRIVE_DMA) { 501 idetim |= piix_setup_idetim_timings( 502 mode[drive], 1, chp->ch_channel); 503 goto end; 504 } 505 } 506 /* If we are there, none of the drives are DMA */ 507 if (mode[0] >= 2) 508 idetim |= piix_setup_idetim_timings( 509 mode[0], 0, chp->ch_channel); 510 else 511 idetim |= piix_setup_idetim_timings( 512 mode[1], 0, chp->ch_channel); 513 end: /* 514 * timing mode is now set up in the controller. Enable 515 * it per-drive 516 */ 517 for (drive = 0; drive < 2; drive++) { 518 /* If no drive, skip */ 519 if ((drvp[drive].drive_flags & DRIVE) == 0) 520 continue; 521 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 522 if (drvp[drive].drive_flags & DRIVE_DMA) 523 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 524 } 525 if (idedma_ctl != 0) { 526 /* Add software bits in status register */ 527 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 528 idedma_ctl); 529 } 530 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 531 } 532 533 static void 534 piix3_4_setup_channel(struct ata_channel *chp) 535 { 536 struct ata_drive_datas *drvp; 537 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 538 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 539 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 540 struct wdc_softc *wdc = &sc->sc_wdcdev; 541 int drive, s; 542 int channel = chp->ch_channel; 543 544 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 545 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 546 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 547 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 548 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 549 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 550 PIIX_SIDETIM_RTC_MASK(channel)); 551 idedma_ctl = 0; 552 553 /* set up new idetim: Enable IDE registers decode */ 554 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 555 556 /* setup DMA if needed */ 557 pciide_channel_dma_setup(cp); 558 559 for (drive = 0; drive < 2; drive++) { 560 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 561 PIIX_UDMATIM_SET(0x3, channel, drive)); 562 drvp = &chp->ch_drive[drive]; 563 /* If no drive, skip */ 564 if ((drvp->drive_flags & DRIVE) == 0) 565 continue; 566 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 567 (drvp->drive_flags & DRIVE_UDMA) == 0)) 568 goto pio; 569 570 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 571 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 572 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 573 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 574 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 575 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 576 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 577 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 578 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 579 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 580 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 581 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 582 ideconf |= PIIX_CONFIG_PINGPONG; 583 } 584 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 585 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 586 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 587 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 588 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 589 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 590 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 591 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 592 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 593 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 594 /* setup Ultra/100 */ 595 if (drvp->UDMA_mode > 2 && 596 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 597 drvp->UDMA_mode = 2; 598 if (drvp->UDMA_mode > 4) { 599 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 600 } else { 601 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 602 if (drvp->UDMA_mode > 2) { 603 ideconf |= PIIX_CONFIG_UDMA66(channel, 604 drive); 605 } else { 606 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 607 drive); 608 } 609 } 610 } 611 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 612 /* setup Ultra/66 */ 613 if (drvp->UDMA_mode > 2 && 614 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 615 drvp->UDMA_mode = 2; 616 if (drvp->UDMA_mode > 2) 617 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 618 else 619 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 620 } 621 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 622 (drvp->drive_flags & DRIVE_UDMA)) { 623 /* use Ultra/DMA */ 624 s = splbio(); 625 drvp->drive_flags &= ~DRIVE_DMA; 626 splx(s); 627 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 628 udmareg |= PIIX_UDMATIM_SET( 629 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 630 } else { 631 /* use Multiword DMA */ 632 s = splbio(); 633 drvp->drive_flags &= ~DRIVE_UDMA; 634 splx(s); 635 if (drive == 0) { 636 idetim |= piix_setup_idetim_timings( 637 drvp->DMA_mode, 1, channel); 638 } else { 639 sidetim |= piix_setup_sidetim_timings( 640 drvp->DMA_mode, 1, channel); 641 idetim =PIIX_IDETIM_SET(idetim, 642 PIIX_IDETIM_SITRE, channel); 643 } 644 } 645 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 646 647 pio: /* use PIO mode */ 648 idetim |= piix_setup_idetim_drvs(drvp); 649 if (drive == 0) { 650 idetim |= piix_setup_idetim_timings( 651 drvp->PIO_mode, 0, channel); 652 } else { 653 sidetim |= piix_setup_sidetim_timings( 654 drvp->PIO_mode, 0, channel); 655 idetim =PIIX_IDETIM_SET(idetim, 656 PIIX_IDETIM_SITRE, channel); 657 } 658 } 659 if (idedma_ctl != 0) { 660 /* Add software bits in status register */ 661 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 662 idedma_ctl); 663 } 664 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 665 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 666 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 667 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 668 } 669 670 671 /* setup ISP and RTC fields, based on mode */ 672 static u_int32_t 673 piix_setup_idetim_timings(mode, dma, channel) 674 u_int8_t mode; 675 u_int8_t dma; 676 u_int8_t channel; 677 { 678 679 if (dma) 680 return PIIX_IDETIM_SET(0, 681 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 682 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 683 channel); 684 else 685 return PIIX_IDETIM_SET(0, 686 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 687 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 688 channel); 689 } 690 691 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 692 static u_int32_t 693 piix_setup_idetim_drvs(drvp) 694 struct ata_drive_datas *drvp; 695 { 696 u_int32_t ret = 0; 697 struct ata_channel *chp = drvp->chnl_softc; 698 u_int8_t channel = chp->ch_channel; 699 u_int8_t drive = drvp->drive; 700 701 /* 702 * If drive is using UDMA, timings setups are independant 703 * So just check DMA and PIO here. 704 */ 705 if (drvp->drive_flags & DRIVE_DMA) { 706 /* if mode = DMA mode 0, use compatible timings */ 707 if ((drvp->drive_flags & DRIVE_DMA) && 708 drvp->DMA_mode == 0) { 709 drvp->PIO_mode = 0; 710 return ret; 711 } 712 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 713 /* 714 * PIO and DMA timings are the same, use fast timings for PIO 715 * too, else use compat timings. 716 */ 717 if ((piix_isp_pio[drvp->PIO_mode] != 718 piix_isp_dma[drvp->DMA_mode]) || 719 (piix_rtc_pio[drvp->PIO_mode] != 720 piix_rtc_dma[drvp->DMA_mode])) 721 drvp->PIO_mode = 0; 722 /* if PIO mode <= 2, use compat timings for PIO */ 723 if (drvp->PIO_mode <= 2) { 724 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 725 channel); 726 return ret; 727 } 728 } 729 730 /* 731 * Now setup PIO modes. If mode < 2, use compat timings. 732 * Else enable fast timings. Enable IORDY and prefetch/post 733 * if PIO mode >= 3. 734 */ 735 736 if (drvp->PIO_mode < 2) 737 return ret; 738 739 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 740 if (drvp->PIO_mode >= 3) { 741 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 742 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 743 } 744 return ret; 745 } 746 747 /* setup values in SIDETIM registers, based on mode */ 748 static u_int32_t 749 piix_setup_sidetim_timings(mode, dma, channel) 750 u_int8_t mode; 751 u_int8_t dma; 752 u_int8_t channel; 753 { 754 if (dma) 755 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 756 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 757 else 758 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 759 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 760 } 761 762 static void 763 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 764 { 765 struct pciide_channel *cp; 766 bus_size_t cmdsize, ctlsize; 767 pcireg_t interface, cmdsts; 768 int channel; 769 770 if (pciide_chipen(sc, pa) == 0) 771 return; 772 773 aprint_normal("%s: bus-master DMA support present", 774 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 775 pciide_mapreg_dma(sc, pa); 776 aprint_normal("\n"); 777 778 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 779 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 780 if (sc->sc_dma_ok) { 781 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 782 sc->sc_wdcdev.irqack = pciide_irqack; 783 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 784 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 785 } 786 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 787 788 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 789 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 790 791 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 792 cmdsts &= ~0x0400; 793 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 794 795 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 796 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 797 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 798 799 interface = PCI_INTERFACE(pa->pa_class); 800 801 wdc_allocate_regs(&sc->sc_wdcdev); 802 803 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 804 channel++) { 805 cp = &sc->pciide_channels[channel]; 806 if (pciide_chansetup(sc, channel, interface) == 0) 807 continue; 808 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 809 pciide_pci_intr); 810 } 811 } 812
Indexes created Fri Oct 17 00:09:41 GMT 2025