piixide.c revision 1.26.4.1
1 /* $NetBSD: piixide.c,v 1.26.4.1 2006/07/13 17:49:29 gdamore Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.26.4.1 2006/07/13 17:49:29 gdamore Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 52 static void piixide_powerhook(int, void *); 53 static int piixide_match(struct device *, struct cfdata *, void *); 54 static void piixide_attach(struct device *, struct device *, void *); 55 56 static const struct pciide_product_desc pciide_intel_products[] = { 57 { PCI_PRODUCT_INTEL_82092AA, 58 0, 59 "Intel 82092AA IDE controller", 60 default_chip_map, 61 }, 62 { PCI_PRODUCT_INTEL_82371FB_IDE, 63 0, 64 "Intel 82371FB IDE controller (PIIX)", 65 piix_chip_map, 66 }, 67 { PCI_PRODUCT_INTEL_82371SB_IDE, 68 0, 69 "Intel 82371SB IDE Interface (PIIX3)", 70 piix_chip_map, 71 }, 72 { PCI_PRODUCT_INTEL_82371AB_IDE, 73 0, 74 "Intel 82371AB IDE controller (PIIX4)", 75 piix_chip_map, 76 }, 77 { PCI_PRODUCT_INTEL_82440MX_IDE, 78 0, 79 "Intel 82440MX IDE controller", 80 piix_chip_map 81 }, 82 { PCI_PRODUCT_INTEL_82801AA_IDE, 83 0, 84 "Intel 82801AA IDE Controller (ICH)", 85 piix_chip_map, 86 }, 87 { PCI_PRODUCT_INTEL_82801AB_IDE, 88 0, 89 "Intel 82801AB IDE Controller (ICH0)", 90 piix_chip_map, 91 }, 92 { PCI_PRODUCT_INTEL_82801BA_IDE, 93 0, 94 "Intel 82801BA IDE Controller (ICH2)", 95 piix_chip_map, 96 }, 97 { PCI_PRODUCT_INTEL_82801BAM_IDE, 98 0, 99 "Intel 82801BAM IDE Controller (ICH2-M)", 100 piix_chip_map, 101 }, 102 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 103 0, 104 "Intel 82801CA IDE Controller (ICH3)", 105 piix_chip_map, 106 }, 107 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 108 0, 109 "Intel 82801CA IDE Controller (ICH3)", 110 piix_chip_map, 111 }, 112 { PCI_PRODUCT_INTEL_82801DB_IDE, 113 0, 114 "Intel 82801DB IDE Controller (ICH4)", 115 piix_chip_map, 116 }, 117 { PCI_PRODUCT_INTEL_82801DBM_IDE, 118 0, 119 "Intel 82801DBM IDE Controller (ICH4-M)", 120 piix_chip_map, 121 }, 122 { PCI_PRODUCT_INTEL_82801EB_IDE, 123 0, 124 "Intel 82801EB IDE Controller (ICH5)", 125 piix_chip_map, 126 }, 127 { PCI_PRODUCT_INTEL_82801EB_SATA, 128 0, 129 "Intel 82801EB Serial ATA Controller", 130 piixsata_chip_map, 131 }, 132 { PCI_PRODUCT_INTEL_82801ER_SATA, 133 0, 134 "Intel 82801ER Serial ATA/Raid Controller", 135 piixsata_chip_map, 136 }, 137 { PCI_PRODUCT_INTEL_6300ESB_IDE, 138 0, 139 "Intel 6300ESB IDE Controller (ICH5)", 140 piix_chip_map, 141 }, 142 { PCI_PRODUCT_INTEL_6300ESB_SATA, 143 0, 144 "Intel 6300ESB Serial ATA Controller", 145 piixsata_chip_map, 146 }, 147 { PCI_PRODUCT_INTEL_6300ESB_RAID, 148 0, 149 "Intel 6300ESB Serial ATA/RAID Controller", 150 piixsata_chip_map, 151 }, 152 { PCI_PRODUCT_INTEL_82801FB_IDE, 153 0, 154 "Intel 82801FB IDE Controller (ICH6)", 155 piix_chip_map, 156 }, 157 { PCI_PRODUCT_INTEL_82801FB_SATA, 158 0, 159 "Intel 82801FB Serial ATA/Raid Controller", 160 piixsata_chip_map, 161 }, 162 { PCI_PRODUCT_INTEL_82801FR_SATA, 163 0, 164 "Intel 82801FR Serial ATA/Raid Controller", 165 piixsata_chip_map, 166 }, 167 { PCI_PRODUCT_INTEL_82801FBM_SATA, 168 0, 169 "Intel 82801FBM Serial ATA Controller (ICH6)", 170 piixsata_chip_map, 171 }, 172 { PCI_PRODUCT_INTEL_82801G_IDE, 173 0, 174 "Intel 82801GB/GR IDE Controller (ICH7)", 175 piix_chip_map, 176 }, 177 { PCI_PRODUCT_INTEL_82801G_SATA, 178 0, 179 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 180 piixsata_chip_map, 181 }, 182 { PCI_PRODUCT_INTEL_82801GBM_SATA, 183 0, 184 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 185 piixsata_chip_map, 186 }, 187 { 0, 188 0, 189 NULL, 190 NULL 191 } 192 }; 193 194 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 195 piixide_match, piixide_attach, NULL, NULL); 196 197 static int 198 piixide_match(struct device *parent, struct cfdata *match, void *aux) 199 { 200 struct pci_attach_args *pa = aux; 201 202 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 203 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 204 return (2); 205 } 206 return (0); 207 } 208 209 static void 210 piixide_attach(struct device *parent, struct device *self, void *aux) 211 { 212 struct pci_attach_args *pa = aux; 213 struct pciide_softc *sc = (struct pciide_softc *)self; 214 215 pciide_common_attach(sc, pa, 216 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 217 218 /* Setup our powerhook */ 219 sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc); 220 if (sc->sc_powerhook == NULL) 221 printf("%s: WARNING: unable to establish PCI power hook\n", 222 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 223 } 224 225 static void 226 piixide_powerhook(int why, void *hdl) 227 { 228 struct pciide_softc *sc = (struct pciide_softc *)hdl; 229 230 switch (why) { 231 case PWR_SUSPEND: 232 case PWR_STANDBY: 233 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 234 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 235 PIIX_IDETIM); 236 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 237 PIIX_UDMATIM); 238 break; 239 case PWR_RESUME: 240 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 241 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 242 sc->sc_idetim); 243 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 244 sc->sc_udmatim); 245 break; 246 case PWR_SOFTSUSPEND: 247 case PWR_SOFTSTANDBY: 248 case PWR_SOFTRESUME: 249 break; 250 } 251 252 return; 253 } 254 255 static void 256 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 257 { 258 struct pciide_channel *cp; 259 int channel; 260 u_int32_t idetim; 261 bus_size_t cmdsize, ctlsize; 262 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 263 264 if (pciide_chipen(sc, pa) == 0) 265 return; 266 267 aprint_normal("%s: bus-master DMA support present", 268 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 269 pciide_mapreg_dma(sc, pa); 270 aprint_normal("\n"); 271 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 272 if (sc->sc_dma_ok) { 273 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 274 sc->sc_wdcdev.irqack = pciide_irqack; 275 switch(sc->sc_pp->ide_product) { 276 case PCI_PRODUCT_INTEL_82371AB_IDE: 277 case PCI_PRODUCT_INTEL_82440MX_IDE: 278 case PCI_PRODUCT_INTEL_82801AA_IDE: 279 case PCI_PRODUCT_INTEL_82801AB_IDE: 280 case PCI_PRODUCT_INTEL_82801BA_IDE: 281 case PCI_PRODUCT_INTEL_82801BAM_IDE: 282 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 283 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 284 case PCI_PRODUCT_INTEL_82801DB_IDE: 285 case PCI_PRODUCT_INTEL_82801DBM_IDE: 286 case PCI_PRODUCT_INTEL_82801EB_IDE: 287 case PCI_PRODUCT_INTEL_6300ESB_IDE: 288 case PCI_PRODUCT_INTEL_82801FB_IDE: 289 case PCI_PRODUCT_INTEL_82801G_IDE: 290 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 291 } 292 } 293 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 294 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 295 switch(sc->sc_pp->ide_product) { 296 case PCI_PRODUCT_INTEL_82801AA_IDE: 297 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 298 break; 299 case PCI_PRODUCT_INTEL_82801BA_IDE: 300 case PCI_PRODUCT_INTEL_82801BAM_IDE: 301 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 302 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 303 case PCI_PRODUCT_INTEL_82801DB_IDE: 304 case PCI_PRODUCT_INTEL_82801DBM_IDE: 305 case PCI_PRODUCT_INTEL_82801EB_IDE: 306 case PCI_PRODUCT_INTEL_6300ESB_IDE: 307 case PCI_PRODUCT_INTEL_82801FB_IDE: 308 case PCI_PRODUCT_INTEL_82801G_IDE: 309 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 310 break; 311 default: 312 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 313 } 314 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 315 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 316 else 317 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 318 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 319 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 320 321 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 322 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 323 DEBUG_PROBE); 324 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 325 ATADEBUG_PRINT((", sidetim=0x%x", 326 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 327 DEBUG_PROBE); 328 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 329 ATADEBUG_PRINT((", udamreg 0x%x", 330 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 331 DEBUG_PROBE); 332 } 333 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 334 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 335 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 336 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 337 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 338 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 339 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 340 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 341 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 342 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 343 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 344 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 345 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 346 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 347 DEBUG_PROBE); 348 } 349 350 } 351 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 352 353 wdc_allocate_regs(&sc->sc_wdcdev); 354 355 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 356 channel++) { 357 cp = &sc->pciide_channels[channel]; 358 if (pciide_chansetup(sc, channel, interface) == 0) 359 continue; 360 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 361 if ((PIIX_IDETIM_READ(idetim, channel) & 362 PIIX_IDETIM_IDE) == 0) { 363 #if 1 364 aprint_normal("%s: %s channel ignored (disabled)\n", 365 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 366 cp->ata_channel.ch_flags |= ATACH_DISABLED; 367 continue; 368 #else 369 pcireg_t interface; 370 371 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 372 channel); 373 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 374 idetim); 375 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 376 sc->sc_tag, PCI_CLASS_REG)); 377 aprint_normal("channel %d idetim=%08x interface=%02x\n", 378 channel, idetim, interface); 379 #endif 380 } 381 pciide_mapchan(pa, cp, interface, 382 &cmdsize, &ctlsize, pciide_pci_intr); 383 } 384 385 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 386 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 387 DEBUG_PROBE); 388 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 389 ATADEBUG_PRINT((", sidetim=0x%x", 390 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 391 DEBUG_PROBE); 392 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 393 ATADEBUG_PRINT((", udamreg 0x%x", 394 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 395 DEBUG_PROBE); 396 } 397 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 398 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 400 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 402 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 404 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 405 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 406 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 407 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 408 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 409 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 410 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 411 DEBUG_PROBE); 412 } 413 } 414 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 415 } 416 417 static void 418 piix_setup_channel(struct ata_channel *chp) 419 { 420 u_int8_t mode[2], drive; 421 u_int32_t oidetim, idetim, idedma_ctl; 422 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 423 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 424 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 425 426 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 427 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 428 idedma_ctl = 0; 429 430 /* set up new idetim: Enable IDE registers decode */ 431 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 432 chp->ch_channel); 433 434 /* setup DMA */ 435 pciide_channel_dma_setup(cp); 436 437 /* 438 * Here we have to mess up with drives mode: PIIX can't have 439 * different timings for master and slave drives. 440 * We need to find the best combination. 441 */ 442 443 /* If both drives supports DMA, take the lower mode */ 444 if ((drvp[0].drive_flags & DRIVE_DMA) && 445 (drvp[1].drive_flags & DRIVE_DMA)) { 446 mode[0] = mode[1] = 447 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 448 drvp[0].DMA_mode = mode[0]; 449 drvp[1].DMA_mode = mode[1]; 450 goto ok; 451 } 452 /* 453 * If only one drive supports DMA, use its mode, and 454 * put the other one in PIO mode 0 if mode not compatible 455 */ 456 if (drvp[0].drive_flags & DRIVE_DMA) { 457 mode[0] = drvp[0].DMA_mode; 458 mode[1] = drvp[1].PIO_mode; 459 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 460 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 461 mode[1] = drvp[1].PIO_mode = 0; 462 goto ok; 463 } 464 if (drvp[1].drive_flags & DRIVE_DMA) { 465 mode[1] = drvp[1].DMA_mode; 466 mode[0] = drvp[0].PIO_mode; 467 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 468 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 469 mode[0] = drvp[0].PIO_mode = 0; 470 goto ok; 471 } 472 /* 473 * If both drives are not DMA, takes the lower mode, unless 474 * one of them is PIO mode < 2 475 */ 476 if (drvp[0].PIO_mode < 2) { 477 mode[0] = drvp[0].PIO_mode = 0; 478 mode[1] = drvp[1].PIO_mode; 479 } else if (drvp[1].PIO_mode < 2) { 480 mode[1] = drvp[1].PIO_mode = 0; 481 mode[0] = drvp[0].PIO_mode; 482 } else { 483 mode[0] = mode[1] = 484 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 485 drvp[0].PIO_mode = mode[0]; 486 drvp[1].PIO_mode = mode[1]; 487 } 488 ok: /* The modes are setup */ 489 for (drive = 0; drive < 2; drive++) { 490 if (drvp[drive].drive_flags & DRIVE_DMA) { 491 idetim |= piix_setup_idetim_timings( 492 mode[drive], 1, chp->ch_channel); 493 goto end; 494 } 495 } 496 /* If we are there, none of the drives are DMA */ 497 if (mode[0] >= 2) 498 idetim |= piix_setup_idetim_timings( 499 mode[0], 0, chp->ch_channel); 500 else 501 idetim |= piix_setup_idetim_timings( 502 mode[1], 0, chp->ch_channel); 503 end: /* 504 * timing mode is now set up in the controller. Enable 505 * it per-drive 506 */ 507 for (drive = 0; drive < 2; drive++) { 508 /* If no drive, skip */ 509 if ((drvp[drive].drive_flags & DRIVE) == 0) 510 continue; 511 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 512 if (drvp[drive].drive_flags & DRIVE_DMA) 513 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 514 } 515 if (idedma_ctl != 0) { 516 /* Add software bits in status register */ 517 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 518 idedma_ctl); 519 } 520 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 521 } 522 523 static void 524 piix3_4_setup_channel(struct ata_channel *chp) 525 { 526 struct ata_drive_datas *drvp; 527 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 528 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 529 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 530 struct wdc_softc *wdc = &sc->sc_wdcdev; 531 int drive, s; 532 int channel = chp->ch_channel; 533 534 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 535 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 536 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 537 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 538 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 539 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 540 PIIX_SIDETIM_RTC_MASK(channel)); 541 idedma_ctl = 0; 542 543 /* set up new idetim: Enable IDE registers decode */ 544 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 545 546 /* setup DMA if needed */ 547 pciide_channel_dma_setup(cp); 548 549 for (drive = 0; drive < 2; drive++) { 550 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 551 PIIX_UDMATIM_SET(0x3, channel, drive)); 552 drvp = &chp->ch_drive[drive]; 553 /* If no drive, skip */ 554 if ((drvp->drive_flags & DRIVE) == 0) 555 continue; 556 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 557 (drvp->drive_flags & DRIVE_UDMA) == 0)) 558 goto pio; 559 560 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 561 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 562 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 563 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 564 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 565 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 566 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 567 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 568 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 569 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 570 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 571 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 572 ideconf |= PIIX_CONFIG_PINGPONG; 573 } 574 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 575 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 576 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 577 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 578 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 579 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 580 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 581 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 582 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 583 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 584 /* setup Ultra/100 */ 585 if (drvp->UDMA_mode > 2 && 586 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 587 drvp->UDMA_mode = 2; 588 if (drvp->UDMA_mode > 4) { 589 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 590 } else { 591 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 592 if (drvp->UDMA_mode > 2) { 593 ideconf |= PIIX_CONFIG_UDMA66(channel, 594 drive); 595 } else { 596 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 597 drive); 598 } 599 } 600 } 601 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 602 /* setup Ultra/66 */ 603 if (drvp->UDMA_mode > 2 && 604 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 605 drvp->UDMA_mode = 2; 606 if (drvp->UDMA_mode > 2) 607 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 608 else 609 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 610 } 611 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 612 (drvp->drive_flags & DRIVE_UDMA)) { 613 /* use Ultra/DMA */ 614 s = splbio(); 615 drvp->drive_flags &= ~DRIVE_DMA; 616 splx(s); 617 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 618 udmareg |= PIIX_UDMATIM_SET( 619 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 620 } else { 621 /* use Multiword DMA */ 622 s = splbio(); 623 drvp->drive_flags &= ~DRIVE_UDMA; 624 splx(s); 625 if (drive == 0) { 626 idetim |= piix_setup_idetim_timings( 627 drvp->DMA_mode, 1, channel); 628 } else { 629 sidetim |= piix_setup_sidetim_timings( 630 drvp->DMA_mode, 1, channel); 631 idetim =PIIX_IDETIM_SET(idetim, 632 PIIX_IDETIM_SITRE, channel); 633 } 634 } 635 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 636 637 pio: /* use PIO mode */ 638 idetim |= piix_setup_idetim_drvs(drvp); 639 if (drive == 0) { 640 idetim |= piix_setup_idetim_timings( 641 drvp->PIO_mode, 0, channel); 642 } else { 643 sidetim |= piix_setup_sidetim_timings( 644 drvp->PIO_mode, 0, channel); 645 idetim =PIIX_IDETIM_SET(idetim, 646 PIIX_IDETIM_SITRE, channel); 647 } 648 } 649 if (idedma_ctl != 0) { 650 /* Add software bits in status register */ 651 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 652 idedma_ctl); 653 } 654 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 655 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 656 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 657 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 658 } 659 660 661 /* setup ISP and RTC fields, based on mode */ 662 static u_int32_t 663 piix_setup_idetim_timings(mode, dma, channel) 664 u_int8_t mode; 665 u_int8_t dma; 666 u_int8_t channel; 667 { 668 669 if (dma) 670 return PIIX_IDETIM_SET(0, 671 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 672 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 673 channel); 674 else 675 return PIIX_IDETIM_SET(0, 676 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 677 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 678 channel); 679 } 680 681 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 682 static u_int32_t 683 piix_setup_idetim_drvs(drvp) 684 struct ata_drive_datas *drvp; 685 { 686 u_int32_t ret = 0; 687 struct ata_channel *chp = drvp->chnl_softc; 688 u_int8_t channel = chp->ch_channel; 689 u_int8_t drive = drvp->drive; 690 691 /* 692 * If drive is using UDMA, timings setups are independant 693 * So just check DMA and PIO here. 694 */ 695 if (drvp->drive_flags & DRIVE_DMA) { 696 /* if mode = DMA mode 0, use compatible timings */ 697 if ((drvp->drive_flags & DRIVE_DMA) && 698 drvp->DMA_mode == 0) { 699 drvp->PIO_mode = 0; 700 return ret; 701 } 702 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 703 /* 704 * PIO and DMA timings are the same, use fast timings for PIO 705 * too, else use compat timings. 706 */ 707 if ((piix_isp_pio[drvp->PIO_mode] != 708 piix_isp_dma[drvp->DMA_mode]) || 709 (piix_rtc_pio[drvp->PIO_mode] != 710 piix_rtc_dma[drvp->DMA_mode])) 711 drvp->PIO_mode = 0; 712 /* if PIO mode <= 2, use compat timings for PIO */ 713 if (drvp->PIO_mode <= 2) { 714 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 715 channel); 716 return ret; 717 } 718 } 719 720 /* 721 * Now setup PIO modes. If mode < 2, use compat timings. 722 * Else enable fast timings. Enable IORDY and prefetch/post 723 * if PIO mode >= 3. 724 */ 725 726 if (drvp->PIO_mode < 2) 727 return ret; 728 729 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 730 if (drvp->PIO_mode >= 3) { 731 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 732 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 733 } 734 return ret; 735 } 736 737 /* setup values in SIDETIM registers, based on mode */ 738 static u_int32_t 739 piix_setup_sidetim_timings(mode, dma, channel) 740 u_int8_t mode; 741 u_int8_t dma; 742 u_int8_t channel; 743 { 744 if (dma) 745 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 746 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 747 else 748 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 749 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 750 } 751 752 static void 753 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 754 { 755 struct pciide_channel *cp; 756 bus_size_t cmdsize, ctlsize; 757 pcireg_t interface, cmdsts; 758 int channel; 759 760 if (pciide_chipen(sc, pa) == 0) 761 return; 762 763 aprint_normal("%s: bus-master DMA support present", 764 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 765 pciide_mapreg_dma(sc, pa); 766 aprint_normal("\n"); 767 768 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 769 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 770 if (sc->sc_dma_ok) { 771 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 772 sc->sc_wdcdev.irqack = pciide_irqack; 773 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 774 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 775 } 776 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 777 778 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 779 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 780 781 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 782 cmdsts &= ~0x0400; 783 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 784 785 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 786 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 787 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 788 789 interface = PCI_INTERFACE(pa->pa_class); 790 791 wdc_allocate_regs(&sc->sc_wdcdev); 792 793 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 794 channel++) { 795 cp = &sc->pciide_channels[channel]; 796 if (pciide_chansetup(sc, channel, interface) == 0) 797 continue; 798 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 799 pciide_pci_intr); 800 } 801 } 802
Indexes created Wed Oct 15 16:09:53 GMT 2025