piixide.c revision 1.29.2.2
1 /* $NetBSD: piixide.c,v 1.29.2.2 2007/01/12 00:57:43 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.29.2.2 2007/01/12 00:57:43 ad Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 52 static void piixide_powerhook(int, void *); 53 static int piixide_match(struct device *, struct cfdata *, void *); 54 static void piixide_attach(struct device *, struct device *, void *); 55 56 static const struct pciide_product_desc pciide_intel_products[] = { 57 { PCI_PRODUCT_INTEL_82092AA, 58 0, 59 "Intel 82092AA IDE controller", 60 default_chip_map, 61 }, 62 { PCI_PRODUCT_INTEL_82371FB_IDE, 63 0, 64 "Intel 82371FB IDE controller (PIIX)", 65 piix_chip_map, 66 }, 67 { PCI_PRODUCT_INTEL_82371SB_IDE, 68 0, 69 "Intel 82371SB IDE Interface (PIIX3)", 70 piix_chip_map, 71 }, 72 { PCI_PRODUCT_INTEL_82371AB_IDE, 73 0, 74 "Intel 82371AB IDE controller (PIIX4)", 75 piix_chip_map, 76 }, 77 { PCI_PRODUCT_INTEL_82440MX_IDE, 78 0, 79 "Intel 82440MX IDE controller", 80 piix_chip_map 81 }, 82 { PCI_PRODUCT_INTEL_82801AA_IDE, 83 0, 84 "Intel 82801AA IDE Controller (ICH)", 85 piix_chip_map, 86 }, 87 { PCI_PRODUCT_INTEL_82801AB_IDE, 88 0, 89 "Intel 82801AB IDE Controller (ICH0)", 90 piix_chip_map, 91 }, 92 { PCI_PRODUCT_INTEL_82801BA_IDE, 93 0, 94 "Intel 82801BA IDE Controller (ICH2)", 95 piix_chip_map, 96 }, 97 { PCI_PRODUCT_INTEL_82801BAM_IDE, 98 0, 99 "Intel 82801BAM IDE Controller (ICH2-M)", 100 piix_chip_map, 101 }, 102 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 103 0, 104 "Intel 82801CA IDE Controller (ICH3)", 105 piix_chip_map, 106 }, 107 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 108 0, 109 "Intel 82801CA IDE Controller (ICH3)", 110 piix_chip_map, 111 }, 112 { PCI_PRODUCT_INTEL_82801DB_IDE, 113 0, 114 "Intel 82801DB IDE Controller (ICH4)", 115 piix_chip_map, 116 }, 117 { PCI_PRODUCT_INTEL_82801DBM_IDE, 118 0, 119 "Intel 82801DBM IDE Controller (ICH4-M)", 120 piix_chip_map, 121 }, 122 { PCI_PRODUCT_INTEL_82801EB_IDE, 123 0, 124 "Intel 82801EB IDE Controller (ICH5)", 125 piix_chip_map, 126 }, 127 { PCI_PRODUCT_INTEL_82801EB_SATA, 128 0, 129 "Intel 82801EB Serial ATA Controller", 130 piixsata_chip_map, 131 }, 132 { PCI_PRODUCT_INTEL_82801ER_SATA, 133 0, 134 "Intel 82801ER Serial ATA/Raid Controller", 135 piixsata_chip_map, 136 }, 137 { PCI_PRODUCT_INTEL_6300ESB_IDE, 138 0, 139 "Intel 6300ESB IDE Controller (ICH5)", 140 piix_chip_map, 141 }, 142 { PCI_PRODUCT_INTEL_6300ESB_SATA, 143 0, 144 "Intel 6300ESB Serial ATA Controller", 145 piixsata_chip_map, 146 }, 147 { PCI_PRODUCT_INTEL_6300ESB_RAID, 148 0, 149 "Intel 6300ESB Serial ATA/RAID Controller", 150 piixsata_chip_map, 151 }, 152 { PCI_PRODUCT_INTEL_82801FB_IDE, 153 0, 154 "Intel 82801FB IDE Controller (ICH6)", 155 piix_chip_map, 156 }, 157 { PCI_PRODUCT_INTEL_82801FB_SATA, 158 0, 159 "Intel 82801FB Serial ATA/Raid Controller", 160 piixsata_chip_map, 161 }, 162 { PCI_PRODUCT_INTEL_82801FR_SATA, 163 0, 164 "Intel 82801FR Serial ATA/Raid Controller", 165 piixsata_chip_map, 166 }, 167 { PCI_PRODUCT_INTEL_82801FBM_SATA, 168 0, 169 "Intel 82801FBM Serial ATA Controller (ICH6)", 170 piixsata_chip_map, 171 }, 172 { PCI_PRODUCT_INTEL_82801G_IDE, 173 0, 174 "Intel 82801GB/GR IDE Controller (ICH7)", 175 piix_chip_map, 176 }, 177 { PCI_PRODUCT_INTEL_82801G_SATA, 178 0, 179 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 180 piixsata_chip_map, 181 }, 182 { PCI_PRODUCT_INTEL_82801GBM_SATA, 183 0, 184 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 185 piixsata_chip_map, 186 }, 187 { PCI_PRODUCT_INTEL_82801H_SATA_1, 188 0, 189 "Intel 82801H Serial ATA Controller (ICH8)", 190 piixsata_chip_map, 191 }, 192 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 193 0, 194 "Intel 82801H Serial ATA RAID Controller (ICH8)", 195 piixsata_chip_map, 196 }, 197 { PCI_PRODUCT_INTEL_82801H_SATA_2, 198 0, 199 "Intel 82801H Serial ATA Controller (ICH8)", 200 piixsata_chip_map, 201 }, 202 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 203 0, 204 "Intel 82801HBM Serial ATA Controller (ICH8M)", 205 piixsata_chip_map, 206 }, 207 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 208 0, 209 "Intel 82801HBM Serial ATA Controller (ICH8M)", 210 piixsata_chip_map, 211 }, 212 { PCI_PRODUCT_INTEL_63XXESB_IDE, 213 0, 214 "Intel 631xESB/632xESB IDE Controller", 215 piix_chip_map, 216 }, 217 { PCI_PRODUCT_INTEL_63XXESB_SATA, 218 0, 219 "Intel 631xESB/632xESB Serial ATA Controller", 220 piixsata_chip_map, 221 }, 222 { 0, 223 0, 224 NULL, 225 NULL 226 } 227 }; 228 229 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 230 piixide_match, piixide_attach, NULL, NULL); 231 232 static int 233 piixide_match(struct device *parent, struct cfdata *match, 234 void *aux) 235 { 236 struct pci_attach_args *pa = aux; 237 238 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 239 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 240 return (2); 241 } 242 return (0); 243 } 244 245 static void 246 piixide_attach(struct device *parent, struct device *self, void *aux) 247 { 248 struct pci_attach_args *pa = aux; 249 struct pciide_softc *sc = (struct pciide_softc *)self; 250 251 pciide_common_attach(sc, pa, 252 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 253 254 /* Setup our powerhook */ 255 sc->sc_powerhook = powerhook_establish( 256 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, piixide_powerhook, sc); 257 if (sc->sc_powerhook == NULL) 258 printf("%s: WARNING: unable to establish PCI power hook\n", 259 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 260 } 261 262 static void 263 piixide_powerhook(int why, void *hdl) 264 { 265 struct pciide_softc *sc = (struct pciide_softc *)hdl; 266 267 switch (why) { 268 case PWR_SUSPEND: 269 case PWR_STANDBY: 270 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 271 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 272 PIIX_IDETIM); 273 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 274 PIIX_UDMATIM); 275 break; 276 case PWR_RESUME: 277 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 278 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 279 sc->sc_idetim); 280 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 281 sc->sc_udmatim); 282 break; 283 case PWR_SOFTSUSPEND: 284 case PWR_SOFTSTANDBY: 285 case PWR_SOFTRESUME: 286 break; 287 } 288 289 return; 290 } 291 292 static void 293 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 294 { 295 struct pciide_channel *cp; 296 int channel; 297 u_int32_t idetim; 298 bus_size_t cmdsize, ctlsize; 299 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 300 301 if (pciide_chipen(sc, pa) == 0) 302 return; 303 304 aprint_normal("%s: bus-master DMA support present", 305 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 306 pciide_mapreg_dma(sc, pa); 307 aprint_normal("\n"); 308 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 309 if (sc->sc_dma_ok) { 310 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 311 sc->sc_wdcdev.irqack = pciide_irqack; 312 switch(sc->sc_pp->ide_product) { 313 case PCI_PRODUCT_INTEL_82371AB_IDE: 314 case PCI_PRODUCT_INTEL_82440MX_IDE: 315 case PCI_PRODUCT_INTEL_82801AA_IDE: 316 case PCI_PRODUCT_INTEL_82801AB_IDE: 317 case PCI_PRODUCT_INTEL_82801BA_IDE: 318 case PCI_PRODUCT_INTEL_82801BAM_IDE: 319 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 320 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 321 case PCI_PRODUCT_INTEL_82801DB_IDE: 322 case PCI_PRODUCT_INTEL_82801DBM_IDE: 323 case PCI_PRODUCT_INTEL_82801EB_IDE: 324 case PCI_PRODUCT_INTEL_6300ESB_IDE: 325 case PCI_PRODUCT_INTEL_82801FB_IDE: 326 case PCI_PRODUCT_INTEL_82801G_IDE: 327 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 328 } 329 } 330 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 331 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 332 switch(sc->sc_pp->ide_product) { 333 case PCI_PRODUCT_INTEL_82801AA_IDE: 334 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 335 break; 336 case PCI_PRODUCT_INTEL_82801BA_IDE: 337 case PCI_PRODUCT_INTEL_82801BAM_IDE: 338 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 339 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 340 case PCI_PRODUCT_INTEL_82801DB_IDE: 341 case PCI_PRODUCT_INTEL_82801DBM_IDE: 342 case PCI_PRODUCT_INTEL_82801EB_IDE: 343 case PCI_PRODUCT_INTEL_6300ESB_IDE: 344 case PCI_PRODUCT_INTEL_82801FB_IDE: 345 case PCI_PRODUCT_INTEL_82801G_IDE: 346 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 347 break; 348 default: 349 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 350 } 351 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 352 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 353 else 354 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 355 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 356 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 357 358 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 359 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 360 DEBUG_PROBE); 361 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 362 ATADEBUG_PRINT((", sidetim=0x%x", 363 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 364 DEBUG_PROBE); 365 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 366 ATADEBUG_PRINT((", udamreg 0x%x", 367 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 368 DEBUG_PROBE); 369 } 370 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 371 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 372 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 373 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 374 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 375 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 376 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 377 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 378 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 379 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 380 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 381 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 382 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 383 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 384 DEBUG_PROBE); 385 } 386 387 } 388 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 389 390 wdc_allocate_regs(&sc->sc_wdcdev); 391 392 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 393 channel++) { 394 cp = &sc->pciide_channels[channel]; 395 if (pciide_chansetup(sc, channel, interface) == 0) 396 continue; 397 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 398 if ((PIIX_IDETIM_READ(idetim, channel) & 399 PIIX_IDETIM_IDE) == 0) { 400 #if 1 401 aprint_normal("%s: %s channel ignored (disabled)\n", 402 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 403 cp->ata_channel.ch_flags |= ATACH_DISABLED; 404 continue; 405 #else 406 pcireg_t interface; 407 408 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 409 channel); 410 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 411 idetim); 412 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 413 sc->sc_tag, PCI_CLASS_REG)); 414 aprint_normal("channel %d idetim=%08x interface=%02x\n", 415 channel, idetim, interface); 416 #endif 417 } 418 pciide_mapchan(pa, cp, interface, 419 &cmdsize, &ctlsize, pciide_pci_intr); 420 } 421 422 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 423 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 424 DEBUG_PROBE); 425 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 426 ATADEBUG_PRINT((", sidetim=0x%x", 427 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 428 DEBUG_PROBE); 429 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 430 ATADEBUG_PRINT((", udamreg 0x%x", 431 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 432 DEBUG_PROBE); 433 } 434 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 435 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 436 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 437 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 438 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 439 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 440 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 441 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 442 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 443 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 444 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 445 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 446 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 447 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 448 DEBUG_PROBE); 449 } 450 } 451 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 452 } 453 454 static void 455 piix_setup_channel(struct ata_channel *chp) 456 { 457 u_int8_t mode[2], drive; 458 u_int32_t oidetim, idetim, idedma_ctl; 459 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 460 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 461 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 462 463 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 464 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 465 idedma_ctl = 0; 466 467 /* set up new idetim: Enable IDE registers decode */ 468 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 469 chp->ch_channel); 470 471 /* setup DMA */ 472 pciide_channel_dma_setup(cp); 473 474 /* 475 * Here we have to mess up with drives mode: PIIX can't have 476 * different timings for master and slave drives. 477 * We need to find the best combination. 478 */ 479 480 /* If both drives supports DMA, take the lower mode */ 481 if ((drvp[0].drive_flags & DRIVE_DMA) && 482 (drvp[1].drive_flags & DRIVE_DMA)) { 483 mode[0] = mode[1] = 484 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 485 drvp[0].DMA_mode = mode[0]; 486 drvp[1].DMA_mode = mode[1]; 487 goto ok; 488 } 489 /* 490 * If only one drive supports DMA, use its mode, and 491 * put the other one in PIO mode 0 if mode not compatible 492 */ 493 if (drvp[0].drive_flags & DRIVE_DMA) { 494 mode[0] = drvp[0].DMA_mode; 495 mode[1] = drvp[1].PIO_mode; 496 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 497 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 498 mode[1] = drvp[1].PIO_mode = 0; 499 goto ok; 500 } 501 if (drvp[1].drive_flags & DRIVE_DMA) { 502 mode[1] = drvp[1].DMA_mode; 503 mode[0] = drvp[0].PIO_mode; 504 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 505 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 506 mode[0] = drvp[0].PIO_mode = 0; 507 goto ok; 508 } 509 /* 510 * If both drives are not DMA, takes the lower mode, unless 511 * one of them is PIO mode < 2 512 */ 513 if (drvp[0].PIO_mode < 2) { 514 mode[0] = drvp[0].PIO_mode = 0; 515 mode[1] = drvp[1].PIO_mode; 516 } else if (drvp[1].PIO_mode < 2) { 517 mode[1] = drvp[1].PIO_mode = 0; 518 mode[0] = drvp[0].PIO_mode; 519 } else { 520 mode[0] = mode[1] = 521 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 522 drvp[0].PIO_mode = mode[0]; 523 drvp[1].PIO_mode = mode[1]; 524 } 525 ok: /* The modes are setup */ 526 for (drive = 0; drive < 2; drive++) { 527 if (drvp[drive].drive_flags & DRIVE_DMA) { 528 idetim |= piix_setup_idetim_timings( 529 mode[drive], 1, chp->ch_channel); 530 goto end; 531 } 532 } 533 /* If we are there, none of the drives are DMA */ 534 if (mode[0] >= 2) 535 idetim |= piix_setup_idetim_timings( 536 mode[0], 0, chp->ch_channel); 537 else 538 idetim |= piix_setup_idetim_timings( 539 mode[1], 0, chp->ch_channel); 540 end: /* 541 * timing mode is now set up in the controller. Enable 542 * it per-drive 543 */ 544 for (drive = 0; drive < 2; drive++) { 545 /* If no drive, skip */ 546 if ((drvp[drive].drive_flags & DRIVE) == 0) 547 continue; 548 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 549 if (drvp[drive].drive_flags & DRIVE_DMA) 550 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 551 } 552 if (idedma_ctl != 0) { 553 /* Add software bits in status register */ 554 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 555 idedma_ctl); 556 } 557 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 558 } 559 560 static void 561 piix3_4_setup_channel(struct ata_channel *chp) 562 { 563 struct ata_drive_datas *drvp; 564 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 565 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 566 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 567 struct wdc_softc *wdc = &sc->sc_wdcdev; 568 int drive, s; 569 int channel = chp->ch_channel; 570 571 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 572 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 573 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 574 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 575 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 576 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 577 PIIX_SIDETIM_RTC_MASK(channel)); 578 idedma_ctl = 0; 579 580 /* set up new idetim: Enable IDE registers decode */ 581 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 582 583 /* setup DMA if needed */ 584 pciide_channel_dma_setup(cp); 585 586 for (drive = 0; drive < 2; drive++) { 587 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 588 PIIX_UDMATIM_SET(0x3, channel, drive)); 589 drvp = &chp->ch_drive[drive]; 590 /* If no drive, skip */ 591 if ((drvp->drive_flags & DRIVE) == 0) 592 continue; 593 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 594 (drvp->drive_flags & DRIVE_UDMA) == 0)) 595 goto pio; 596 597 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 598 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 599 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 600 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 601 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 602 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 603 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 604 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 605 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 606 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 607 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 608 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 609 ideconf |= PIIX_CONFIG_PINGPONG; 610 } 611 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 612 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 613 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 614 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 615 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 616 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 617 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 618 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 619 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 620 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 621 /* setup Ultra/100 */ 622 if (drvp->UDMA_mode > 2 && 623 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 624 drvp->UDMA_mode = 2; 625 if (drvp->UDMA_mode > 4) { 626 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 627 } else { 628 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 629 if (drvp->UDMA_mode > 2) { 630 ideconf |= PIIX_CONFIG_UDMA66(channel, 631 drive); 632 } else { 633 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 634 drive); 635 } 636 } 637 } 638 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 639 /* setup Ultra/66 */ 640 if (drvp->UDMA_mode > 2 && 641 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 642 drvp->UDMA_mode = 2; 643 if (drvp->UDMA_mode > 2) 644 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 645 else 646 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 647 } 648 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 649 (drvp->drive_flags & DRIVE_UDMA)) { 650 /* use Ultra/DMA */ 651 s = splbio(); 652 drvp->drive_flags &= ~DRIVE_DMA; 653 splx(s); 654 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 655 udmareg |= PIIX_UDMATIM_SET( 656 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 657 } else { 658 /* use Multiword DMA */ 659 s = splbio(); 660 drvp->drive_flags &= ~DRIVE_UDMA; 661 splx(s); 662 if (drive == 0) { 663 idetim |= piix_setup_idetim_timings( 664 drvp->DMA_mode, 1, channel); 665 } else { 666 sidetim |= piix_setup_sidetim_timings( 667 drvp->DMA_mode, 1, channel); 668 idetim =PIIX_IDETIM_SET(idetim, 669 PIIX_IDETIM_SITRE, channel); 670 } 671 } 672 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 673 674 pio: /* use PIO mode */ 675 idetim |= piix_setup_idetim_drvs(drvp); 676 if (drive == 0) { 677 idetim |= piix_setup_idetim_timings( 678 drvp->PIO_mode, 0, channel); 679 } else { 680 sidetim |= piix_setup_sidetim_timings( 681 drvp->PIO_mode, 0, channel); 682 idetim =PIIX_IDETIM_SET(idetim, 683 PIIX_IDETIM_SITRE, channel); 684 } 685 } 686 if (idedma_ctl != 0) { 687 /* Add software bits in status register */ 688 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 689 idedma_ctl); 690 } 691 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 692 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 693 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 694 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 695 } 696 697 698 /* setup ISP and RTC fields, based on mode */ 699 static u_int32_t 700 piix_setup_idetim_timings(mode, dma, channel) 701 u_int8_t mode; 702 u_int8_t dma; 703 u_int8_t channel; 704 { 705 706 if (dma) 707 return PIIX_IDETIM_SET(0, 708 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 709 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 710 channel); 711 else 712 return PIIX_IDETIM_SET(0, 713 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 714 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 715 channel); 716 } 717 718 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 719 static u_int32_t 720 piix_setup_idetim_drvs(drvp) 721 struct ata_drive_datas *drvp; 722 { 723 u_int32_t ret = 0; 724 struct ata_channel *chp = drvp->chnl_softc; 725 u_int8_t channel = chp->ch_channel; 726 u_int8_t drive = drvp->drive; 727 728 /* 729 * If drive is using UDMA, timings setups are independent 730 * So just check DMA and PIO here. 731 */ 732 if (drvp->drive_flags & DRIVE_DMA) { 733 /* if mode = DMA mode 0, use compatible timings */ 734 if ((drvp->drive_flags & DRIVE_DMA) && 735 drvp->DMA_mode == 0) { 736 drvp->PIO_mode = 0; 737 return ret; 738 } 739 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 740 /* 741 * PIO and DMA timings are the same, use fast timings for PIO 742 * too, else use compat timings. 743 */ 744 if ((piix_isp_pio[drvp->PIO_mode] != 745 piix_isp_dma[drvp->DMA_mode]) || 746 (piix_rtc_pio[drvp->PIO_mode] != 747 piix_rtc_dma[drvp->DMA_mode])) 748 drvp->PIO_mode = 0; 749 /* if PIO mode <= 2, use compat timings for PIO */ 750 if (drvp->PIO_mode <= 2) { 751 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 752 channel); 753 return ret; 754 } 755 } 756 757 /* 758 * Now setup PIO modes. If mode < 2, use compat timings. 759 * Else enable fast timings. Enable IORDY and prefetch/post 760 * if PIO mode >= 3. 761 */ 762 763 if (drvp->PIO_mode < 2) 764 return ret; 765 766 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 767 if (drvp->PIO_mode >= 3) { 768 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 769 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 770 } 771 return ret; 772 } 773 774 /* setup values in SIDETIM registers, based on mode */ 775 static u_int32_t 776 piix_setup_sidetim_timings(mode, dma, channel) 777 u_int8_t mode; 778 u_int8_t dma; 779 u_int8_t channel; 780 { 781 if (dma) 782 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 783 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 784 else 785 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 786 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 787 } 788 789 static void 790 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 791 { 792 struct pciide_channel *cp; 793 bus_size_t cmdsize, ctlsize; 794 pcireg_t interface, cmdsts; 795 int channel; 796 797 if (pciide_chipen(sc, pa) == 0) 798 return; 799 800 aprint_normal("%s: bus-master DMA support present", 801 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 802 pciide_mapreg_dma(sc, pa); 803 aprint_normal("\n"); 804 805 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 806 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 807 if (sc->sc_dma_ok) { 808 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 809 sc->sc_wdcdev.irqack = pciide_irqack; 810 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 811 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 812 } 813 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 814 815 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 816 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 817 818 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 819 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 820 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 821 822 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 823 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 824 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 825 826 interface = PCI_INTERFACE(pa->pa_class); 827 828 wdc_allocate_regs(&sc->sc_wdcdev); 829 830 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 831 channel++) { 832 cp = &sc->pciide_channels[channel]; 833 if (pciide_chansetup(sc, channel, interface) == 0) 834 continue; 835 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 836 pciide_pci_intr); 837 } 838 } 839
Indexes created Fri Oct 17 09:09:57 GMT 2025