piixide.c revision 1.3
1 /* $NetBSD: piixide.c,v 1.3 2003/11/27 23:02:40 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct channel_softc *); 43 static void piix3_4_setup_channel(struct channel_softc *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static int piixide_match(struct device *, struct cfdata *, void *); 50 static void piixide_attach(struct device *, struct device *, void *); 51 52 static const struct pciide_product_desc pciide_intel_products[] = { 53 { PCI_PRODUCT_INTEL_82092AA, 54 0, 55 "Intel 82092AA IDE controller", 56 default_chip_map, 57 }, 58 { PCI_PRODUCT_INTEL_82371FB_IDE, 59 0, 60 "Intel 82371FB IDE controller (PIIX)", 61 piix_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371SB_IDE, 64 0, 65 "Intel 82371SB IDE Interface (PIIX3)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371AB_IDE, 69 0, 70 "Intel 82371AB IDE controller (PIIX4)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82440MX_IDE, 74 0, 75 "Intel 82440MX IDE controller", 76 piix_chip_map 77 }, 78 { PCI_PRODUCT_INTEL_82801AA_IDE, 79 0, 80 "Intel 82801AA IDE Controller (ICH)", 81 piix_chip_map, 82 }, 83 { PCI_PRODUCT_INTEL_82801AB_IDE, 84 0, 85 "Intel 82801AB IDE Controller (ICH0)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801BA_IDE, 89 0, 90 "Intel 82801BA IDE Controller (ICH2)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 0, 95 "Intel 82801BAM IDE Controller (ICH2-M)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 0, 100 "Intel 82801CA IDE Controller (ICH3)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801DB_IDE, 109 0, 110 "Intel 82801DB IDE Controller (ICH4)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 0, 115 "Intel 82801DBM IDE Controller (ICH4-M)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801EB_IDE, 119 0, 120 "Intel 82801EB IDE Controller (ICH5)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_31244, 124 0, 125 "Intel 31244 Serial ATA Controller", 126 artisea_chip_map, 127 }, 128 /* 129 * XXX Is this really the same as the 31244? --thorpej 130 */ 131 { PCI_PRODUCT_INTEL_82801EB_SATA, 132 0, 133 "Intel 82801EB Serial ATA Controller", 134 artisea_chip_map, 135 }, 136 { 0, 137 0, 138 NULL, 139 NULL 140 } 141 }; 142 143 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 144 piixide_match, piixide_attach, NULL, NULL); 145 146 static int 147 piixide_match(struct device *parent, struct cfdata *match, void *aux) 148 { 149 struct pci_attach_args *pa = aux; 150 151 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 152 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 153 return (2); 154 } 155 return (0); 156 } 157 158 static void 159 piixide_attach(struct device *parent, struct device *self, void *aux) 160 { 161 struct pci_attach_args *pa = aux; 162 struct pciide_softc *sc = (struct pciide_softc *)self; 163 164 pciide_common_attach(sc, pa, 165 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 166 167 } 168 169 static void 170 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 171 { 172 struct pciide_channel *cp; 173 int channel; 174 u_int32_t idetim; 175 bus_size_t cmdsize, ctlsize; 176 177 if (pciide_chipen(sc, pa) == 0) 178 return; 179 180 aprint_normal("%s: bus-master DMA support present", 181 sc->sc_wdcdev.sc_dev.dv_xname); 182 pciide_mapreg_dma(sc, pa); 183 aprint_normal("\n"); 184 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 185 WDC_CAPABILITY_MODE; 186 if (sc->sc_dma_ok) { 187 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 188 sc->sc_wdcdev.irqack = pciide_irqack; 189 switch(sc->sc_pp->ide_product) { 190 case PCI_PRODUCT_INTEL_82371AB_IDE: 191 case PCI_PRODUCT_INTEL_82440MX_IDE: 192 case PCI_PRODUCT_INTEL_82801AA_IDE: 193 case PCI_PRODUCT_INTEL_82801AB_IDE: 194 case PCI_PRODUCT_INTEL_82801BA_IDE: 195 case PCI_PRODUCT_INTEL_82801BAM_IDE: 196 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 197 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 198 case PCI_PRODUCT_INTEL_82801DB_IDE: 199 case PCI_PRODUCT_INTEL_82801DBM_IDE: 200 case PCI_PRODUCT_INTEL_82801EB_IDE: 201 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 202 } 203 } 204 sc->sc_wdcdev.PIO_cap = 4; 205 sc->sc_wdcdev.DMA_cap = 2; 206 switch(sc->sc_pp->ide_product) { 207 case PCI_PRODUCT_INTEL_82801AA_IDE: 208 sc->sc_wdcdev.UDMA_cap = 4; 209 break; 210 case PCI_PRODUCT_INTEL_82801BA_IDE: 211 case PCI_PRODUCT_INTEL_82801BAM_IDE: 212 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 213 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 214 case PCI_PRODUCT_INTEL_82801DB_IDE: 215 case PCI_PRODUCT_INTEL_82801DBM_IDE: 216 case PCI_PRODUCT_INTEL_82801EB_IDE: 217 sc->sc_wdcdev.UDMA_cap = 5; 218 break; 219 default: 220 sc->sc_wdcdev.UDMA_cap = 2; 221 } 222 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 223 sc->sc_wdcdev.set_modes = piix_setup_channel; 224 else 225 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 226 sc->sc_wdcdev.channels = sc->wdc_chanarray; 227 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 228 229 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 230 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 231 DEBUG_PROBE); 232 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 233 WDCDEBUG_PRINT((", sidetim=0x%x", 234 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 235 DEBUG_PROBE); 236 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 237 WDCDEBUG_PRINT((", udamreg 0x%x", 238 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 239 DEBUG_PROBE); 240 } 241 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 242 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 243 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 244 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 245 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 246 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 247 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 248 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 249 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ) { 250 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 251 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 252 DEBUG_PROBE); 253 } 254 255 } 256 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 257 258 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 259 cp = &sc->pciide_channels[channel]; 260 /* PIIX is compat-only */ 261 if (pciide_chansetup(sc, channel, 0) == 0) 262 continue; 263 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 264 if ((PIIX_IDETIM_READ(idetim, channel) & 265 PIIX_IDETIM_IDE) == 0) { 266 #if 1 267 aprint_normal("%s: %s channel ignored (disabled)\n", 268 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 269 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 270 continue; 271 #else 272 pcireg_t interface; 273 274 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 275 channel); 276 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 277 idetim); 278 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 279 sc->sc_tag, PCI_CLASS_REG)); 280 aprint_normal("channel %d idetim=%08x interface=%02x\n", 281 channel, idetim, interface); 282 #endif 283 } 284 /* PIIX are compat-only pciide devices */ 285 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 286 } 287 288 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 289 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 290 DEBUG_PROBE); 291 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 292 WDCDEBUG_PRINT((", sidetim=0x%x", 293 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 294 DEBUG_PROBE); 295 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 296 WDCDEBUG_PRINT((", udamreg 0x%x", 297 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 298 DEBUG_PROBE); 299 } 300 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 301 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 302 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 303 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 304 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 305 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 306 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 307 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 308 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 309 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 310 DEBUG_PROBE); 311 } 312 } 313 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 314 } 315 316 static void 317 piix_setup_channel(struct channel_softc *chp) 318 { 319 u_int8_t mode[2], drive; 320 u_int32_t oidetim, idetim, idedma_ctl; 321 struct pciide_channel *cp = (struct pciide_channel*)chp; 322 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 323 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 324 325 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 326 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 327 idedma_ctl = 0; 328 329 /* set up new idetim: Enable IDE registers decode */ 330 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 331 chp->channel); 332 333 /* setup DMA */ 334 pciide_channel_dma_setup(cp); 335 336 /* 337 * Here we have to mess up with drives mode: PIIX can't have 338 * different timings for master and slave drives. 339 * We need to find the best combination. 340 */ 341 342 /* If both drives supports DMA, take the lower mode */ 343 if ((drvp[0].drive_flags & DRIVE_DMA) && 344 (drvp[1].drive_flags & DRIVE_DMA)) { 345 mode[0] = mode[1] = 346 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 347 drvp[0].DMA_mode = mode[0]; 348 drvp[1].DMA_mode = mode[1]; 349 goto ok; 350 } 351 /* 352 * If only one drive supports DMA, use its mode, and 353 * put the other one in PIO mode 0 if mode not compatible 354 */ 355 if (drvp[0].drive_flags & DRIVE_DMA) { 356 mode[0] = drvp[0].DMA_mode; 357 mode[1] = drvp[1].PIO_mode; 358 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 359 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 360 mode[1] = drvp[1].PIO_mode = 0; 361 goto ok; 362 } 363 if (drvp[1].drive_flags & DRIVE_DMA) { 364 mode[1] = drvp[1].DMA_mode; 365 mode[0] = drvp[0].PIO_mode; 366 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 367 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 368 mode[0] = drvp[0].PIO_mode = 0; 369 goto ok; 370 } 371 /* 372 * If both drives are not DMA, takes the lower mode, unless 373 * one of them is PIO mode < 2 374 */ 375 if (drvp[0].PIO_mode < 2) { 376 mode[0] = drvp[0].PIO_mode = 0; 377 mode[1] = drvp[1].PIO_mode; 378 } else if (drvp[1].PIO_mode < 2) { 379 mode[1] = drvp[1].PIO_mode = 0; 380 mode[0] = drvp[0].PIO_mode; 381 } else { 382 mode[0] = mode[1] = 383 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 384 drvp[0].PIO_mode = mode[0]; 385 drvp[1].PIO_mode = mode[1]; 386 } 387 ok: /* The modes are setup */ 388 for (drive = 0; drive < 2; drive++) { 389 if (drvp[drive].drive_flags & DRIVE_DMA) { 390 idetim |= piix_setup_idetim_timings( 391 mode[drive], 1, chp->channel); 392 goto end; 393 } 394 } 395 /* If we are there, none of the drives are DMA */ 396 if (mode[0] >= 2) 397 idetim |= piix_setup_idetim_timings( 398 mode[0], 0, chp->channel); 399 else 400 idetim |= piix_setup_idetim_timings( 401 mode[1], 0, chp->channel); 402 end: /* 403 * timing mode is now set up in the controller. Enable 404 * it per-drive 405 */ 406 for (drive = 0; drive < 2; drive++) { 407 /* If no drive, skip */ 408 if ((drvp[drive].drive_flags & DRIVE) == 0) 409 continue; 410 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 411 if (drvp[drive].drive_flags & DRIVE_DMA) 412 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 413 } 414 if (idedma_ctl != 0) { 415 /* Add software bits in status register */ 416 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 417 idedma_ctl); 418 } 419 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 420 } 421 422 static void 423 piix3_4_setup_channel(struct channel_softc *chp) 424 { 425 struct ata_drive_datas *drvp; 426 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 427 struct pciide_channel *cp = (struct pciide_channel*)chp; 428 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 429 int drive; 430 int channel = chp->channel; 431 432 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 433 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 434 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 435 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 436 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 437 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 438 PIIX_SIDETIM_RTC_MASK(channel)); 439 idedma_ctl = 0; 440 441 /* set up new idetim: Enable IDE registers decode */ 442 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 443 444 /* setup DMA if needed */ 445 pciide_channel_dma_setup(cp); 446 447 for (drive = 0; drive < 2; drive++) { 448 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 449 PIIX_UDMATIM_SET(0x3, channel, drive)); 450 drvp = &chp->ch_drive[drive]; 451 /* If no drive, skip */ 452 if ((drvp->drive_flags & DRIVE) == 0) 453 continue; 454 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 455 (drvp->drive_flags & DRIVE_UDMA) == 0)) 456 goto pio; 457 458 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 459 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 460 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 461 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 462 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 467 ideconf |= PIIX_CONFIG_PINGPONG; 468 } 469 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 472 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 473 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 474 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 475 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 476 /* setup Ultra/100 */ 477 if (drvp->UDMA_mode > 2 && 478 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 479 drvp->UDMA_mode = 2; 480 if (drvp->UDMA_mode > 4) { 481 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 482 } else { 483 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 484 if (drvp->UDMA_mode > 2) { 485 ideconf |= PIIX_CONFIG_UDMA66(channel, 486 drive); 487 } else { 488 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 489 drive); 490 } 491 } 492 } 493 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 494 /* setup Ultra/66 */ 495 if (drvp->UDMA_mode > 2 && 496 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 497 drvp->UDMA_mode = 2; 498 if (drvp->UDMA_mode > 2) 499 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 500 else 501 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 502 } 503 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 504 (drvp->drive_flags & DRIVE_UDMA)) { 505 /* use Ultra/DMA */ 506 drvp->drive_flags &= ~DRIVE_DMA; 507 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 508 udmareg |= PIIX_UDMATIM_SET( 509 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 510 } else { 511 /* use Multiword DMA */ 512 drvp->drive_flags &= ~DRIVE_UDMA; 513 if (drive == 0) { 514 idetim |= piix_setup_idetim_timings( 515 drvp->DMA_mode, 1, channel); 516 } else { 517 sidetim |= piix_setup_sidetim_timings( 518 drvp->DMA_mode, 1, channel); 519 idetim =PIIX_IDETIM_SET(idetim, 520 PIIX_IDETIM_SITRE, channel); 521 } 522 } 523 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 524 525 pio: /* use PIO mode */ 526 idetim |= piix_setup_idetim_drvs(drvp); 527 if (drive == 0) { 528 idetim |= piix_setup_idetim_timings( 529 drvp->PIO_mode, 0, channel); 530 } else { 531 sidetim |= piix_setup_sidetim_timings( 532 drvp->PIO_mode, 0, channel); 533 idetim =PIIX_IDETIM_SET(idetim, 534 PIIX_IDETIM_SITRE, channel); 535 } 536 } 537 if (idedma_ctl != 0) { 538 /* Add software bits in status register */ 539 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 540 idedma_ctl); 541 } 542 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 543 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 544 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 545 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 546 } 547 548 549 /* setup ISP and RTC fields, based on mode */ 550 static u_int32_t 551 piix_setup_idetim_timings(mode, dma, channel) 552 u_int8_t mode; 553 u_int8_t dma; 554 u_int8_t channel; 555 { 556 557 if (dma) 558 return PIIX_IDETIM_SET(0, 559 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 560 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 561 channel); 562 else 563 return PIIX_IDETIM_SET(0, 564 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 565 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 566 channel); 567 } 568 569 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 570 static u_int32_t 571 piix_setup_idetim_drvs(drvp) 572 struct ata_drive_datas *drvp; 573 { 574 u_int32_t ret = 0; 575 struct channel_softc *chp = drvp->chnl_softc; 576 u_int8_t channel = chp->channel; 577 u_int8_t drive = drvp->drive; 578 579 /* 580 * If drive is using UDMA, timings setups are independant 581 * So just check DMA and PIO here. 582 */ 583 if (drvp->drive_flags & DRIVE_DMA) { 584 /* if mode = DMA mode 0, use compatible timings */ 585 if ((drvp->drive_flags & DRIVE_DMA) && 586 drvp->DMA_mode == 0) { 587 drvp->PIO_mode = 0; 588 return ret; 589 } 590 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 591 /* 592 * PIO and DMA timings are the same, use fast timings for PIO 593 * too, else use compat timings. 594 */ 595 if ((piix_isp_pio[drvp->PIO_mode] != 596 piix_isp_dma[drvp->DMA_mode]) || 597 (piix_rtc_pio[drvp->PIO_mode] != 598 piix_rtc_dma[drvp->DMA_mode])) 599 drvp->PIO_mode = 0; 600 /* if PIO mode <= 2, use compat timings for PIO */ 601 if (drvp->PIO_mode <= 2) { 602 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 603 channel); 604 return ret; 605 } 606 } 607 608 /* 609 * Now setup PIO modes. If mode < 2, use compat timings. 610 * Else enable fast timings. Enable IORDY and prefetch/post 611 * if PIO mode >= 3. 612 */ 613 614 if (drvp->PIO_mode < 2) 615 return ret; 616 617 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 618 if (drvp->PIO_mode >= 3) { 619 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 620 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 621 } 622 return ret; 623 } 624 625 /* setup values in SIDETIM registers, based on mode */ 626 static u_int32_t 627 piix_setup_sidetim_timings(mode, dma, channel) 628 u_int8_t mode; 629 u_int8_t dma; 630 u_int8_t channel; 631 { 632 if (dma) 633 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 634 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 635 else 636 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 637 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 638 } 639 640 static void 641 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 642 { 643 struct pciide_channel *cp; 644 bus_size_t cmdsize, ctlsize; 645 pcireg_t interface; 646 int channel; 647 648 if (pciide_chipen(sc, pa) == 0) 649 return; 650 651 aprint_normal("%s: bus-master DMA support present", 652 sc->sc_wdcdev.sc_dev.dv_xname); 653 #ifndef PCIIDE_I31244_ENABLEDMA 654 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 655 PCI_REVISION(pa->pa_class) == 0) { 656 aprint_normal(" but disabled due to rev. 0"); 657 sc->sc_dma_ok = 0; 658 } else 659 #endif 660 pciide_mapreg_dma(sc, pa); 661 aprint_normal("\n"); 662 663 /* 664 * XXX Configure LEDs to show activity. 665 */ 666 667 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 668 WDC_CAPABILITY_MODE; 669 sc->sc_wdcdev.PIO_cap = 4; 670 if (sc->sc_dma_ok) { 671 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 672 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 673 sc->sc_wdcdev.irqack = pciide_irqack; 674 sc->sc_wdcdev.DMA_cap = 2; 675 sc->sc_wdcdev.UDMA_cap = 6; 676 } 677 sc->sc_wdcdev.set_modes = sata_setup_channel; 678 679 sc->sc_wdcdev.channels = sc->wdc_chanarray; 680 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 681 682 interface = PCI_INTERFACE(pa->pa_class); 683 684 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 685 cp = &sc->pciide_channels[channel]; 686 if (pciide_chansetup(sc, channel, interface) == 0) 687 continue; 688 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 689 pciide_pci_intr); 690 } 691 } 692
Indexes created Fri Sep 26 20:09:58 GMT 2025