piixide.c revision 1.30
1 /* $NetBSD: piixide.c,v 1.30 2006/09/24 03:53:09 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.30 2006/09/24 03:53:09 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 52 static void piixide_powerhook(int, void *); 53 static int piixide_match(struct device *, struct cfdata *, void *); 54 static void piixide_attach(struct device *, struct device *, void *); 55 56 static const struct pciide_product_desc pciide_intel_products[] = { 57 { PCI_PRODUCT_INTEL_82092AA, 58 0, 59 "Intel 82092AA IDE controller", 60 default_chip_map, 61 }, 62 { PCI_PRODUCT_INTEL_82371FB_IDE, 63 0, 64 "Intel 82371FB IDE controller (PIIX)", 65 piix_chip_map, 66 }, 67 { PCI_PRODUCT_INTEL_82371SB_IDE, 68 0, 69 "Intel 82371SB IDE Interface (PIIX3)", 70 piix_chip_map, 71 }, 72 { PCI_PRODUCT_INTEL_82371AB_IDE, 73 0, 74 "Intel 82371AB IDE controller (PIIX4)", 75 piix_chip_map, 76 }, 77 { PCI_PRODUCT_INTEL_82440MX_IDE, 78 0, 79 "Intel 82440MX IDE controller", 80 piix_chip_map 81 }, 82 { PCI_PRODUCT_INTEL_82801AA_IDE, 83 0, 84 "Intel 82801AA IDE Controller (ICH)", 85 piix_chip_map, 86 }, 87 { PCI_PRODUCT_INTEL_82801AB_IDE, 88 0, 89 "Intel 82801AB IDE Controller (ICH0)", 90 piix_chip_map, 91 }, 92 { PCI_PRODUCT_INTEL_82801BA_IDE, 93 0, 94 "Intel 82801BA IDE Controller (ICH2)", 95 piix_chip_map, 96 }, 97 { PCI_PRODUCT_INTEL_82801BAM_IDE, 98 0, 99 "Intel 82801BAM IDE Controller (ICH2-M)", 100 piix_chip_map, 101 }, 102 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 103 0, 104 "Intel 82801CA IDE Controller (ICH3)", 105 piix_chip_map, 106 }, 107 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 108 0, 109 "Intel 82801CA IDE Controller (ICH3)", 110 piix_chip_map, 111 }, 112 { PCI_PRODUCT_INTEL_82801DB_IDE, 113 0, 114 "Intel 82801DB IDE Controller (ICH4)", 115 piix_chip_map, 116 }, 117 { PCI_PRODUCT_INTEL_82801DBM_IDE, 118 0, 119 "Intel 82801DBM IDE Controller (ICH4-M)", 120 piix_chip_map, 121 }, 122 { PCI_PRODUCT_INTEL_82801EB_IDE, 123 0, 124 "Intel 82801EB IDE Controller (ICH5)", 125 piix_chip_map, 126 }, 127 { PCI_PRODUCT_INTEL_82801EB_SATA, 128 0, 129 "Intel 82801EB Serial ATA Controller", 130 piixsata_chip_map, 131 }, 132 { PCI_PRODUCT_INTEL_82801ER_SATA, 133 0, 134 "Intel 82801ER Serial ATA/Raid Controller", 135 piixsata_chip_map, 136 }, 137 { PCI_PRODUCT_INTEL_6300ESB_IDE, 138 0, 139 "Intel 6300ESB IDE Controller (ICH5)", 140 piix_chip_map, 141 }, 142 { PCI_PRODUCT_INTEL_6300ESB_SATA, 143 0, 144 "Intel 6300ESB Serial ATA Controller", 145 piixsata_chip_map, 146 }, 147 { PCI_PRODUCT_INTEL_6300ESB_RAID, 148 0, 149 "Intel 6300ESB Serial ATA/RAID Controller", 150 piixsata_chip_map, 151 }, 152 { PCI_PRODUCT_INTEL_82801FB_IDE, 153 0, 154 "Intel 82801FB IDE Controller (ICH6)", 155 piix_chip_map, 156 }, 157 { PCI_PRODUCT_INTEL_82801FB_SATA, 158 0, 159 "Intel 82801FB Serial ATA/Raid Controller", 160 piixsata_chip_map, 161 }, 162 { PCI_PRODUCT_INTEL_82801FR_SATA, 163 0, 164 "Intel 82801FR Serial ATA/Raid Controller", 165 piixsata_chip_map, 166 }, 167 { PCI_PRODUCT_INTEL_82801FBM_SATA, 168 0, 169 "Intel 82801FBM Serial ATA Controller (ICH6)", 170 piixsata_chip_map, 171 }, 172 { PCI_PRODUCT_INTEL_82801G_IDE, 173 0, 174 "Intel 82801GB/GR IDE Controller (ICH7)", 175 piix_chip_map, 176 }, 177 { PCI_PRODUCT_INTEL_82801G_SATA, 178 0, 179 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 180 piixsata_chip_map, 181 }, 182 { PCI_PRODUCT_INTEL_82801GBM_SATA, 183 0, 184 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 185 piixsata_chip_map, 186 }, 187 { PCI_PRODUCT_INTEL_82801H_SATA_1, 188 0, 189 "Intel 82801H Serial ATA Controller (ICH8)", 190 piixsata_chip_map, 191 }, 192 { PCI_PRODUCT_INTEL_82801H_SATA_AHCI6, 193 0, 194 "Intel 82801H AHCI Controller (ICH8)", 195 piixsata_chip_map, 196 }, 197 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 198 0, 199 "Intel 82801H Serial ATA RAID Controller (ICH8)", 200 piixsata_chip_map, 201 }, 202 { PCI_PRODUCT_INTEL_82801H_SATA_AHCI4, 203 0, 204 "Intel 82801H Serial ATA Controller (ICH8)", 205 piixsata_chip_map, 206 }, 207 { PCI_PRODUCT_INTEL_82801H_SATA_2, 208 0, 209 "Intel 82801H Serial ATA Controller (ICH8)", 210 piixsata_chip_map, 211 }, 212 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 213 0, 214 "Intel 82801HBM Serial ATA Controller (ICH8M)", 215 piixsata_chip_map, 216 }, 217 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 218 0, 219 "Intel 82801HBM Serial ATA Controller (ICH8M)", 220 piixsata_chip_map, 221 }, 222 { PCI_PRODUCT_INTEL_63XXESB_IDE, 223 0, 224 "Intel 631xESB/632xESB IDE Controller", 225 piix_chip_map, 226 }, 227 { PCI_PRODUCT_INTEL_63XXESB_SATA, 228 0, 229 "Intel 631xESB/632xESB Serial ATA Controller", 230 piixsata_chip_map, 231 }, 232 { 0, 233 0, 234 NULL, 235 NULL 236 } 237 }; 238 239 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 240 piixide_match, piixide_attach, NULL, NULL); 241 242 static int 243 piixide_match(struct device *parent, struct cfdata *match, void *aux) 244 { 245 struct pci_attach_args *pa = aux; 246 247 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 248 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 249 return (2); 250 } 251 return (0); 252 } 253 254 static void 255 piixide_attach(struct device *parent, struct device *self, void *aux) 256 { 257 struct pci_attach_args *pa = aux; 258 struct pciide_softc *sc = (struct pciide_softc *)self; 259 260 pciide_common_attach(sc, pa, 261 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 262 263 /* Setup our powerhook */ 264 sc->sc_powerhook = powerhook_establish( 265 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, piixide_powerhook, sc); 266 if (sc->sc_powerhook == NULL) 267 printf("%s: WARNING: unable to establish PCI power hook\n", 268 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 269 } 270 271 static void 272 piixide_powerhook(int why, void *hdl) 273 { 274 struct pciide_softc *sc = (struct pciide_softc *)hdl; 275 276 switch (why) { 277 case PWR_SUSPEND: 278 case PWR_STANDBY: 279 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 280 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 281 PIIX_IDETIM); 282 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 283 PIIX_UDMATIM); 284 break; 285 case PWR_RESUME: 286 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 287 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 288 sc->sc_idetim); 289 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 290 sc->sc_udmatim); 291 break; 292 case PWR_SOFTSUSPEND: 293 case PWR_SOFTSTANDBY: 294 case PWR_SOFTRESUME: 295 break; 296 } 297 298 return; 299 } 300 301 static void 302 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 303 { 304 struct pciide_channel *cp; 305 int channel; 306 u_int32_t idetim; 307 bus_size_t cmdsize, ctlsize; 308 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 309 310 if (pciide_chipen(sc, pa) == 0) 311 return; 312 313 aprint_normal("%s: bus-master DMA support present", 314 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 315 pciide_mapreg_dma(sc, pa); 316 aprint_normal("\n"); 317 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 318 if (sc->sc_dma_ok) { 319 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 320 sc->sc_wdcdev.irqack = pciide_irqack; 321 switch(sc->sc_pp->ide_product) { 322 case PCI_PRODUCT_INTEL_82371AB_IDE: 323 case PCI_PRODUCT_INTEL_82440MX_IDE: 324 case PCI_PRODUCT_INTEL_82801AA_IDE: 325 case PCI_PRODUCT_INTEL_82801AB_IDE: 326 case PCI_PRODUCT_INTEL_82801BA_IDE: 327 case PCI_PRODUCT_INTEL_82801BAM_IDE: 328 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 329 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 330 case PCI_PRODUCT_INTEL_82801DB_IDE: 331 case PCI_PRODUCT_INTEL_82801DBM_IDE: 332 case PCI_PRODUCT_INTEL_82801EB_IDE: 333 case PCI_PRODUCT_INTEL_6300ESB_IDE: 334 case PCI_PRODUCT_INTEL_82801FB_IDE: 335 case PCI_PRODUCT_INTEL_82801G_IDE: 336 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 337 } 338 } 339 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 340 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 341 switch(sc->sc_pp->ide_product) { 342 case PCI_PRODUCT_INTEL_82801AA_IDE: 343 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 344 break; 345 case PCI_PRODUCT_INTEL_82801BA_IDE: 346 case PCI_PRODUCT_INTEL_82801BAM_IDE: 347 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 348 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 349 case PCI_PRODUCT_INTEL_82801DB_IDE: 350 case PCI_PRODUCT_INTEL_82801DBM_IDE: 351 case PCI_PRODUCT_INTEL_82801EB_IDE: 352 case PCI_PRODUCT_INTEL_6300ESB_IDE: 353 case PCI_PRODUCT_INTEL_82801FB_IDE: 354 case PCI_PRODUCT_INTEL_82801G_IDE: 355 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 356 break; 357 default: 358 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 359 } 360 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 361 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 362 else 363 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 364 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 365 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 366 367 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 368 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 369 DEBUG_PROBE); 370 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 371 ATADEBUG_PRINT((", sidetim=0x%x", 372 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 373 DEBUG_PROBE); 374 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 375 ATADEBUG_PRINT((", udamreg 0x%x", 376 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 377 DEBUG_PROBE); 378 } 379 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 380 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 381 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 382 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 383 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 384 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 385 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 386 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 387 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 388 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 389 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 390 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 391 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 392 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 393 DEBUG_PROBE); 394 } 395 396 } 397 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 398 399 wdc_allocate_regs(&sc->sc_wdcdev); 400 401 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 402 channel++) { 403 cp = &sc->pciide_channels[channel]; 404 if (pciide_chansetup(sc, channel, interface) == 0) 405 continue; 406 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 407 if ((PIIX_IDETIM_READ(idetim, channel) & 408 PIIX_IDETIM_IDE) == 0) { 409 #if 1 410 aprint_normal("%s: %s channel ignored (disabled)\n", 411 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 412 cp->ata_channel.ch_flags |= ATACH_DISABLED; 413 continue; 414 #else 415 pcireg_t interface; 416 417 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 418 channel); 419 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 420 idetim); 421 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 422 sc->sc_tag, PCI_CLASS_REG)); 423 aprint_normal("channel %d idetim=%08x interface=%02x\n", 424 channel, idetim, interface); 425 #endif 426 } 427 pciide_mapchan(pa, cp, interface, 428 &cmdsize, &ctlsize, pciide_pci_intr); 429 } 430 431 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 432 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 433 DEBUG_PROBE); 434 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 435 ATADEBUG_PRINT((", sidetim=0x%x", 436 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 437 DEBUG_PROBE); 438 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 439 ATADEBUG_PRINT((", udamreg 0x%x", 440 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 441 DEBUG_PROBE); 442 } 443 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 444 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 445 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 446 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 447 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 448 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 449 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 450 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 451 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 452 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 453 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 454 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 455 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 456 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 457 DEBUG_PROBE); 458 } 459 } 460 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 461 } 462 463 static void 464 piix_setup_channel(struct ata_channel *chp) 465 { 466 u_int8_t mode[2], drive; 467 u_int32_t oidetim, idetim, idedma_ctl; 468 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 469 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 470 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 471 472 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 473 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 474 idedma_ctl = 0; 475 476 /* set up new idetim: Enable IDE registers decode */ 477 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 478 chp->ch_channel); 479 480 /* setup DMA */ 481 pciide_channel_dma_setup(cp); 482 483 /* 484 * Here we have to mess up with drives mode: PIIX can't have 485 * different timings for master and slave drives. 486 * We need to find the best combination. 487 */ 488 489 /* If both drives supports DMA, take the lower mode */ 490 if ((drvp[0].drive_flags & DRIVE_DMA) && 491 (drvp[1].drive_flags & DRIVE_DMA)) { 492 mode[0] = mode[1] = 493 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 494 drvp[0].DMA_mode = mode[0]; 495 drvp[1].DMA_mode = mode[1]; 496 goto ok; 497 } 498 /* 499 * If only one drive supports DMA, use its mode, and 500 * put the other one in PIO mode 0 if mode not compatible 501 */ 502 if (drvp[0].drive_flags & DRIVE_DMA) { 503 mode[0] = drvp[0].DMA_mode; 504 mode[1] = drvp[1].PIO_mode; 505 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 506 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 507 mode[1] = drvp[1].PIO_mode = 0; 508 goto ok; 509 } 510 if (drvp[1].drive_flags & DRIVE_DMA) { 511 mode[1] = drvp[1].DMA_mode; 512 mode[0] = drvp[0].PIO_mode; 513 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 514 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 515 mode[0] = drvp[0].PIO_mode = 0; 516 goto ok; 517 } 518 /* 519 * If both drives are not DMA, takes the lower mode, unless 520 * one of them is PIO mode < 2 521 */ 522 if (drvp[0].PIO_mode < 2) { 523 mode[0] = drvp[0].PIO_mode = 0; 524 mode[1] = drvp[1].PIO_mode; 525 } else if (drvp[1].PIO_mode < 2) { 526 mode[1] = drvp[1].PIO_mode = 0; 527 mode[0] = drvp[0].PIO_mode; 528 } else { 529 mode[0] = mode[1] = 530 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 531 drvp[0].PIO_mode = mode[0]; 532 drvp[1].PIO_mode = mode[1]; 533 } 534 ok: /* The modes are setup */ 535 for (drive = 0; drive < 2; drive++) { 536 if (drvp[drive].drive_flags & DRIVE_DMA) { 537 idetim |= piix_setup_idetim_timings( 538 mode[drive], 1, chp->ch_channel); 539 goto end; 540 } 541 } 542 /* If we are there, none of the drives are DMA */ 543 if (mode[0] >= 2) 544 idetim |= piix_setup_idetim_timings( 545 mode[0], 0, chp->ch_channel); 546 else 547 idetim |= piix_setup_idetim_timings( 548 mode[1], 0, chp->ch_channel); 549 end: /* 550 * timing mode is now set up in the controller. Enable 551 * it per-drive 552 */ 553 for (drive = 0; drive < 2; drive++) { 554 /* If no drive, skip */ 555 if ((drvp[drive].drive_flags & DRIVE) == 0) 556 continue; 557 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 558 if (drvp[drive].drive_flags & DRIVE_DMA) 559 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 560 } 561 if (idedma_ctl != 0) { 562 /* Add software bits in status register */ 563 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 564 idedma_ctl); 565 } 566 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 567 } 568 569 static void 570 piix3_4_setup_channel(struct ata_channel *chp) 571 { 572 struct ata_drive_datas *drvp; 573 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 574 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 575 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 576 struct wdc_softc *wdc = &sc->sc_wdcdev; 577 int drive, s; 578 int channel = chp->ch_channel; 579 580 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 581 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 582 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 583 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 584 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 585 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 586 PIIX_SIDETIM_RTC_MASK(channel)); 587 idedma_ctl = 0; 588 589 /* set up new idetim: Enable IDE registers decode */ 590 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 591 592 /* setup DMA if needed */ 593 pciide_channel_dma_setup(cp); 594 595 for (drive = 0; drive < 2; drive++) { 596 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 597 PIIX_UDMATIM_SET(0x3, channel, drive)); 598 drvp = &chp->ch_drive[drive]; 599 /* If no drive, skip */ 600 if ((drvp->drive_flags & DRIVE) == 0) 601 continue; 602 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 603 (drvp->drive_flags & DRIVE_UDMA) == 0)) 604 goto pio; 605 606 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 607 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 608 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 609 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 610 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 611 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 612 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 613 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 614 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 615 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 616 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 617 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 618 ideconf |= PIIX_CONFIG_PINGPONG; 619 } 620 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 621 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 622 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 623 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 624 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 625 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 626 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 630 /* setup Ultra/100 */ 631 if (drvp->UDMA_mode > 2 && 632 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 633 drvp->UDMA_mode = 2; 634 if (drvp->UDMA_mode > 4) { 635 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 636 } else { 637 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 638 if (drvp->UDMA_mode > 2) { 639 ideconf |= PIIX_CONFIG_UDMA66(channel, 640 drive); 641 } else { 642 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 643 drive); 644 } 645 } 646 } 647 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 648 /* setup Ultra/66 */ 649 if (drvp->UDMA_mode > 2 && 650 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 651 drvp->UDMA_mode = 2; 652 if (drvp->UDMA_mode > 2) 653 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 654 else 655 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 656 } 657 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 658 (drvp->drive_flags & DRIVE_UDMA)) { 659 /* use Ultra/DMA */ 660 s = splbio(); 661 drvp->drive_flags &= ~DRIVE_DMA; 662 splx(s); 663 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 664 udmareg |= PIIX_UDMATIM_SET( 665 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 666 } else { 667 /* use Multiword DMA */ 668 s = splbio(); 669 drvp->drive_flags &= ~DRIVE_UDMA; 670 splx(s); 671 if (drive == 0) { 672 idetim |= piix_setup_idetim_timings( 673 drvp->DMA_mode, 1, channel); 674 } else { 675 sidetim |= piix_setup_sidetim_timings( 676 drvp->DMA_mode, 1, channel); 677 idetim =PIIX_IDETIM_SET(idetim, 678 PIIX_IDETIM_SITRE, channel); 679 } 680 } 681 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 682 683 pio: /* use PIO mode */ 684 idetim |= piix_setup_idetim_drvs(drvp); 685 if (drive == 0) { 686 idetim |= piix_setup_idetim_timings( 687 drvp->PIO_mode, 0, channel); 688 } else { 689 sidetim |= piix_setup_sidetim_timings( 690 drvp->PIO_mode, 0, channel); 691 idetim =PIIX_IDETIM_SET(idetim, 692 PIIX_IDETIM_SITRE, channel); 693 } 694 } 695 if (idedma_ctl != 0) { 696 /* Add software bits in status register */ 697 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 698 idedma_ctl); 699 } 700 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 701 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 702 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 703 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 704 } 705 706 707 /* setup ISP and RTC fields, based on mode */ 708 static u_int32_t 709 piix_setup_idetim_timings(mode, dma, channel) 710 u_int8_t mode; 711 u_int8_t dma; 712 u_int8_t channel; 713 { 714 715 if (dma) 716 return PIIX_IDETIM_SET(0, 717 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 718 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 719 channel); 720 else 721 return PIIX_IDETIM_SET(0, 722 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 723 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 724 channel); 725 } 726 727 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 728 static u_int32_t 729 piix_setup_idetim_drvs(drvp) 730 struct ata_drive_datas *drvp; 731 { 732 u_int32_t ret = 0; 733 struct ata_channel *chp = drvp->chnl_softc; 734 u_int8_t channel = chp->ch_channel; 735 u_int8_t drive = drvp->drive; 736 737 /* 738 * If drive is using UDMA, timings setups are independant 739 * So just check DMA and PIO here. 740 */ 741 if (drvp->drive_flags & DRIVE_DMA) { 742 /* if mode = DMA mode 0, use compatible timings */ 743 if ((drvp->drive_flags & DRIVE_DMA) && 744 drvp->DMA_mode == 0) { 745 drvp->PIO_mode = 0; 746 return ret; 747 } 748 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 749 /* 750 * PIO and DMA timings are the same, use fast timings for PIO 751 * too, else use compat timings. 752 */ 753 if ((piix_isp_pio[drvp->PIO_mode] != 754 piix_isp_dma[drvp->DMA_mode]) || 755 (piix_rtc_pio[drvp->PIO_mode] != 756 piix_rtc_dma[drvp->DMA_mode])) 757 drvp->PIO_mode = 0; 758 /* if PIO mode <= 2, use compat timings for PIO */ 759 if (drvp->PIO_mode <= 2) { 760 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 761 channel); 762 return ret; 763 } 764 } 765 766 /* 767 * Now setup PIO modes. If mode < 2, use compat timings. 768 * Else enable fast timings. Enable IORDY and prefetch/post 769 * if PIO mode >= 3. 770 */ 771 772 if (drvp->PIO_mode < 2) 773 return ret; 774 775 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 776 if (drvp->PIO_mode >= 3) { 777 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 778 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 779 } 780 return ret; 781 } 782 783 /* setup values in SIDETIM registers, based on mode */ 784 static u_int32_t 785 piix_setup_sidetim_timings(mode, dma, channel) 786 u_int8_t mode; 787 u_int8_t dma; 788 u_int8_t channel; 789 { 790 if (dma) 791 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 792 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 793 else 794 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 795 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 796 } 797 798 static void 799 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 800 { 801 struct pciide_channel *cp; 802 bus_size_t cmdsize, ctlsize; 803 pcireg_t interface, cmdsts; 804 int channel, ich = 0; 805 uint8_t reg; 806 807 if (pciide_chipen(sc, pa) == 0) 808 return; 809 810 aprint_normal("%s: bus-master DMA support present", 811 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 812 pciide_mapreg_dma(sc, pa); 813 aprint_normal("\n"); 814 815 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 816 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 817 if (sc->sc_dma_ok) { 818 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 819 sc->sc_wdcdev.irqack = pciide_irqack; 820 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 821 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 822 } 823 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 824 825 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 826 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 827 828 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 829 cmdsts &= ~0x0400; 830 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 831 832 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 833 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 834 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 835 836 interface = PCI_INTERFACE(pa->pa_class); 837 838 switch (sc->sc_pp->ide_product) { 839 case PCI_PRODUCT_INTEL_6300ESB_SATA: 840 case PCI_PRODUCT_INTEL_6300ESB_RAID: 841 case PCI_PRODUCT_INTEL_63XXESB_SATA: 842 case PCI_PRODUCT_INTEL_82801EB_SATA: 843 case PCI_PRODUCT_INTEL_82801ER_SATA: 844 ich = 5; 845 break; 846 case PCI_PRODUCT_INTEL_82801FB_SATA: 847 case PCI_PRODUCT_INTEL_82801FR_SATA: 848 case PCI_PRODUCT_INTEL_82801FBM_SATA: 849 ich = 6; 850 break; 851 case PCI_PRODUCT_INTEL_82801G_SATA: 852 case PCI_PRODUCT_INTEL_82801G_SATA_AHCI: 853 case PCI_PRODUCT_INTEL_82801G_SATA_RAID: 854 case PCI_PRODUCT_INTEL_82801GBM_SATA: 855 case PCI_PRODUCT_INTEL_82801GBM_AHCI: 856 case PCI_PRODUCT_INTEL_82801GHM_RAID: 857 ich = 7; 858 break; 859 case PCI_PRODUCT_INTEL_82801H_SATA_1: 860 case PCI_PRODUCT_INTEL_82801H_SATA_AHCI6: 861 case PCI_PRODUCT_INTEL_82801H_SATA_RAID: 862 case PCI_PRODUCT_INTEL_82801H_SATA_AHCI4: 863 case PCI_PRODUCT_INTEL_82801H_SATA_2: 864 case PCI_PRODUCT_INTEL_82801HBM_SATA_1: 865 case PCI_PRODUCT_INTEL_82801HBM_SATA_2: 866 ich = 8; 867 break; 868 } 869 870 /* 871 * Put the SATA portion of controllers that don't operate in combined 872 * mode into native PCI modes so the maximum number of devices can be 873 * used. Intel calls this "enhanced mode". 874 */ 875 876 if (ich == 5) { 877 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP); 878 if ((reg & ICH5_SATA_MAP_COMBINED) == 0) { 879 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 880 ICH5_SATA_PI); 881 reg |= ICH5_SATA_PI_PRI_NATIVE | 882 ICH5_SATA_PI_SEC_NATIVE; 883 pciide_pci_write(pa->pa_pc, pa->pa_tag, 884 ICH5_SATA_PI, reg); 885 interface |= PCIIDE_INTERFACE_PCI(0) | 886 PCIIDE_INTERFACE_PCI(1); 887 } 888 } else { 889 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP) & 890 ICH6_SATA_MAP_CMB_MASK; 891 if (reg != ICH6_SATA_MAP_CMB_PRI && 892 reg != ICH6_SATA_MAP_CMB_SEC) { 893 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 894 ICH5_SATA_PI); 895 reg |= ICH5_SATA_PI_PRI_NATIVE | 896 ICH5_SATA_PI_SEC_NATIVE; 897 898 pciide_pci_write(pa->pa_pc, pa->pa_tag, 899 ICH5_SATA_PI, reg); 900 interface |= PCIIDE_INTERFACE_PCI(0) | 901 PCIIDE_INTERFACE_PCI(1); 902 903 /* 904 * Ask for SATA IDE Mode, we don't need to do this 905 * for the combined mode case as combined mode is 906 * only allowed in IDE Mode. 907 */ 908 909 if (ich >= 7) { 910 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, 911 ICH5_SATA_MAP) & ~ICH7_SATA_MAP_SMS_MASK; 912 pciide_pci_write(pa->pa_pc, pa->pa_tag, 913 ICH5_SATA_MAP, reg); 914 } 915 } 916 } 917 918 wdc_allocate_regs(&sc->sc_wdcdev); 919 920 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 921 channel++) { 922 cp = &sc->pciide_channels[channel]; 923 if (pciide_chansetup(sc, channel, interface) == 0) 924 continue; 925 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 926 pciide_pci_intr); 927 } 928 } 929
Indexes created Fri Sep 26 20:09:58 GMT 2025