piixide.c revision 1.33
1 /* $NetBSD: piixide.c,v 1.33 2006/11/16 01:33:10 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.33 2006/11/16 01:33:10 christos Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 52 static void piixide_powerhook(int, void *); 53 static int piixide_match(struct device *, struct cfdata *, void *); 54 static void piixide_attach(struct device *, struct device *, void *); 55 56 static const struct pciide_product_desc pciide_intel_products[] = { 57 { PCI_PRODUCT_INTEL_82092AA, 58 0, 59 "Intel 82092AA IDE controller", 60 default_chip_map, 61 }, 62 { PCI_PRODUCT_INTEL_82371FB_IDE, 63 0, 64 "Intel 82371FB IDE controller (PIIX)", 65 piix_chip_map, 66 }, 67 { PCI_PRODUCT_INTEL_82371SB_IDE, 68 0, 69 "Intel 82371SB IDE Interface (PIIX3)", 70 piix_chip_map, 71 }, 72 { PCI_PRODUCT_INTEL_82371AB_IDE, 73 0, 74 "Intel 82371AB IDE controller (PIIX4)", 75 piix_chip_map, 76 }, 77 { PCI_PRODUCT_INTEL_82440MX_IDE, 78 0, 79 "Intel 82440MX IDE controller", 80 piix_chip_map 81 }, 82 { PCI_PRODUCT_INTEL_82801AA_IDE, 83 0, 84 "Intel 82801AA IDE Controller (ICH)", 85 piix_chip_map, 86 }, 87 { PCI_PRODUCT_INTEL_82801AB_IDE, 88 0, 89 "Intel 82801AB IDE Controller (ICH0)", 90 piix_chip_map, 91 }, 92 { PCI_PRODUCT_INTEL_82801BA_IDE, 93 0, 94 "Intel 82801BA IDE Controller (ICH2)", 95 piix_chip_map, 96 }, 97 { PCI_PRODUCT_INTEL_82801BAM_IDE, 98 0, 99 "Intel 82801BAM IDE Controller (ICH2-M)", 100 piix_chip_map, 101 }, 102 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 103 0, 104 "Intel 82801CA IDE Controller (ICH3)", 105 piix_chip_map, 106 }, 107 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 108 0, 109 "Intel 82801CA IDE Controller (ICH3)", 110 piix_chip_map, 111 }, 112 { PCI_PRODUCT_INTEL_82801DB_IDE, 113 0, 114 "Intel 82801DB IDE Controller (ICH4)", 115 piix_chip_map, 116 }, 117 { PCI_PRODUCT_INTEL_82801DBM_IDE, 118 0, 119 "Intel 82801DBM IDE Controller (ICH4-M)", 120 piix_chip_map, 121 }, 122 { PCI_PRODUCT_INTEL_82801EB_IDE, 123 0, 124 "Intel 82801EB IDE Controller (ICH5)", 125 piix_chip_map, 126 }, 127 { PCI_PRODUCT_INTEL_82801EB_SATA, 128 0, 129 "Intel 82801EB Serial ATA Controller", 130 piixsata_chip_map, 131 }, 132 { PCI_PRODUCT_INTEL_82801ER_SATA, 133 0, 134 "Intel 82801ER Serial ATA/Raid Controller", 135 piixsata_chip_map, 136 }, 137 { PCI_PRODUCT_INTEL_6300ESB_IDE, 138 0, 139 "Intel 6300ESB IDE Controller (ICH5)", 140 piix_chip_map, 141 }, 142 { PCI_PRODUCT_INTEL_6300ESB_SATA, 143 0, 144 "Intel 6300ESB Serial ATA Controller", 145 piixsata_chip_map, 146 }, 147 { PCI_PRODUCT_INTEL_6300ESB_RAID, 148 0, 149 "Intel 6300ESB Serial ATA/RAID Controller", 150 piixsata_chip_map, 151 }, 152 { PCI_PRODUCT_INTEL_82801FB_IDE, 153 0, 154 "Intel 82801FB IDE Controller (ICH6)", 155 piix_chip_map, 156 }, 157 { PCI_PRODUCT_INTEL_82801FB_SATA, 158 0, 159 "Intel 82801FB Serial ATA/Raid Controller", 160 piixsata_chip_map, 161 }, 162 { PCI_PRODUCT_INTEL_82801FR_SATA, 163 0, 164 "Intel 82801FR Serial ATA/Raid Controller", 165 piixsata_chip_map, 166 }, 167 { PCI_PRODUCT_INTEL_82801FBM_SATA, 168 0, 169 "Intel 82801FBM Serial ATA Controller (ICH6)", 170 piixsata_chip_map, 171 }, 172 { PCI_PRODUCT_INTEL_82801G_IDE, 173 0, 174 "Intel 82801GB/GR IDE Controller (ICH7)", 175 piix_chip_map, 176 }, 177 { PCI_PRODUCT_INTEL_82801G_SATA, 178 0, 179 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 180 piixsata_chip_map, 181 }, 182 { PCI_PRODUCT_INTEL_82801GBM_SATA, 183 0, 184 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 185 piixsata_chip_map, 186 }, 187 { PCI_PRODUCT_INTEL_82801H_SATA_1, 188 0, 189 "Intel 82801H Serial ATA Controller (ICH8)", 190 piixsata_chip_map, 191 }, 192 { PCI_PRODUCT_INTEL_82801H_SATA_AHCI6, 193 0, 194 "Intel 82801H AHCI Controller (ICH8)", 195 piixsata_chip_map, 196 }, 197 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 198 0, 199 "Intel 82801H Serial ATA RAID Controller (ICH8)", 200 piixsata_chip_map, 201 }, 202 { PCI_PRODUCT_INTEL_82801H_SATA_AHCI4, 203 0, 204 "Intel 82801H Serial ATA Controller (ICH8)", 205 piixsata_chip_map, 206 }, 207 { PCI_PRODUCT_INTEL_82801H_SATA_2, 208 0, 209 "Intel 82801H Serial ATA Controller (ICH8)", 210 piixsata_chip_map, 211 }, 212 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 213 0, 214 "Intel 82801HBM Serial ATA Controller (ICH8M)", 215 piixsata_chip_map, 216 }, 217 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 218 0, 219 "Intel 82801HBM Serial ATA Controller (ICH8M)", 220 piixsata_chip_map, 221 }, 222 { PCI_PRODUCT_INTEL_63XXESB_IDE, 223 0, 224 "Intel 631xESB/632xESB IDE Controller", 225 piix_chip_map, 226 }, 227 { PCI_PRODUCT_INTEL_63XXESB_SATA, 228 0, 229 "Intel 631xESB/632xESB Serial ATA Controller", 230 piixsata_chip_map, 231 }, 232 { 0, 233 0, 234 NULL, 235 NULL 236 } 237 }; 238 239 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 240 piixide_match, piixide_attach, NULL, NULL); 241 242 static int 243 piixide_match(struct device *parent, struct cfdata *match, 244 void *aux) 245 { 246 struct pci_attach_args *pa = aux; 247 248 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 249 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 250 return (2); 251 } 252 return (0); 253 } 254 255 static void 256 piixide_attach(struct device *parent, struct device *self, void *aux) 257 { 258 struct pci_attach_args *pa = aux; 259 struct pciide_softc *sc = (struct pciide_softc *)self; 260 261 pciide_common_attach(sc, pa, 262 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 263 264 /* Setup our powerhook */ 265 sc->sc_powerhook = powerhook_establish( 266 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, piixide_powerhook, sc); 267 if (sc->sc_powerhook == NULL) 268 printf("%s: WARNING: unable to establish PCI power hook\n", 269 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 270 } 271 272 static void 273 piixide_powerhook(int why, void *hdl) 274 { 275 struct pciide_softc *sc = (struct pciide_softc *)hdl; 276 277 switch (why) { 278 case PWR_SUSPEND: 279 case PWR_STANDBY: 280 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 281 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 282 PIIX_IDETIM); 283 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 284 PIIX_UDMATIM); 285 break; 286 case PWR_RESUME: 287 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 288 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 289 sc->sc_idetim); 290 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 291 sc->sc_udmatim); 292 break; 293 case PWR_SOFTSUSPEND: 294 case PWR_SOFTSTANDBY: 295 case PWR_SOFTRESUME: 296 break; 297 } 298 299 return; 300 } 301 302 static void 303 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 304 { 305 struct pciide_channel *cp; 306 int channel; 307 u_int32_t idetim; 308 bus_size_t cmdsize, ctlsize; 309 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 310 311 if (pciide_chipen(sc, pa) == 0) 312 return; 313 314 aprint_normal("%s: bus-master DMA support present", 315 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 316 pciide_mapreg_dma(sc, pa); 317 aprint_normal("\n"); 318 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 319 if (sc->sc_dma_ok) { 320 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 321 sc->sc_wdcdev.irqack = pciide_irqack; 322 switch(sc->sc_pp->ide_product) { 323 case PCI_PRODUCT_INTEL_82371AB_IDE: 324 case PCI_PRODUCT_INTEL_82440MX_IDE: 325 case PCI_PRODUCT_INTEL_82801AA_IDE: 326 case PCI_PRODUCT_INTEL_82801AB_IDE: 327 case PCI_PRODUCT_INTEL_82801BA_IDE: 328 case PCI_PRODUCT_INTEL_82801BAM_IDE: 329 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 330 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 331 case PCI_PRODUCT_INTEL_82801DB_IDE: 332 case PCI_PRODUCT_INTEL_82801DBM_IDE: 333 case PCI_PRODUCT_INTEL_82801EB_IDE: 334 case PCI_PRODUCT_INTEL_6300ESB_IDE: 335 case PCI_PRODUCT_INTEL_82801FB_IDE: 336 case PCI_PRODUCT_INTEL_82801G_IDE: 337 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 338 } 339 } 340 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 341 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 342 switch(sc->sc_pp->ide_product) { 343 case PCI_PRODUCT_INTEL_82801AA_IDE: 344 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 345 break; 346 case PCI_PRODUCT_INTEL_82801BA_IDE: 347 case PCI_PRODUCT_INTEL_82801BAM_IDE: 348 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 349 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 350 case PCI_PRODUCT_INTEL_82801DB_IDE: 351 case PCI_PRODUCT_INTEL_82801DBM_IDE: 352 case PCI_PRODUCT_INTEL_82801EB_IDE: 353 case PCI_PRODUCT_INTEL_6300ESB_IDE: 354 case PCI_PRODUCT_INTEL_82801FB_IDE: 355 case PCI_PRODUCT_INTEL_82801G_IDE: 356 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 357 break; 358 default: 359 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 360 } 361 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 362 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 363 else 364 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 365 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 366 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 367 368 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 369 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 370 DEBUG_PROBE); 371 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 372 ATADEBUG_PRINT((", sidetim=0x%x", 373 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 374 DEBUG_PROBE); 375 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 376 ATADEBUG_PRINT((", udamreg 0x%x", 377 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 378 DEBUG_PROBE); 379 } 380 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 381 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 382 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 383 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 384 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 385 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 386 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 387 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 388 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 389 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 390 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 391 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 392 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 393 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 394 DEBUG_PROBE); 395 } 396 397 } 398 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 399 400 wdc_allocate_regs(&sc->sc_wdcdev); 401 402 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 403 channel++) { 404 cp = &sc->pciide_channels[channel]; 405 if (pciide_chansetup(sc, channel, interface) == 0) 406 continue; 407 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 408 if ((PIIX_IDETIM_READ(idetim, channel) & 409 PIIX_IDETIM_IDE) == 0) { 410 #if 1 411 aprint_normal("%s: %s channel ignored (disabled)\n", 412 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 413 cp->ata_channel.ch_flags |= ATACH_DISABLED; 414 continue; 415 #else 416 pcireg_t interface; 417 418 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 419 channel); 420 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 421 idetim); 422 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 423 sc->sc_tag, PCI_CLASS_REG)); 424 aprint_normal("channel %d idetim=%08x interface=%02x\n", 425 channel, idetim, interface); 426 #endif 427 } 428 pciide_mapchan(pa, cp, interface, 429 &cmdsize, &ctlsize, pciide_pci_intr); 430 } 431 432 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 433 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 434 DEBUG_PROBE); 435 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 436 ATADEBUG_PRINT((", sidetim=0x%x", 437 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 438 DEBUG_PROBE); 439 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 440 ATADEBUG_PRINT((", udamreg 0x%x", 441 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 442 DEBUG_PROBE); 443 } 444 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 445 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 446 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 447 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 448 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 449 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 450 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 451 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 452 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 453 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 454 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 455 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 456 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 457 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 458 DEBUG_PROBE); 459 } 460 } 461 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 462 } 463 464 static void 465 piix_setup_channel(struct ata_channel *chp) 466 { 467 u_int8_t mode[2], drive; 468 u_int32_t oidetim, idetim, idedma_ctl; 469 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 470 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 471 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 472 473 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 474 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 475 idedma_ctl = 0; 476 477 /* set up new idetim: Enable IDE registers decode */ 478 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 479 chp->ch_channel); 480 481 /* setup DMA */ 482 pciide_channel_dma_setup(cp); 483 484 /* 485 * Here we have to mess up with drives mode: PIIX can't have 486 * different timings for master and slave drives. 487 * We need to find the best combination. 488 */ 489 490 /* If both drives supports DMA, take the lower mode */ 491 if ((drvp[0].drive_flags & DRIVE_DMA) && 492 (drvp[1].drive_flags & DRIVE_DMA)) { 493 mode[0] = mode[1] = 494 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 495 drvp[0].DMA_mode = mode[0]; 496 drvp[1].DMA_mode = mode[1]; 497 goto ok; 498 } 499 /* 500 * If only one drive supports DMA, use its mode, and 501 * put the other one in PIO mode 0 if mode not compatible 502 */ 503 if (drvp[0].drive_flags & DRIVE_DMA) { 504 mode[0] = drvp[0].DMA_mode; 505 mode[1] = drvp[1].PIO_mode; 506 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 507 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 508 mode[1] = drvp[1].PIO_mode = 0; 509 goto ok; 510 } 511 if (drvp[1].drive_flags & DRIVE_DMA) { 512 mode[1] = drvp[1].DMA_mode; 513 mode[0] = drvp[0].PIO_mode; 514 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 515 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 516 mode[0] = drvp[0].PIO_mode = 0; 517 goto ok; 518 } 519 /* 520 * If both drives are not DMA, takes the lower mode, unless 521 * one of them is PIO mode < 2 522 */ 523 if (drvp[0].PIO_mode < 2) { 524 mode[0] = drvp[0].PIO_mode = 0; 525 mode[1] = drvp[1].PIO_mode; 526 } else if (drvp[1].PIO_mode < 2) { 527 mode[1] = drvp[1].PIO_mode = 0; 528 mode[0] = drvp[0].PIO_mode; 529 } else { 530 mode[0] = mode[1] = 531 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 532 drvp[0].PIO_mode = mode[0]; 533 drvp[1].PIO_mode = mode[1]; 534 } 535 ok: /* The modes are setup */ 536 for (drive = 0; drive < 2; drive++) { 537 if (drvp[drive].drive_flags & DRIVE_DMA) { 538 idetim |= piix_setup_idetim_timings( 539 mode[drive], 1, chp->ch_channel); 540 goto end; 541 } 542 } 543 /* If we are there, none of the drives are DMA */ 544 if (mode[0] >= 2) 545 idetim |= piix_setup_idetim_timings( 546 mode[0], 0, chp->ch_channel); 547 else 548 idetim |= piix_setup_idetim_timings( 549 mode[1], 0, chp->ch_channel); 550 end: /* 551 * timing mode is now set up in the controller. Enable 552 * it per-drive 553 */ 554 for (drive = 0; drive < 2; drive++) { 555 /* If no drive, skip */ 556 if ((drvp[drive].drive_flags & DRIVE) == 0) 557 continue; 558 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 559 if (drvp[drive].drive_flags & DRIVE_DMA) 560 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 561 } 562 if (idedma_ctl != 0) { 563 /* Add software bits in status register */ 564 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 565 idedma_ctl); 566 } 567 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 568 } 569 570 static void 571 piix3_4_setup_channel(struct ata_channel *chp) 572 { 573 struct ata_drive_datas *drvp; 574 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 575 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 576 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 577 struct wdc_softc *wdc = &sc->sc_wdcdev; 578 int drive, s; 579 int channel = chp->ch_channel; 580 581 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 582 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 583 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 584 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 585 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 586 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 587 PIIX_SIDETIM_RTC_MASK(channel)); 588 idedma_ctl = 0; 589 590 /* set up new idetim: Enable IDE registers decode */ 591 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 592 593 /* setup DMA if needed */ 594 pciide_channel_dma_setup(cp); 595 596 for (drive = 0; drive < 2; drive++) { 597 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 598 PIIX_UDMATIM_SET(0x3, channel, drive)); 599 drvp = &chp->ch_drive[drive]; 600 /* If no drive, skip */ 601 if ((drvp->drive_flags & DRIVE) == 0) 602 continue; 603 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 604 (drvp->drive_flags & DRIVE_UDMA) == 0)) 605 goto pio; 606 607 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 608 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 609 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 610 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 611 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 612 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 613 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 614 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 615 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 616 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 617 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 618 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 619 ideconf |= PIIX_CONFIG_PINGPONG; 620 } 621 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 622 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 623 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 624 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 625 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 626 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 631 /* setup Ultra/100 */ 632 if (drvp->UDMA_mode > 2 && 633 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 634 drvp->UDMA_mode = 2; 635 if (drvp->UDMA_mode > 4) { 636 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 637 } else { 638 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 639 if (drvp->UDMA_mode > 2) { 640 ideconf |= PIIX_CONFIG_UDMA66(channel, 641 drive); 642 } else { 643 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 644 drive); 645 } 646 } 647 } 648 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 649 /* setup Ultra/66 */ 650 if (drvp->UDMA_mode > 2 && 651 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 652 drvp->UDMA_mode = 2; 653 if (drvp->UDMA_mode > 2) 654 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 655 else 656 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 657 } 658 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 659 (drvp->drive_flags & DRIVE_UDMA)) { 660 /* use Ultra/DMA */ 661 s = splbio(); 662 drvp->drive_flags &= ~DRIVE_DMA; 663 splx(s); 664 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 665 udmareg |= PIIX_UDMATIM_SET( 666 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 667 } else { 668 /* use Multiword DMA */ 669 s = splbio(); 670 drvp->drive_flags &= ~DRIVE_UDMA; 671 splx(s); 672 if (drive == 0) { 673 idetim |= piix_setup_idetim_timings( 674 drvp->DMA_mode, 1, channel); 675 } else { 676 sidetim |= piix_setup_sidetim_timings( 677 drvp->DMA_mode, 1, channel); 678 idetim =PIIX_IDETIM_SET(idetim, 679 PIIX_IDETIM_SITRE, channel); 680 } 681 } 682 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 683 684 pio: /* use PIO mode */ 685 idetim |= piix_setup_idetim_drvs(drvp); 686 if (drive == 0) { 687 idetim |= piix_setup_idetim_timings( 688 drvp->PIO_mode, 0, channel); 689 } else { 690 sidetim |= piix_setup_sidetim_timings( 691 drvp->PIO_mode, 0, channel); 692 idetim =PIIX_IDETIM_SET(idetim, 693 PIIX_IDETIM_SITRE, channel); 694 } 695 } 696 if (idedma_ctl != 0) { 697 /* Add software bits in status register */ 698 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 699 idedma_ctl); 700 } 701 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 702 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 703 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 704 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 705 } 706 707 708 /* setup ISP and RTC fields, based on mode */ 709 static u_int32_t 710 piix_setup_idetim_timings(mode, dma, channel) 711 u_int8_t mode; 712 u_int8_t dma; 713 u_int8_t channel; 714 { 715 716 if (dma) 717 return PIIX_IDETIM_SET(0, 718 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 719 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 720 channel); 721 else 722 return PIIX_IDETIM_SET(0, 723 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 724 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 725 channel); 726 } 727 728 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 729 static u_int32_t 730 piix_setup_idetim_drvs(drvp) 731 struct ata_drive_datas *drvp; 732 { 733 u_int32_t ret = 0; 734 struct ata_channel *chp = drvp->chnl_softc; 735 u_int8_t channel = chp->ch_channel; 736 u_int8_t drive = drvp->drive; 737 738 /* 739 * If drive is using UDMA, timings setups are independant 740 * So just check DMA and PIO here. 741 */ 742 if (drvp->drive_flags & DRIVE_DMA) { 743 /* if mode = DMA mode 0, use compatible timings */ 744 if ((drvp->drive_flags & DRIVE_DMA) && 745 drvp->DMA_mode == 0) { 746 drvp->PIO_mode = 0; 747 return ret; 748 } 749 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 750 /* 751 * PIO and DMA timings are the same, use fast timings for PIO 752 * too, else use compat timings. 753 */ 754 if ((piix_isp_pio[drvp->PIO_mode] != 755 piix_isp_dma[drvp->DMA_mode]) || 756 (piix_rtc_pio[drvp->PIO_mode] != 757 piix_rtc_dma[drvp->DMA_mode])) 758 drvp->PIO_mode = 0; 759 /* if PIO mode <= 2, use compat timings for PIO */ 760 if (drvp->PIO_mode <= 2) { 761 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 762 channel); 763 return ret; 764 } 765 } 766 767 /* 768 * Now setup PIO modes. If mode < 2, use compat timings. 769 * Else enable fast timings. Enable IORDY and prefetch/post 770 * if PIO mode >= 3. 771 */ 772 773 if (drvp->PIO_mode < 2) 774 return ret; 775 776 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 777 if (drvp->PIO_mode >= 3) { 778 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 779 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 780 } 781 return ret; 782 } 783 784 /* setup values in SIDETIM registers, based on mode */ 785 static u_int32_t 786 piix_setup_sidetim_timings(mode, dma, channel) 787 u_int8_t mode; 788 u_int8_t dma; 789 u_int8_t channel; 790 { 791 if (dma) 792 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 793 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 794 else 795 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 796 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 797 } 798 799 static void 800 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 801 { 802 struct pciide_channel *cp; 803 bus_size_t cmdsize, ctlsize; 804 pcireg_t interface, cmdsts; 805 int channel, ich = 0; 806 uint8_t reg; 807 808 if (pciide_chipen(sc, pa) == 0) 809 return; 810 811 aprint_normal("%s: bus-master DMA support present", 812 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 813 pciide_mapreg_dma(sc, pa); 814 aprint_normal("\n"); 815 816 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 817 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 818 if (sc->sc_dma_ok) { 819 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 820 sc->sc_wdcdev.irqack = pciide_irqack; 821 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 822 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 823 } 824 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 825 826 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 827 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 828 829 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 830 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 831 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 832 833 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 834 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 835 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 836 837 interface = PCI_INTERFACE(pa->pa_class); 838 839 switch (sc->sc_pp->ide_product) { 840 case PCI_PRODUCT_INTEL_6300ESB_SATA: 841 case PCI_PRODUCT_INTEL_6300ESB_RAID: 842 case PCI_PRODUCT_INTEL_63XXESB_SATA: 843 case PCI_PRODUCT_INTEL_82801EB_SATA: 844 case PCI_PRODUCT_INTEL_82801ER_SATA: 845 ich = 5; 846 break; 847 case PCI_PRODUCT_INTEL_82801FB_SATA: 848 case PCI_PRODUCT_INTEL_82801FR_SATA: 849 case PCI_PRODUCT_INTEL_82801FBM_SATA: 850 ich = 6; 851 break; 852 case PCI_PRODUCT_INTEL_82801G_SATA: 853 case PCI_PRODUCT_INTEL_82801G_SATA_AHCI: 854 case PCI_PRODUCT_INTEL_82801G_SATA_RAID: 855 case PCI_PRODUCT_INTEL_82801GBM_SATA: 856 case PCI_PRODUCT_INTEL_82801GBM_AHCI: 857 case PCI_PRODUCT_INTEL_82801GHM_RAID: 858 ich = 7; 859 break; 860 case PCI_PRODUCT_INTEL_82801H_SATA_1: 861 case PCI_PRODUCT_INTEL_82801H_SATA_AHCI6: 862 case PCI_PRODUCT_INTEL_82801H_SATA_RAID: 863 case PCI_PRODUCT_INTEL_82801H_SATA_AHCI4: 864 case PCI_PRODUCT_INTEL_82801H_SATA_2: 865 case PCI_PRODUCT_INTEL_82801HBM_SATA_1: 866 case PCI_PRODUCT_INTEL_82801HBM_SATA_2: 867 ich = 8; 868 break; 869 } 870 871 /* 872 * Put the SATA portion of controllers that don't operate in combined 873 * mode into native PCI modes so the maximum number of devices can be 874 * used. Intel calls this "enhanced mode". 875 */ 876 877 if (ich == 5) { 878 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP); 879 if ((reg & ICH5_SATA_MAP_COMBINED) == 0) { 880 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 881 ICH5_SATA_PI); 882 reg |= ICH5_SATA_PI_PRI_NATIVE | 883 ICH5_SATA_PI_SEC_NATIVE; 884 pciide_pci_write(pa->pa_pc, pa->pa_tag, 885 ICH5_SATA_PI, reg); 886 interface |= PCIIDE_INTERFACE_PCI(0) | 887 PCIIDE_INTERFACE_PCI(1); 888 } 889 } else { 890 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, ICH5_SATA_MAP) & 891 ICH6_SATA_MAP_CMB_MASK; 892 if (reg != ICH6_SATA_MAP_CMB_PRI && 893 reg != ICH6_SATA_MAP_CMB_SEC) { 894 reg = pciide_pci_read(pa->pa_pc, pa->pa_tag, 895 ICH5_SATA_PI); 896 reg |= ICH5_SATA_PI_PRI_NATIVE | 897 ICH5_SATA_PI_SEC_NATIVE; 898 899 pciide_pci_write(pa->pa_pc, pa->pa_tag, 900 ICH5_SATA_PI, reg); 901 interface |= PCIIDE_INTERFACE_PCI(0) | 902 PCIIDE_INTERFACE_PCI(1); 903 904 /* 905 * Ask for SATA IDE Mode, we don't need to do this 906 * for the combined mode case as combined mode is 907 * only allowed in IDE Mode. 908 */ 909 910 if (ich >= 7) { 911 reg = pciide_pci_read(sc->sc_pc, sc->sc_tag, 912 ICH5_SATA_MAP) & ~ICH7_SATA_MAP_SMS_MASK; 913 pciide_pci_write(pa->pa_pc, pa->pa_tag, 914 ICH5_SATA_MAP, reg); 915 } 916 } 917 } 918 919 wdc_allocate_regs(&sc->sc_wdcdev); 920 921 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 922 channel++) { 923 cp = &sc->pciide_channels[channel]; 924 if (pciide_chansetup(sc, channel, interface) == 0) 925 continue; 926 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 927 pciide_pci_intr); 928 } 929 } 930
Indexes created Fri Sep 26 20:09:58 GMT 2025