piixide.c revision 1.35.2.1
1 /* $NetBSD: piixide.c,v 1.35.2.1 2007/10/24 22:00:15 pavel Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.35.2.1 2007/10/24 22:00:15 pavel Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 52 static void piixide_powerhook(int, void *); 53 static int piixide_match(struct device *, struct cfdata *, void *); 54 static void piixide_attach(struct device *, struct device *, void *); 55 56 static const struct pciide_product_desc pciide_intel_products[] = { 57 { PCI_PRODUCT_INTEL_82092AA, 58 0, 59 "Intel 82092AA IDE controller", 60 default_chip_map, 61 }, 62 { PCI_PRODUCT_INTEL_82371FB_IDE, 63 0, 64 "Intel 82371FB IDE controller (PIIX)", 65 piix_chip_map, 66 }, 67 { PCI_PRODUCT_INTEL_82371SB_IDE, 68 0, 69 "Intel 82371SB IDE Interface (PIIX3)", 70 piix_chip_map, 71 }, 72 { PCI_PRODUCT_INTEL_82371AB_IDE, 73 0, 74 "Intel 82371AB IDE controller (PIIX4)", 75 piix_chip_map, 76 }, 77 { PCI_PRODUCT_INTEL_82440MX_IDE, 78 0, 79 "Intel 82440MX IDE controller", 80 piix_chip_map 81 }, 82 { PCI_PRODUCT_INTEL_82801AA_IDE, 83 0, 84 "Intel 82801AA IDE Controller (ICH)", 85 piix_chip_map, 86 }, 87 { PCI_PRODUCT_INTEL_82801AB_IDE, 88 0, 89 "Intel 82801AB IDE Controller (ICH0)", 90 piix_chip_map, 91 }, 92 { PCI_PRODUCT_INTEL_82801BA_IDE, 93 0, 94 "Intel 82801BA IDE Controller (ICH2)", 95 piix_chip_map, 96 }, 97 { PCI_PRODUCT_INTEL_82801BAM_IDE, 98 0, 99 "Intel 82801BAM IDE Controller (ICH2-M)", 100 piix_chip_map, 101 }, 102 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 103 0, 104 "Intel 82801CA IDE Controller (ICH3)", 105 piix_chip_map, 106 }, 107 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 108 0, 109 "Intel 82801CA IDE Controller (ICH3)", 110 piix_chip_map, 111 }, 112 { PCI_PRODUCT_INTEL_82801DB_IDE, 113 0, 114 "Intel 82801DB IDE Controller (ICH4)", 115 piix_chip_map, 116 }, 117 { PCI_PRODUCT_INTEL_82801DBM_IDE, 118 0, 119 "Intel 82801DBM IDE Controller (ICH4-M)", 120 piix_chip_map, 121 }, 122 { PCI_PRODUCT_INTEL_82801EB_IDE, 123 0, 124 "Intel 82801EB IDE Controller (ICH5)", 125 piix_chip_map, 126 }, 127 { PCI_PRODUCT_INTEL_82801EB_SATA, 128 0, 129 "Intel 82801EB Serial ATA Controller", 130 piixsata_chip_map, 131 }, 132 { PCI_PRODUCT_INTEL_82801ER_SATA, 133 0, 134 "Intel 82801ER Serial ATA/Raid Controller", 135 piixsata_chip_map, 136 }, 137 { PCI_PRODUCT_INTEL_6300ESB_IDE, 138 0, 139 "Intel 6300ESB IDE Controller (ICH5)", 140 piix_chip_map, 141 }, 142 { PCI_PRODUCT_INTEL_6300ESB_SATA, 143 0, 144 "Intel 6300ESB Serial ATA Controller", 145 piixsata_chip_map, 146 }, 147 { PCI_PRODUCT_INTEL_6300ESB_RAID, 148 0, 149 "Intel 6300ESB Serial ATA/RAID Controller", 150 piixsata_chip_map, 151 }, 152 { PCI_PRODUCT_INTEL_82801FB_IDE, 153 0, 154 "Intel 82801FB IDE Controller (ICH6)", 155 piix_chip_map, 156 }, 157 { PCI_PRODUCT_INTEL_82801FB_SATA, 158 0, 159 "Intel 82801FB Serial ATA/Raid Controller", 160 piixsata_chip_map, 161 }, 162 { PCI_PRODUCT_INTEL_82801FR_SATA, 163 0, 164 "Intel 82801FR Serial ATA/Raid Controller", 165 piixsata_chip_map, 166 }, 167 { PCI_PRODUCT_INTEL_82801FBM_SATA, 168 0, 169 "Intel 82801FBM Serial ATA Controller (ICH6)", 170 piixsata_chip_map, 171 }, 172 { PCI_PRODUCT_INTEL_82801G_IDE, 173 0, 174 "Intel 82801GB/GR IDE Controller (ICH7)", 175 piix_chip_map, 176 }, 177 { PCI_PRODUCT_INTEL_82801G_SATA, 178 0, 179 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 180 piixsata_chip_map, 181 }, 182 { PCI_PRODUCT_INTEL_82801GBM_SATA, 183 0, 184 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 185 piixsata_chip_map, 186 }, 187 { PCI_PRODUCT_INTEL_82801H_SATA_1, 188 0, 189 "Intel 82801H Serial ATA Controller (ICH8)", 190 piixsata_chip_map, 191 }, 192 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 193 0, 194 "Intel 82801H Serial ATA RAID Controller (ICH8)", 195 piixsata_chip_map, 196 }, 197 { PCI_PRODUCT_INTEL_82801H_SATA_2, 198 0, 199 "Intel 82801H Serial ATA Controller (ICH8)", 200 piixsata_chip_map, 201 }, 202 { PCI_PRODUCT_INTEL_82801HBM_IDE, 203 0, 204 "Intel 82801HBM IDE Controller (ICH8M)", 205 piix_chip_map, 206 }, 207 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 208 0, 209 "Intel 82801HBM Serial ATA Controller (ICH8M)", 210 piixsata_chip_map, 211 }, 212 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 213 0, 214 "Intel 82801HBM Serial ATA Controller (ICH8M)", 215 piixsata_chip_map, 216 }, 217 { PCI_PRODUCT_INTEL_82801HEM_SATA, 218 0, 219 "Intel 82801HEM Serial ATA Controller (ICH8M)", 220 piixsata_chip_map, 221 }, 222 { PCI_PRODUCT_INTEL_63XXESB_IDE, 223 0, 224 "Intel 631xESB/632xESB IDE Controller", 225 piix_chip_map, 226 }, 227 { PCI_PRODUCT_INTEL_82801I_SATA_1, 228 0, 229 "Intel 82801I Serial ATA Controller (ICH9)", 230 piixsata_chip_map, 231 }, 232 { PCI_PRODUCT_INTEL_82801I_SATA_2, 233 0, 234 "Intel 82801I Serial ATA Controller (ICH9)", 235 piixsata_chip_map, 236 }, 237 { PCI_PRODUCT_INTEL_82801I_SATA_3, 238 0, 239 "Intel 82801I Serial ATA Controller (ICH9)", 240 piixsata_chip_map, 241 }, 242 { PCI_PRODUCT_INTEL_63XXESB_SATA, 243 0, 244 "Intel 631xESB/632xESB Serial ATA Controller", 245 piixsata_chip_map, 246 }, 247 { 0, 248 0, 249 NULL, 250 NULL 251 } 252 }; 253 254 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 255 piixide_match, piixide_attach, NULL, NULL); 256 257 static int 258 piixide_match(struct device *parent, struct cfdata *match, 259 void *aux) 260 { 261 struct pci_attach_args *pa = aux; 262 263 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 264 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 265 return (2); 266 } 267 return (0); 268 } 269 270 static void 271 piixide_attach(struct device *parent, struct device *self, void *aux) 272 { 273 struct pci_attach_args *pa = aux; 274 struct pciide_softc *sc = (struct pciide_softc *)self; 275 276 pciide_common_attach(sc, pa, 277 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 278 279 /* Setup our powerhook */ 280 sc->sc_powerhook = powerhook_establish( 281 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, piixide_powerhook, sc); 282 if (sc->sc_powerhook == NULL) 283 printf("%s: WARNING: unable to establish PCI power hook\n", 284 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 285 } 286 287 static void 288 piixide_powerhook(int why, void *hdl) 289 { 290 struct pciide_softc *sc = (struct pciide_softc *)hdl; 291 292 switch (why) { 293 case PWR_SUSPEND: 294 case PWR_STANDBY: 295 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 296 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 297 PIIX_IDETIM); 298 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 299 PIIX_UDMATIM); 300 break; 301 case PWR_RESUME: 302 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 303 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 304 sc->sc_idetim); 305 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 306 sc->sc_udmatim); 307 break; 308 case PWR_SOFTSUSPEND: 309 case PWR_SOFTSTANDBY: 310 case PWR_SOFTRESUME: 311 break; 312 } 313 314 return; 315 } 316 317 static void 318 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 319 { 320 struct pciide_channel *cp; 321 int channel; 322 u_int32_t idetim; 323 bus_size_t cmdsize, ctlsize; 324 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 325 326 if (pciide_chipen(sc, pa) == 0) 327 return; 328 329 aprint_normal("%s: bus-master DMA support present", 330 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 331 pciide_mapreg_dma(sc, pa); 332 aprint_normal("\n"); 333 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 334 if (sc->sc_dma_ok) { 335 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 336 sc->sc_wdcdev.irqack = pciide_irqack; 337 switch(sc->sc_pp->ide_product) { 338 case PCI_PRODUCT_INTEL_82371AB_IDE: 339 case PCI_PRODUCT_INTEL_82440MX_IDE: 340 case PCI_PRODUCT_INTEL_82801AA_IDE: 341 case PCI_PRODUCT_INTEL_82801AB_IDE: 342 case PCI_PRODUCT_INTEL_82801BA_IDE: 343 case PCI_PRODUCT_INTEL_82801BAM_IDE: 344 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 345 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 346 case PCI_PRODUCT_INTEL_82801DB_IDE: 347 case PCI_PRODUCT_INTEL_82801DBM_IDE: 348 case PCI_PRODUCT_INTEL_82801EB_IDE: 349 case PCI_PRODUCT_INTEL_6300ESB_IDE: 350 case PCI_PRODUCT_INTEL_82801FB_IDE: 351 case PCI_PRODUCT_INTEL_82801G_IDE: 352 case PCI_PRODUCT_INTEL_82801HBM_IDE: 353 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 354 } 355 } 356 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 357 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 358 switch(sc->sc_pp->ide_product) { 359 case PCI_PRODUCT_INTEL_82801AA_IDE: 360 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 361 break; 362 case PCI_PRODUCT_INTEL_82801BA_IDE: 363 case PCI_PRODUCT_INTEL_82801BAM_IDE: 364 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 365 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 366 case PCI_PRODUCT_INTEL_82801DB_IDE: 367 case PCI_PRODUCT_INTEL_82801DBM_IDE: 368 case PCI_PRODUCT_INTEL_82801EB_IDE: 369 case PCI_PRODUCT_INTEL_6300ESB_IDE: 370 case PCI_PRODUCT_INTEL_82801FB_IDE: 371 case PCI_PRODUCT_INTEL_82801G_IDE: 372 case PCI_PRODUCT_INTEL_82801HBM_IDE: 373 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 374 break; 375 default: 376 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 377 } 378 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 379 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 380 else 381 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 382 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 383 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 384 385 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 386 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 387 DEBUG_PROBE); 388 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 389 ATADEBUG_PRINT((", sidetim=0x%x", 390 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 391 DEBUG_PROBE); 392 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 393 ATADEBUG_PRINT((", udamreg 0x%x", 394 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 395 DEBUG_PROBE); 396 } 397 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 398 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 400 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 402 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 404 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 405 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 406 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 407 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 408 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 409 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 410 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 411 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 412 DEBUG_PROBE); 413 } 414 415 } 416 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 417 418 wdc_allocate_regs(&sc->sc_wdcdev); 419 420 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 421 channel++) { 422 cp = &sc->pciide_channels[channel]; 423 if (pciide_chansetup(sc, channel, interface) == 0) 424 continue; 425 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 426 if ((PIIX_IDETIM_READ(idetim, channel) & 427 PIIX_IDETIM_IDE) == 0) { 428 #if 1 429 aprint_normal("%s: %s channel ignored (disabled)\n", 430 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 431 cp->ata_channel.ch_flags |= ATACH_DISABLED; 432 continue; 433 #else 434 pcireg_t interface; 435 436 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 437 channel); 438 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 439 idetim); 440 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 441 sc->sc_tag, PCI_CLASS_REG)); 442 aprint_normal("channel %d idetim=%08x interface=%02x\n", 443 channel, idetim, interface); 444 #endif 445 } 446 pciide_mapchan(pa, cp, interface, 447 &cmdsize, &ctlsize, pciide_pci_intr); 448 } 449 450 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 451 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 452 DEBUG_PROBE); 453 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 454 ATADEBUG_PRINT((", sidetim=0x%x", 455 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 456 DEBUG_PROBE); 457 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 458 ATADEBUG_PRINT((", udamreg 0x%x", 459 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 460 DEBUG_PROBE); 461 } 462 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 472 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 473 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 474 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 475 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 476 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 477 DEBUG_PROBE); 478 } 479 } 480 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 481 } 482 483 static void 484 piix_setup_channel(struct ata_channel *chp) 485 { 486 u_int8_t mode[2], drive; 487 u_int32_t oidetim, idetim, idedma_ctl; 488 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 489 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 490 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 491 492 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 493 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 494 idedma_ctl = 0; 495 496 /* set up new idetim: Enable IDE registers decode */ 497 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 498 chp->ch_channel); 499 500 /* setup DMA */ 501 pciide_channel_dma_setup(cp); 502 503 /* 504 * Here we have to mess up with drives mode: PIIX can't have 505 * different timings for master and slave drives. 506 * We need to find the best combination. 507 */ 508 509 /* If both drives supports DMA, take the lower mode */ 510 if ((drvp[0].drive_flags & DRIVE_DMA) && 511 (drvp[1].drive_flags & DRIVE_DMA)) { 512 mode[0] = mode[1] = 513 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 514 drvp[0].DMA_mode = mode[0]; 515 drvp[1].DMA_mode = mode[1]; 516 goto ok; 517 } 518 /* 519 * If only one drive supports DMA, use its mode, and 520 * put the other one in PIO mode 0 if mode not compatible 521 */ 522 if (drvp[0].drive_flags & DRIVE_DMA) { 523 mode[0] = drvp[0].DMA_mode; 524 mode[1] = drvp[1].PIO_mode; 525 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 526 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 527 mode[1] = drvp[1].PIO_mode = 0; 528 goto ok; 529 } 530 if (drvp[1].drive_flags & DRIVE_DMA) { 531 mode[1] = drvp[1].DMA_mode; 532 mode[0] = drvp[0].PIO_mode; 533 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 534 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 535 mode[0] = drvp[0].PIO_mode = 0; 536 goto ok; 537 } 538 /* 539 * If both drives are not DMA, takes the lower mode, unless 540 * one of them is PIO mode < 2 541 */ 542 if (drvp[0].PIO_mode < 2) { 543 mode[0] = drvp[0].PIO_mode = 0; 544 mode[1] = drvp[1].PIO_mode; 545 } else if (drvp[1].PIO_mode < 2) { 546 mode[1] = drvp[1].PIO_mode = 0; 547 mode[0] = drvp[0].PIO_mode; 548 } else { 549 mode[0] = mode[1] = 550 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 551 drvp[0].PIO_mode = mode[0]; 552 drvp[1].PIO_mode = mode[1]; 553 } 554 ok: /* The modes are setup */ 555 for (drive = 0; drive < 2; drive++) { 556 if (drvp[drive].drive_flags & DRIVE_DMA) { 557 idetim |= piix_setup_idetim_timings( 558 mode[drive], 1, chp->ch_channel); 559 goto end; 560 } 561 } 562 /* If we are there, none of the drives are DMA */ 563 if (mode[0] >= 2) 564 idetim |= piix_setup_idetim_timings( 565 mode[0], 0, chp->ch_channel); 566 else 567 idetim |= piix_setup_idetim_timings( 568 mode[1], 0, chp->ch_channel); 569 end: /* 570 * timing mode is now set up in the controller. Enable 571 * it per-drive 572 */ 573 for (drive = 0; drive < 2; drive++) { 574 /* If no drive, skip */ 575 if ((drvp[drive].drive_flags & DRIVE) == 0) 576 continue; 577 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 578 if (drvp[drive].drive_flags & DRIVE_DMA) 579 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 580 } 581 if (idedma_ctl != 0) { 582 /* Add software bits in status register */ 583 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 584 idedma_ctl); 585 } 586 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 587 } 588 589 static void 590 piix3_4_setup_channel(struct ata_channel *chp) 591 { 592 struct ata_drive_datas *drvp; 593 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 594 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 595 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 596 struct wdc_softc *wdc = &sc->sc_wdcdev; 597 int drive, s; 598 int channel = chp->ch_channel; 599 600 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 601 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 602 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 603 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 604 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 605 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 606 PIIX_SIDETIM_RTC_MASK(channel)); 607 idedma_ctl = 0; 608 609 /* set up new idetim: Enable IDE registers decode */ 610 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 611 612 /* setup DMA if needed */ 613 pciide_channel_dma_setup(cp); 614 615 for (drive = 0; drive < 2; drive++) { 616 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 617 PIIX_UDMATIM_SET(0x3, channel, drive)); 618 drvp = &chp->ch_drive[drive]; 619 /* If no drive, skip */ 620 if ((drvp->drive_flags & DRIVE) == 0) 621 continue; 622 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 623 (drvp->drive_flags & DRIVE_UDMA) == 0)) 624 goto pio; 625 626 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 632 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 633 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 636 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 637 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 638 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 639 ideconf |= PIIX_CONFIG_PINGPONG; 640 } 641 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 642 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 643 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 644 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 645 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 646 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 647 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 648 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 649 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 650 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 651 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 652 /* setup Ultra/100 */ 653 if (drvp->UDMA_mode > 2 && 654 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 655 drvp->UDMA_mode = 2; 656 if (drvp->UDMA_mode > 4) { 657 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 658 } else { 659 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 660 if (drvp->UDMA_mode > 2) { 661 ideconf |= PIIX_CONFIG_UDMA66(channel, 662 drive); 663 } else { 664 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 665 drive); 666 } 667 } 668 } 669 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 670 /* setup Ultra/66 */ 671 if (drvp->UDMA_mode > 2 && 672 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 673 drvp->UDMA_mode = 2; 674 if (drvp->UDMA_mode > 2) 675 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 676 else 677 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 678 } 679 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 680 (drvp->drive_flags & DRIVE_UDMA)) { 681 /* use Ultra/DMA */ 682 s = splbio(); 683 drvp->drive_flags &= ~DRIVE_DMA; 684 splx(s); 685 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 686 udmareg |= PIIX_UDMATIM_SET( 687 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 688 } else { 689 /* use Multiword DMA */ 690 s = splbio(); 691 drvp->drive_flags &= ~DRIVE_UDMA; 692 splx(s); 693 if (drive == 0) { 694 idetim |= piix_setup_idetim_timings( 695 drvp->DMA_mode, 1, channel); 696 } else { 697 sidetim |= piix_setup_sidetim_timings( 698 drvp->DMA_mode, 1, channel); 699 idetim =PIIX_IDETIM_SET(idetim, 700 PIIX_IDETIM_SITRE, channel); 701 } 702 } 703 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 704 705 pio: /* use PIO mode */ 706 idetim |= piix_setup_idetim_drvs(drvp); 707 if (drive == 0) { 708 idetim |= piix_setup_idetim_timings( 709 drvp->PIO_mode, 0, channel); 710 } else { 711 sidetim |= piix_setup_sidetim_timings( 712 drvp->PIO_mode, 0, channel); 713 idetim =PIIX_IDETIM_SET(idetim, 714 PIIX_IDETIM_SITRE, channel); 715 } 716 } 717 if (idedma_ctl != 0) { 718 /* Add software bits in status register */ 719 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 720 idedma_ctl); 721 } 722 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 723 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 724 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 725 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 726 } 727 728 729 /* setup ISP and RTC fields, based on mode */ 730 static u_int32_t 731 piix_setup_idetim_timings(mode, dma, channel) 732 u_int8_t mode; 733 u_int8_t dma; 734 u_int8_t channel; 735 { 736 737 if (dma) 738 return PIIX_IDETIM_SET(0, 739 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 740 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 741 channel); 742 else 743 return PIIX_IDETIM_SET(0, 744 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 745 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 746 channel); 747 } 748 749 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 750 static u_int32_t 751 piix_setup_idetim_drvs(drvp) 752 struct ata_drive_datas *drvp; 753 { 754 u_int32_t ret = 0; 755 struct ata_channel *chp = drvp->chnl_softc; 756 u_int8_t channel = chp->ch_channel; 757 u_int8_t drive = drvp->drive; 758 759 /* 760 * If drive is using UDMA, timings setups are independent 761 * So just check DMA and PIO here. 762 */ 763 if (drvp->drive_flags & DRIVE_DMA) { 764 /* if mode = DMA mode 0, use compatible timings */ 765 if ((drvp->drive_flags & DRIVE_DMA) && 766 drvp->DMA_mode == 0) { 767 drvp->PIO_mode = 0; 768 return ret; 769 } 770 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 771 /* 772 * PIO and DMA timings are the same, use fast timings for PIO 773 * too, else use compat timings. 774 */ 775 if ((piix_isp_pio[drvp->PIO_mode] != 776 piix_isp_dma[drvp->DMA_mode]) || 777 (piix_rtc_pio[drvp->PIO_mode] != 778 piix_rtc_dma[drvp->DMA_mode])) 779 drvp->PIO_mode = 0; 780 /* if PIO mode <= 2, use compat timings for PIO */ 781 if (drvp->PIO_mode <= 2) { 782 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 783 channel); 784 return ret; 785 } 786 } 787 788 /* 789 * Now setup PIO modes. If mode < 2, use compat timings. 790 * Else enable fast timings. Enable IORDY and prefetch/post 791 * if PIO mode >= 3. 792 */ 793 794 if (drvp->PIO_mode < 2) 795 return ret; 796 797 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 798 if (drvp->PIO_mode >= 3) { 799 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 800 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 801 } 802 return ret; 803 } 804 805 /* setup values in SIDETIM registers, based on mode */ 806 static u_int32_t 807 piix_setup_sidetim_timings(mode, dma, channel) 808 u_int8_t mode; 809 u_int8_t dma; 810 u_int8_t channel; 811 { 812 if (dma) 813 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 814 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 815 else 816 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 817 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 818 } 819 820 static void 821 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 822 { 823 struct pciide_channel *cp; 824 bus_size_t cmdsize, ctlsize; 825 pcireg_t interface, cmdsts; 826 int channel; 827 828 if (pciide_chipen(sc, pa) == 0) 829 return; 830 831 aprint_normal("%s: bus-master DMA support present", 832 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 833 pciide_mapreg_dma(sc, pa); 834 aprint_normal("\n"); 835 836 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 837 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 838 if (sc->sc_dma_ok) { 839 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 840 sc->sc_wdcdev.irqack = pciide_irqack; 841 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 842 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 843 } 844 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 845 846 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 847 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 848 849 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 850 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 851 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 852 853 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 854 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 855 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 856 857 interface = PCI_INTERFACE(pa->pa_class); 858 859 wdc_allocate_regs(&sc->sc_wdcdev); 860 861 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 862 channel++) { 863 cp = &sc->pciide_channels[channel]; 864 if (pciide_chansetup(sc, channel, interface) == 0) 865 continue; 866 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 867 pciide_pci_intr); 868 } 869 } 870
Indexes created Mon Oct 20 20:10:13 GMT 2025