piixide.c revision 1.36.2.1
1 /* $NetBSD: piixide.c,v 1.36.2.1 2007/03/12 05:55:26 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.36.2.1 2007/03/12 05:55:26 rmind Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static void piixide_powerhook(int, void *); 54 static int piixide_match(struct device *, struct cfdata *, void *); 55 static void piixide_attach(struct device *, struct device *, void *); 56 57 static const struct pciide_product_desc pciide_intel_products[] = { 58 { PCI_PRODUCT_INTEL_82092AA, 59 0, 60 "Intel 82092AA IDE controller", 61 default_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371FB_IDE, 64 0, 65 "Intel 82371FB IDE controller (PIIX)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371SB_IDE, 69 0, 70 "Intel 82371SB IDE Interface (PIIX3)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82371AB_IDE, 74 0, 75 "Intel 82371AB IDE controller (PIIX4)", 76 piix_chip_map, 77 }, 78 { PCI_PRODUCT_INTEL_82440MX_IDE, 79 0, 80 "Intel 82440MX IDE controller", 81 piix_chip_map 82 }, 83 { PCI_PRODUCT_INTEL_82801AA_IDE, 84 0, 85 "Intel 82801AA IDE Controller (ICH)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801AB_IDE, 89 0, 90 "Intel 82801AB IDE Controller (ICH0)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BA_IDE, 94 0, 95 "Intel 82801BA IDE Controller (ICH2)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801BAM_IDE, 99 0, 100 "Intel 82801BAM IDE Controller (ICH2-M)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 109 0, 110 "Intel 82801CA IDE Controller (ICH3)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DB_IDE, 114 0, 115 "Intel 82801DB IDE Controller (ICH4)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801DBM_IDE, 119 0, 120 "Intel 82801DBM IDE Controller (ICH4-M)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_IDE, 124 0, 125 "Intel 82801EB IDE Controller (ICH5)", 126 piix_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801EB_SATA, 129 0, 130 "Intel 82801EB Serial ATA Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_82801ER_SATA, 134 0, 135 "Intel 82801ER Serial ATA/Raid Controller", 136 piixsata_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_IDE, 139 0, 140 "Intel 6300ESB IDE Controller (ICH5)", 141 piix_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_6300ESB_SATA, 144 0, 145 "Intel 6300ESB Serial ATA Controller", 146 piixsata_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_6300ESB_RAID, 149 0, 150 "Intel 6300ESB Serial ATA/RAID Controller", 151 piixsata_chip_map, 152 }, 153 { PCI_PRODUCT_INTEL_82801FB_IDE, 154 0, 155 "Intel 82801FB IDE Controller (ICH6)", 156 piix_chip_map, 157 }, 158 { PCI_PRODUCT_INTEL_82801FB_SATA, 159 0, 160 "Intel 82801FB Serial ATA/Raid Controller", 161 piixsata_chip_map, 162 }, 163 { PCI_PRODUCT_INTEL_82801FR_SATA, 164 0, 165 "Intel 82801FR Serial ATA/Raid Controller", 166 piixsata_chip_map, 167 }, 168 { PCI_PRODUCT_INTEL_82801FBM_SATA, 169 0, 170 "Intel 82801FBM Serial ATA Controller (ICH6)", 171 piixsata_chip_map, 172 }, 173 { PCI_PRODUCT_INTEL_82801G_IDE, 174 0, 175 "Intel 82801GB/GR IDE Controller (ICH7)", 176 piix_chip_map, 177 }, 178 { PCI_PRODUCT_INTEL_82801G_SATA, 179 0, 180 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 181 piixsata_chip_map, 182 }, 183 { PCI_PRODUCT_INTEL_82801GBM_SATA, 184 0, 185 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 186 piixsata_chip_map, 187 }, 188 { PCI_PRODUCT_INTEL_82801H_SATA_1, 189 0, 190 "Intel 82801H Serial ATA Controller (ICH8)", 191 piixsata_chip_map, 192 }, 193 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 194 0, 195 "Intel 82801H Serial ATA RAID Controller (ICH8)", 196 piixsata_chip_map, 197 }, 198 { PCI_PRODUCT_INTEL_82801H_SATA_2, 199 0, 200 "Intel 82801H Serial ATA Controller (ICH8)", 201 piixsata_chip_map, 202 }, 203 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 204 0, 205 "Intel 82801HBM Serial ATA Controller (ICH8M)", 206 piixsata_chip_map, 207 }, 208 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 209 0, 210 "Intel 82801HBM Serial ATA Controller (ICH8M)", 211 piixsata_chip_map, 212 }, 213 { PCI_PRODUCT_INTEL_63XXESB_IDE, 214 0, 215 "Intel 631xESB/632xESB IDE Controller", 216 piix_chip_map, 217 }, 218 { PCI_PRODUCT_INTEL_63XXESB_SATA, 219 0, 220 "Intel 631xESB/632xESB Serial ATA Controller", 221 piixsata_chip_map, 222 }, 223 { 0, 224 0, 225 NULL, 226 NULL 227 } 228 }; 229 230 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 231 piixide_match, piixide_attach, NULL, NULL); 232 233 static int 234 piixide_match(struct device *parent, struct cfdata *match, 235 void *aux) 236 { 237 struct pci_attach_args *pa = aux; 238 239 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 240 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 241 return (2); 242 } 243 return (0); 244 } 245 246 static void 247 piixide_attach(struct device *parent, struct device *self, void *aux) 248 { 249 struct pci_attach_args *pa = aux; 250 struct pciide_softc *sc = (struct pciide_softc *)self; 251 252 pciide_common_attach(sc, pa, 253 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 254 255 /* Setup our powerhook */ 256 sc->sc_powerhook = powerhook_establish( 257 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, piixide_powerhook, sc); 258 if (sc->sc_powerhook == NULL) 259 printf("%s: WARNING: unable to establish PCI power hook\n", 260 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 261 } 262 263 static void 264 piixide_powerhook(int why, void *hdl) 265 { 266 struct pciide_softc *sc = (struct pciide_softc *)hdl; 267 268 switch (why) { 269 case PWR_SUSPEND: 270 case PWR_STANDBY: 271 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 272 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 273 PIIX_IDETIM); 274 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 275 PIIX_UDMATIM); 276 break; 277 case PWR_RESUME: 278 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 279 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 280 sc->sc_idetim); 281 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 282 sc->sc_udmatim); 283 break; 284 case PWR_SOFTSUSPEND: 285 case PWR_SOFTSTANDBY: 286 case PWR_SOFTRESUME: 287 break; 288 } 289 290 return; 291 } 292 293 static void 294 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 295 { 296 struct pciide_channel *cp; 297 int channel; 298 u_int32_t idetim; 299 bus_size_t cmdsize, ctlsize; 300 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 301 302 if (pciide_chipen(sc, pa) == 0) 303 return; 304 305 aprint_verbose("%s: bus-master DMA support present", 306 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 307 pciide_mapreg_dma(sc, pa); 308 aprint_verbose("\n"); 309 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 310 if (sc->sc_dma_ok) { 311 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 312 sc->sc_wdcdev.irqack = pciide_irqack; 313 /* Do all revisions require DMA alignment workaround? */ 314 sc->sc_wdcdev.dma_init = piix_dma_init; 315 switch(sc->sc_pp->ide_product) { 316 case PCI_PRODUCT_INTEL_82371AB_IDE: 317 case PCI_PRODUCT_INTEL_82440MX_IDE: 318 case PCI_PRODUCT_INTEL_82801AA_IDE: 319 case PCI_PRODUCT_INTEL_82801AB_IDE: 320 case PCI_PRODUCT_INTEL_82801BA_IDE: 321 case PCI_PRODUCT_INTEL_82801BAM_IDE: 322 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 323 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 324 case PCI_PRODUCT_INTEL_82801DB_IDE: 325 case PCI_PRODUCT_INTEL_82801DBM_IDE: 326 case PCI_PRODUCT_INTEL_82801EB_IDE: 327 case PCI_PRODUCT_INTEL_6300ESB_IDE: 328 case PCI_PRODUCT_INTEL_82801FB_IDE: 329 case PCI_PRODUCT_INTEL_82801G_IDE: 330 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 331 } 332 } 333 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 334 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 335 switch(sc->sc_pp->ide_product) { 336 case PCI_PRODUCT_INTEL_82801AA_IDE: 337 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 338 break; 339 case PCI_PRODUCT_INTEL_82801BA_IDE: 340 case PCI_PRODUCT_INTEL_82801BAM_IDE: 341 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 342 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 343 case PCI_PRODUCT_INTEL_82801DB_IDE: 344 case PCI_PRODUCT_INTEL_82801DBM_IDE: 345 case PCI_PRODUCT_INTEL_82801EB_IDE: 346 case PCI_PRODUCT_INTEL_6300ESB_IDE: 347 case PCI_PRODUCT_INTEL_82801FB_IDE: 348 case PCI_PRODUCT_INTEL_82801G_IDE: 349 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 350 break; 351 default: 352 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 353 } 354 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 355 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 356 else 357 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 358 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 359 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 360 361 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 362 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 363 DEBUG_PROBE); 364 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 365 ATADEBUG_PRINT((", sidetim=0x%x", 366 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 367 DEBUG_PROBE); 368 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 369 ATADEBUG_PRINT((", udamreg 0x%x", 370 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 371 DEBUG_PROBE); 372 } 373 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 374 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 375 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 376 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 377 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 378 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 379 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 380 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 381 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 382 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 383 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 384 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 385 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 386 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 387 DEBUG_PROBE); 388 } 389 390 } 391 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 392 393 wdc_allocate_regs(&sc->sc_wdcdev); 394 395 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 396 channel++) { 397 cp = &sc->pciide_channels[channel]; 398 if (pciide_chansetup(sc, channel, interface) == 0) 399 continue; 400 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 401 if ((PIIX_IDETIM_READ(idetim, channel) & 402 PIIX_IDETIM_IDE) == 0) { 403 #if 1 404 aprint_normal("%s: %s channel ignored (disabled)\n", 405 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 406 cp->ata_channel.ch_flags |= ATACH_DISABLED; 407 continue; 408 #else 409 pcireg_t interface; 410 411 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 412 channel); 413 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 414 idetim); 415 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 416 sc->sc_tag, PCI_CLASS_REG)); 417 aprint_normal("channel %d idetim=%08x interface=%02x\n", 418 channel, idetim, interface); 419 #endif 420 } 421 pciide_mapchan(pa, cp, interface, 422 &cmdsize, &ctlsize, pciide_pci_intr); 423 } 424 425 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 426 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 427 DEBUG_PROBE); 428 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 429 ATADEBUG_PRINT((", sidetim=0x%x", 430 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 431 DEBUG_PROBE); 432 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 433 ATADEBUG_PRINT((", udamreg 0x%x", 434 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 435 DEBUG_PROBE); 436 } 437 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 438 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 439 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 440 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 441 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 442 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 443 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 444 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 445 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 446 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 447 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 448 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 449 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 450 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 451 DEBUG_PROBE); 452 } 453 } 454 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 455 } 456 457 static void 458 piix_setup_channel(struct ata_channel *chp) 459 { 460 u_int8_t mode[2], drive; 461 u_int32_t oidetim, idetim, idedma_ctl; 462 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 463 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 464 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 465 466 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 467 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 468 idedma_ctl = 0; 469 470 /* set up new idetim: Enable IDE registers decode */ 471 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 472 chp->ch_channel); 473 474 /* setup DMA */ 475 pciide_channel_dma_setup(cp); 476 477 /* 478 * Here we have to mess up with drives mode: PIIX can't have 479 * different timings for master and slave drives. 480 * We need to find the best combination. 481 */ 482 483 /* If both drives supports DMA, take the lower mode */ 484 if ((drvp[0].drive_flags & DRIVE_DMA) && 485 (drvp[1].drive_flags & DRIVE_DMA)) { 486 mode[0] = mode[1] = 487 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 488 drvp[0].DMA_mode = mode[0]; 489 drvp[1].DMA_mode = mode[1]; 490 goto ok; 491 } 492 /* 493 * If only one drive supports DMA, use its mode, and 494 * put the other one in PIO mode 0 if mode not compatible 495 */ 496 if (drvp[0].drive_flags & DRIVE_DMA) { 497 mode[0] = drvp[0].DMA_mode; 498 mode[1] = drvp[1].PIO_mode; 499 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 500 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 501 mode[1] = drvp[1].PIO_mode = 0; 502 goto ok; 503 } 504 if (drvp[1].drive_flags & DRIVE_DMA) { 505 mode[1] = drvp[1].DMA_mode; 506 mode[0] = drvp[0].PIO_mode; 507 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 508 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 509 mode[0] = drvp[0].PIO_mode = 0; 510 goto ok; 511 } 512 /* 513 * If both drives are not DMA, takes the lower mode, unless 514 * one of them is PIO mode < 2 515 */ 516 if (drvp[0].PIO_mode < 2) { 517 mode[0] = drvp[0].PIO_mode = 0; 518 mode[1] = drvp[1].PIO_mode; 519 } else if (drvp[1].PIO_mode < 2) { 520 mode[1] = drvp[1].PIO_mode = 0; 521 mode[0] = drvp[0].PIO_mode; 522 } else { 523 mode[0] = mode[1] = 524 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 525 drvp[0].PIO_mode = mode[0]; 526 drvp[1].PIO_mode = mode[1]; 527 } 528 ok: /* The modes are setup */ 529 for (drive = 0; drive < 2; drive++) { 530 if (drvp[drive].drive_flags & DRIVE_DMA) { 531 idetim |= piix_setup_idetim_timings( 532 mode[drive], 1, chp->ch_channel); 533 goto end; 534 } 535 } 536 /* If we are there, none of the drives are DMA */ 537 if (mode[0] >= 2) 538 idetim |= piix_setup_idetim_timings( 539 mode[0], 0, chp->ch_channel); 540 else 541 idetim |= piix_setup_idetim_timings( 542 mode[1], 0, chp->ch_channel); 543 end: /* 544 * timing mode is now set up in the controller. Enable 545 * it per-drive 546 */ 547 for (drive = 0; drive < 2; drive++) { 548 /* If no drive, skip */ 549 if ((drvp[drive].drive_flags & DRIVE) == 0) 550 continue; 551 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 552 if (drvp[drive].drive_flags & DRIVE_DMA) 553 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 554 } 555 if (idedma_ctl != 0) { 556 /* Add software bits in status register */ 557 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 558 idedma_ctl); 559 } 560 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 561 } 562 563 static void 564 piix3_4_setup_channel(struct ata_channel *chp) 565 { 566 struct ata_drive_datas *drvp; 567 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 568 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 569 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 570 struct wdc_softc *wdc = &sc->sc_wdcdev; 571 int drive, s; 572 int channel = chp->ch_channel; 573 574 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 575 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 576 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 577 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 578 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 579 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 580 PIIX_SIDETIM_RTC_MASK(channel)); 581 idedma_ctl = 0; 582 583 /* set up new idetim: Enable IDE registers decode */ 584 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 585 586 /* setup DMA if needed */ 587 pciide_channel_dma_setup(cp); 588 589 for (drive = 0; drive < 2; drive++) { 590 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 591 PIIX_UDMATIM_SET(0x3, channel, drive)); 592 drvp = &chp->ch_drive[drive]; 593 /* If no drive, skip */ 594 if ((drvp->drive_flags & DRIVE) == 0) 595 continue; 596 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 597 (drvp->drive_flags & DRIVE_UDMA) == 0)) 598 goto pio; 599 600 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 601 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 602 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 603 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 604 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 605 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 606 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 607 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 608 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 609 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 610 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 611 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 612 ideconf |= PIIX_CONFIG_PINGPONG; 613 } 614 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 615 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 616 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 617 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 618 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 619 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 620 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 621 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 622 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 623 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 624 /* setup Ultra/100 */ 625 if (drvp->UDMA_mode > 2 && 626 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 627 drvp->UDMA_mode = 2; 628 if (drvp->UDMA_mode > 4) { 629 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 630 } else { 631 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 632 if (drvp->UDMA_mode > 2) { 633 ideconf |= PIIX_CONFIG_UDMA66(channel, 634 drive); 635 } else { 636 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 637 drive); 638 } 639 } 640 } 641 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 642 /* setup Ultra/66 */ 643 if (drvp->UDMA_mode > 2 && 644 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 645 drvp->UDMA_mode = 2; 646 if (drvp->UDMA_mode > 2) 647 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 648 else 649 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 650 } 651 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 652 (drvp->drive_flags & DRIVE_UDMA)) { 653 /* use Ultra/DMA */ 654 s = splbio(); 655 drvp->drive_flags &= ~DRIVE_DMA; 656 splx(s); 657 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 658 udmareg |= PIIX_UDMATIM_SET( 659 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 660 } else { 661 /* use Multiword DMA */ 662 s = splbio(); 663 drvp->drive_flags &= ~DRIVE_UDMA; 664 splx(s); 665 if (drive == 0) { 666 idetim |= piix_setup_idetim_timings( 667 drvp->DMA_mode, 1, channel); 668 } else { 669 sidetim |= piix_setup_sidetim_timings( 670 drvp->DMA_mode, 1, channel); 671 idetim =PIIX_IDETIM_SET(idetim, 672 PIIX_IDETIM_SITRE, channel); 673 } 674 } 675 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 676 677 pio: /* use PIO mode */ 678 idetim |= piix_setup_idetim_drvs(drvp); 679 if (drive == 0) { 680 idetim |= piix_setup_idetim_timings( 681 drvp->PIO_mode, 0, channel); 682 } else { 683 sidetim |= piix_setup_sidetim_timings( 684 drvp->PIO_mode, 0, channel); 685 idetim =PIIX_IDETIM_SET(idetim, 686 PIIX_IDETIM_SITRE, channel); 687 } 688 } 689 if (idedma_ctl != 0) { 690 /* Add software bits in status register */ 691 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 692 idedma_ctl); 693 } 694 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 695 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 696 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 697 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 698 } 699 700 701 /* setup ISP and RTC fields, based on mode */ 702 static u_int32_t 703 piix_setup_idetim_timings(mode, dma, channel) 704 u_int8_t mode; 705 u_int8_t dma; 706 u_int8_t channel; 707 { 708 709 if (dma) 710 return PIIX_IDETIM_SET(0, 711 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 712 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 713 channel); 714 else 715 return PIIX_IDETIM_SET(0, 716 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 717 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 718 channel); 719 } 720 721 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 722 static u_int32_t 723 piix_setup_idetim_drvs(drvp) 724 struct ata_drive_datas *drvp; 725 { 726 u_int32_t ret = 0; 727 struct ata_channel *chp = drvp->chnl_softc; 728 u_int8_t channel = chp->ch_channel; 729 u_int8_t drive = drvp->drive; 730 731 /* 732 * If drive is using UDMA, timings setups are independent 733 * So just check DMA and PIO here. 734 */ 735 if (drvp->drive_flags & DRIVE_DMA) { 736 /* if mode = DMA mode 0, use compatible timings */ 737 if ((drvp->drive_flags & DRIVE_DMA) && 738 drvp->DMA_mode == 0) { 739 drvp->PIO_mode = 0; 740 return ret; 741 } 742 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 743 /* 744 * PIO and DMA timings are the same, use fast timings for PIO 745 * too, else use compat timings. 746 */ 747 if ((piix_isp_pio[drvp->PIO_mode] != 748 piix_isp_dma[drvp->DMA_mode]) || 749 (piix_rtc_pio[drvp->PIO_mode] != 750 piix_rtc_dma[drvp->DMA_mode])) 751 drvp->PIO_mode = 0; 752 /* if PIO mode <= 2, use compat timings for PIO */ 753 if (drvp->PIO_mode <= 2) { 754 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 755 channel); 756 return ret; 757 } 758 } 759 760 /* 761 * Now setup PIO modes. If mode < 2, use compat timings. 762 * Else enable fast timings. Enable IORDY and prefetch/post 763 * if PIO mode >= 3. 764 */ 765 766 if (drvp->PIO_mode < 2) 767 return ret; 768 769 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 770 if (drvp->PIO_mode >= 3) { 771 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 772 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 773 } 774 return ret; 775 } 776 777 /* setup values in SIDETIM registers, based on mode */ 778 static u_int32_t 779 piix_setup_sidetim_timings(mode, dma, channel) 780 u_int8_t mode; 781 u_int8_t dma; 782 u_int8_t channel; 783 { 784 if (dma) 785 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 786 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 787 else 788 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 789 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 790 } 791 792 static void 793 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 794 { 795 struct pciide_channel *cp; 796 bus_size_t cmdsize, ctlsize; 797 pcireg_t interface, cmdsts; 798 int channel; 799 800 if (pciide_chipen(sc, pa) == 0) 801 return; 802 803 aprint_verbose("%s: bus-master DMA support present", 804 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 805 pciide_mapreg_dma(sc, pa); 806 aprint_verbose("\n"); 807 808 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 809 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 810 if (sc->sc_dma_ok) { 811 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 812 sc->sc_wdcdev.irqack = pciide_irqack; 813 /* Do all revisions require DMA alignment workaround? */ 814 sc->sc_wdcdev.dma_init = piix_dma_init; 815 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 816 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 817 } 818 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 819 820 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 821 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 822 823 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 824 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 825 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 826 827 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 828 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 829 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 830 831 interface = PCI_INTERFACE(pa->pa_class); 832 833 wdc_allocate_regs(&sc->sc_wdcdev); 834 835 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 836 channel++) { 837 cp = &sc->pciide_channels[channel]; 838 if (pciide_chansetup(sc, channel, interface) == 0) 839 continue; 840 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 841 pciide_pci_intr); 842 } 843 } 844 845 static int 846 piix_dma_init(void *v, int channel, int drive, void *databuf, 847 size_t datalen, int flags) 848 { 849 850 /* use PIO for unaligned transfer */ 851 if (((uintptr_t)databuf) & 0x1) 852 return EINVAL; 853 854 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 855 } 856
Indexes created Thu Oct 16 14:10:15 GMT 2025