piixide.c revision 1.37.14.1
1 /* $NetBSD: piixide.c,v 1.37.14.1 2007/08/03 22:17:21 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.37.14.1 2007/08/03 22:17:21 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static pnp_status_t piixide_power(device_t, pnp_request_t, void *); 54 static int piixide_match(struct device *, struct cfdata *, void *); 55 static void piixide_attach(struct device *, struct device *, void *); 56 57 static const struct pciide_product_desc pciide_intel_products[] = { 58 { PCI_PRODUCT_INTEL_82092AA, 59 0, 60 "Intel 82092AA IDE controller", 61 default_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371FB_IDE, 64 0, 65 "Intel 82371FB IDE controller (PIIX)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371SB_IDE, 69 0, 70 "Intel 82371SB IDE Interface (PIIX3)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82371AB_IDE, 74 0, 75 "Intel 82371AB IDE controller (PIIX4)", 76 piix_chip_map, 77 }, 78 { PCI_PRODUCT_INTEL_82440MX_IDE, 79 0, 80 "Intel 82440MX IDE controller", 81 piix_chip_map 82 }, 83 { PCI_PRODUCT_INTEL_82801AA_IDE, 84 0, 85 "Intel 82801AA IDE Controller (ICH)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801AB_IDE, 89 0, 90 "Intel 82801AB IDE Controller (ICH0)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BA_IDE, 94 0, 95 "Intel 82801BA IDE Controller (ICH2)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801BAM_IDE, 99 0, 100 "Intel 82801BAM IDE Controller (ICH2-M)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 109 0, 110 "Intel 82801CA IDE Controller (ICH3)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DB_IDE, 114 0, 115 "Intel 82801DB IDE Controller (ICH4)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801DBM_IDE, 119 0, 120 "Intel 82801DBM IDE Controller (ICH4-M)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_IDE, 124 0, 125 "Intel 82801EB IDE Controller (ICH5)", 126 piix_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801EB_SATA, 129 0, 130 "Intel 82801EB Serial ATA Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_82801ER_SATA, 134 0, 135 "Intel 82801ER Serial ATA/Raid Controller", 136 piixsata_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_IDE, 139 0, 140 "Intel 6300ESB IDE Controller (ICH5)", 141 piix_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_6300ESB_SATA, 144 0, 145 "Intel 6300ESB Serial ATA Controller", 146 piixsata_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_6300ESB_RAID, 149 0, 150 "Intel 6300ESB Serial ATA/RAID Controller", 151 piixsata_chip_map, 152 }, 153 { PCI_PRODUCT_INTEL_82801FB_IDE, 154 0, 155 "Intel 82801FB IDE Controller (ICH6)", 156 piix_chip_map, 157 }, 158 { PCI_PRODUCT_INTEL_82801FB_SATA, 159 0, 160 "Intel 82801FB Serial ATA/Raid Controller", 161 piixsata_chip_map, 162 }, 163 { PCI_PRODUCT_INTEL_82801FR_SATA, 164 0, 165 "Intel 82801FR Serial ATA/Raid Controller", 166 piixsata_chip_map, 167 }, 168 { PCI_PRODUCT_INTEL_82801FBM_SATA, 169 0, 170 "Intel 82801FBM Serial ATA Controller (ICH6)", 171 piixsata_chip_map, 172 }, 173 { PCI_PRODUCT_INTEL_82801G_IDE, 174 0, 175 "Intel 82801GB/GR IDE Controller (ICH7)", 176 piix_chip_map, 177 }, 178 { PCI_PRODUCT_INTEL_82801G_SATA, 179 0, 180 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 181 piixsata_chip_map, 182 }, 183 { PCI_PRODUCT_INTEL_82801GBM_SATA, 184 0, 185 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 186 piixsata_chip_map, 187 }, 188 { PCI_PRODUCT_INTEL_82801H_SATA_1, 189 0, 190 "Intel 82801H Serial ATA Controller (ICH8)", 191 piixsata_chip_map, 192 }, 193 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 194 0, 195 "Intel 82801H Serial ATA RAID Controller (ICH8)", 196 piixsata_chip_map, 197 }, 198 { PCI_PRODUCT_INTEL_82801H_SATA_2, 199 0, 200 "Intel 82801H Serial ATA Controller (ICH8)", 201 piixsata_chip_map, 202 }, 203 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 204 0, 205 "Intel 82801HBM Serial ATA Controller (ICH8M)", 206 piixsata_chip_map, 207 }, 208 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 209 0, 210 "Intel 82801HBM Serial ATA Controller (ICH8M)", 211 piixsata_chip_map, 212 }, 213 { PCI_PRODUCT_INTEL_63XXESB_IDE, 214 0, 215 "Intel 631xESB/632xESB IDE Controller", 216 piix_chip_map, 217 }, 218 { PCI_PRODUCT_INTEL_63XXESB_SATA, 219 0, 220 "Intel 631xESB/632xESB Serial ATA Controller", 221 piixsata_chip_map, 222 }, 223 { 0, 224 0, 225 NULL, 226 NULL 227 } 228 }; 229 230 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 231 piixide_match, piixide_attach, NULL, NULL); 232 233 static int 234 piixide_match(struct device *parent, struct cfdata *match, 235 void *aux) 236 { 237 struct pci_attach_args *pa = aux; 238 239 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 240 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 241 return (2); 242 } 243 return (0); 244 } 245 246 static void 247 piixide_attach(struct device *parent, struct device *self, void *aux) 248 { 249 struct pci_attach_args *pa = aux; 250 struct pciide_softc *sc = (struct pciide_softc *)self; 251 pnp_status_t status; 252 253 pciide_common_attach(sc, pa, 254 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 255 256 /* Setup our power handler */ 257 status = pnp_register(self, piixide_power); 258 if (status != PNP_STATUS_SUCCESS) 259 aprint_error("%s: couldn't establish power handler\n", 260 device_xname(self)); 261 } 262 263 static pnp_status_t 264 piixide_power(device_t dv, pnp_request_t req, void *aux) 265 { 266 struct pciide_softc *sc = (struct pciide_softc *)dv; 267 pnp_state_t *state; 268 pnp_capabilities_t *caps; 269 pcireg_t val; 270 int off; 271 272 switch (req) { 273 case PNP_REQUEST_GET_CAPABILITIES: 274 caps = (pnp_capabilities_t *)aux; 275 pci_get_capability(sc->sc_pc, sc->sc_tag, 276 PCI_CAP_PWRMGMT, &off, &val); 277 caps->state = pci_pnp_capabilities(val); 278 caps->state |= PNP_STATE_D0 | PNP_STATE_D3; 279 break; 280 case PNP_REQUEST_GET_STATE: 281 state = (pnp_state_t *)aux; 282 if (pci_get_powerstate(sc->sc_pc, sc->sc_tag, &val) != 0) 283 *state = PNP_STATE_D0; 284 else 285 *state = pci_pnp_powerstate(val); 286 break; 287 case PNP_REQUEST_SET_STATE: 288 state = (pnp_state_t *)aux; 289 290 switch (*state) { 291 case PNP_STATE_D3: 292 val = PCI_PMCSR_STATE_D3; 293 pci_conf_capture(sc->sc_pc, sc->sc_tag, 294 &sc->sc_pciconf); 295 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 296 PIIX_IDETIM); 297 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 298 PIIX_UDMATIM); 299 break; 300 case PNP_STATE_D0: 301 val = PCI_PMCSR_STATE_D0; 302 break; 303 default: 304 return PNP_STATUS_UNSUPPORTED; 305 } 306 307 (void)pci_set_powerstate(sc->sc_pc, sc->sc_tag, val); 308 309 if (*state != PNP_STATE_D0) 310 break; 311 312 pci_conf_restore(sc->sc_pc, sc->sc_tag, 313 &sc->sc_pciconf); 314 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 315 sc->sc_idetim); 316 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 317 sc->sc_udmatim); 318 break; 319 default: 320 return PNP_STATUS_UNSUPPORTED; 321 } 322 323 return PNP_STATUS_SUCCESS; 324 } 325 326 static void 327 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 328 { 329 struct pciide_channel *cp; 330 int channel; 331 u_int32_t idetim; 332 bus_size_t cmdsize, ctlsize; 333 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 334 335 if (pciide_chipen(sc, pa) == 0) 336 return; 337 338 aprint_verbose("%s: bus-master DMA support present", 339 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 340 pciide_mapreg_dma(sc, pa); 341 aprint_verbose("\n"); 342 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 343 if (sc->sc_dma_ok) { 344 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 345 sc->sc_wdcdev.irqack = pciide_irqack; 346 /* Do all revisions require DMA alignment workaround? */ 347 sc->sc_wdcdev.dma_init = piix_dma_init; 348 switch(sc->sc_pp->ide_product) { 349 case PCI_PRODUCT_INTEL_82371AB_IDE: 350 case PCI_PRODUCT_INTEL_82440MX_IDE: 351 case PCI_PRODUCT_INTEL_82801AA_IDE: 352 case PCI_PRODUCT_INTEL_82801AB_IDE: 353 case PCI_PRODUCT_INTEL_82801BA_IDE: 354 case PCI_PRODUCT_INTEL_82801BAM_IDE: 355 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 356 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 357 case PCI_PRODUCT_INTEL_82801DB_IDE: 358 case PCI_PRODUCT_INTEL_82801DBM_IDE: 359 case PCI_PRODUCT_INTEL_82801EB_IDE: 360 case PCI_PRODUCT_INTEL_6300ESB_IDE: 361 case PCI_PRODUCT_INTEL_82801FB_IDE: 362 case PCI_PRODUCT_INTEL_82801G_IDE: 363 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 364 } 365 } 366 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 367 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 368 switch(sc->sc_pp->ide_product) { 369 case PCI_PRODUCT_INTEL_82801AA_IDE: 370 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 371 break; 372 case PCI_PRODUCT_INTEL_82801BA_IDE: 373 case PCI_PRODUCT_INTEL_82801BAM_IDE: 374 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 375 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 376 case PCI_PRODUCT_INTEL_82801DB_IDE: 377 case PCI_PRODUCT_INTEL_82801DBM_IDE: 378 case PCI_PRODUCT_INTEL_82801EB_IDE: 379 case PCI_PRODUCT_INTEL_6300ESB_IDE: 380 case PCI_PRODUCT_INTEL_82801FB_IDE: 381 case PCI_PRODUCT_INTEL_82801G_IDE: 382 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 383 break; 384 default: 385 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 386 } 387 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 388 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 389 else 390 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 391 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 392 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 393 394 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 395 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 396 DEBUG_PROBE); 397 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 398 ATADEBUG_PRINT((", sidetim=0x%x", 399 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 400 DEBUG_PROBE); 401 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 402 ATADEBUG_PRINT((", udamreg 0x%x", 403 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 404 DEBUG_PROBE); 405 } 406 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 407 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 408 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 409 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 410 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 411 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 412 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 413 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 414 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 415 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 416 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 417 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 418 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 419 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 420 DEBUG_PROBE); 421 } 422 423 } 424 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 425 426 wdc_allocate_regs(&sc->sc_wdcdev); 427 428 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 429 channel++) { 430 cp = &sc->pciide_channels[channel]; 431 if (pciide_chansetup(sc, channel, interface) == 0) 432 continue; 433 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 434 if ((PIIX_IDETIM_READ(idetim, channel) & 435 PIIX_IDETIM_IDE) == 0) { 436 #if 1 437 aprint_normal("%s: %s channel ignored (disabled)\n", 438 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 439 cp->ata_channel.ch_flags |= ATACH_DISABLED; 440 continue; 441 #else 442 pcireg_t interface; 443 444 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 445 channel); 446 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 447 idetim); 448 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 449 sc->sc_tag, PCI_CLASS_REG)); 450 aprint_normal("channel %d idetim=%08x interface=%02x\n", 451 channel, idetim, interface); 452 #endif 453 } 454 pciide_mapchan(pa, cp, interface, 455 &cmdsize, &ctlsize, pciide_pci_intr); 456 } 457 458 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 459 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 460 DEBUG_PROBE); 461 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 462 ATADEBUG_PRINT((", sidetim=0x%x", 463 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 464 DEBUG_PROBE); 465 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 466 ATADEBUG_PRINT((", udamreg 0x%x", 467 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 468 DEBUG_PROBE); 469 } 470 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 472 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 473 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 474 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 475 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 476 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 477 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 478 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 479 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 480 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 481 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 482 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 483 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 484 DEBUG_PROBE); 485 } 486 } 487 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 488 } 489 490 static void 491 piix_setup_channel(struct ata_channel *chp) 492 { 493 u_int8_t mode[2], drive; 494 u_int32_t oidetim, idetim, idedma_ctl; 495 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 496 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 497 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 498 499 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 500 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 501 idedma_ctl = 0; 502 503 /* set up new idetim: Enable IDE registers decode */ 504 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 505 chp->ch_channel); 506 507 /* setup DMA */ 508 pciide_channel_dma_setup(cp); 509 510 /* 511 * Here we have to mess up with drives mode: PIIX can't have 512 * different timings for master and slave drives. 513 * We need to find the best combination. 514 */ 515 516 /* If both drives supports DMA, take the lower mode */ 517 if ((drvp[0].drive_flags & DRIVE_DMA) && 518 (drvp[1].drive_flags & DRIVE_DMA)) { 519 mode[0] = mode[1] = 520 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 521 drvp[0].DMA_mode = mode[0]; 522 drvp[1].DMA_mode = mode[1]; 523 goto ok; 524 } 525 /* 526 * If only one drive supports DMA, use its mode, and 527 * put the other one in PIO mode 0 if mode not compatible 528 */ 529 if (drvp[0].drive_flags & DRIVE_DMA) { 530 mode[0] = drvp[0].DMA_mode; 531 mode[1] = drvp[1].PIO_mode; 532 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 533 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 534 mode[1] = drvp[1].PIO_mode = 0; 535 goto ok; 536 } 537 if (drvp[1].drive_flags & DRIVE_DMA) { 538 mode[1] = drvp[1].DMA_mode; 539 mode[0] = drvp[0].PIO_mode; 540 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 541 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 542 mode[0] = drvp[0].PIO_mode = 0; 543 goto ok; 544 } 545 /* 546 * If both drives are not DMA, takes the lower mode, unless 547 * one of them is PIO mode < 2 548 */ 549 if (drvp[0].PIO_mode < 2) { 550 mode[0] = drvp[0].PIO_mode = 0; 551 mode[1] = drvp[1].PIO_mode; 552 } else if (drvp[1].PIO_mode < 2) { 553 mode[1] = drvp[1].PIO_mode = 0; 554 mode[0] = drvp[0].PIO_mode; 555 } else { 556 mode[0] = mode[1] = 557 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 558 drvp[0].PIO_mode = mode[0]; 559 drvp[1].PIO_mode = mode[1]; 560 } 561 ok: /* The modes are setup */ 562 for (drive = 0; drive < 2; drive++) { 563 if (drvp[drive].drive_flags & DRIVE_DMA) { 564 idetim |= piix_setup_idetim_timings( 565 mode[drive], 1, chp->ch_channel); 566 goto end; 567 } 568 } 569 /* If we are there, none of the drives are DMA */ 570 if (mode[0] >= 2) 571 idetim |= piix_setup_idetim_timings( 572 mode[0], 0, chp->ch_channel); 573 else 574 idetim |= piix_setup_idetim_timings( 575 mode[1], 0, chp->ch_channel); 576 end: /* 577 * timing mode is now set up in the controller. Enable 578 * it per-drive 579 */ 580 for (drive = 0; drive < 2; drive++) { 581 /* If no drive, skip */ 582 if ((drvp[drive].drive_flags & DRIVE) == 0) 583 continue; 584 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 585 if (drvp[drive].drive_flags & DRIVE_DMA) 586 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 587 } 588 if (idedma_ctl != 0) { 589 /* Add software bits in status register */ 590 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 591 idedma_ctl); 592 } 593 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 594 } 595 596 static void 597 piix3_4_setup_channel(struct ata_channel *chp) 598 { 599 struct ata_drive_datas *drvp; 600 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 601 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 602 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 603 struct wdc_softc *wdc = &sc->sc_wdcdev; 604 int drive, s; 605 int channel = chp->ch_channel; 606 607 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 608 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 609 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 610 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 611 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 612 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 613 PIIX_SIDETIM_RTC_MASK(channel)); 614 idedma_ctl = 0; 615 616 /* set up new idetim: Enable IDE registers decode */ 617 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 618 619 /* setup DMA if needed */ 620 pciide_channel_dma_setup(cp); 621 622 for (drive = 0; drive < 2; drive++) { 623 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 624 PIIX_UDMATIM_SET(0x3, channel, drive)); 625 drvp = &chp->ch_drive[drive]; 626 /* If no drive, skip */ 627 if ((drvp->drive_flags & DRIVE) == 0) 628 continue; 629 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 630 (drvp->drive_flags & DRIVE_UDMA) == 0)) 631 goto pio; 632 633 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 636 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 637 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 638 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 639 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 640 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 641 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 642 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 643 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 644 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 645 ideconf |= PIIX_CONFIG_PINGPONG; 646 } 647 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 648 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 649 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 650 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 651 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 652 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 653 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 654 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 655 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 656 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 657 /* setup Ultra/100 */ 658 if (drvp->UDMA_mode > 2 && 659 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 660 drvp->UDMA_mode = 2; 661 if (drvp->UDMA_mode > 4) { 662 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 663 } else { 664 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 665 if (drvp->UDMA_mode > 2) { 666 ideconf |= PIIX_CONFIG_UDMA66(channel, 667 drive); 668 } else { 669 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 670 drive); 671 } 672 } 673 } 674 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 675 /* setup Ultra/66 */ 676 if (drvp->UDMA_mode > 2 && 677 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 678 drvp->UDMA_mode = 2; 679 if (drvp->UDMA_mode > 2) 680 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 681 else 682 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 683 } 684 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 685 (drvp->drive_flags & DRIVE_UDMA)) { 686 /* use Ultra/DMA */ 687 s = splbio(); 688 drvp->drive_flags &= ~DRIVE_DMA; 689 splx(s); 690 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 691 udmareg |= PIIX_UDMATIM_SET( 692 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 693 } else { 694 /* use Multiword DMA */ 695 s = splbio(); 696 drvp->drive_flags &= ~DRIVE_UDMA; 697 splx(s); 698 if (drive == 0) { 699 idetim |= piix_setup_idetim_timings( 700 drvp->DMA_mode, 1, channel); 701 } else { 702 sidetim |= piix_setup_sidetim_timings( 703 drvp->DMA_mode, 1, channel); 704 idetim =PIIX_IDETIM_SET(idetim, 705 PIIX_IDETIM_SITRE, channel); 706 } 707 } 708 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 709 710 pio: /* use PIO mode */ 711 idetim |= piix_setup_idetim_drvs(drvp); 712 if (drive == 0) { 713 idetim |= piix_setup_idetim_timings( 714 drvp->PIO_mode, 0, channel); 715 } else { 716 sidetim |= piix_setup_sidetim_timings( 717 drvp->PIO_mode, 0, channel); 718 idetim =PIIX_IDETIM_SET(idetim, 719 PIIX_IDETIM_SITRE, channel); 720 } 721 } 722 if (idedma_ctl != 0) { 723 /* Add software bits in status register */ 724 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 725 idedma_ctl); 726 } 727 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 728 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 729 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 730 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 731 } 732 733 734 /* setup ISP and RTC fields, based on mode */ 735 static u_int32_t 736 piix_setup_idetim_timings(mode, dma, channel) 737 u_int8_t mode; 738 u_int8_t dma; 739 u_int8_t channel; 740 { 741 742 if (dma) 743 return PIIX_IDETIM_SET(0, 744 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 745 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 746 channel); 747 else 748 return PIIX_IDETIM_SET(0, 749 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 750 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 751 channel); 752 } 753 754 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 755 static u_int32_t 756 piix_setup_idetim_drvs(drvp) 757 struct ata_drive_datas *drvp; 758 { 759 u_int32_t ret = 0; 760 struct ata_channel *chp = drvp->chnl_softc; 761 u_int8_t channel = chp->ch_channel; 762 u_int8_t drive = drvp->drive; 763 764 /* 765 * If drive is using UDMA, timings setups are independent 766 * So just check DMA and PIO here. 767 */ 768 if (drvp->drive_flags & DRIVE_DMA) { 769 /* if mode = DMA mode 0, use compatible timings */ 770 if ((drvp->drive_flags & DRIVE_DMA) && 771 drvp->DMA_mode == 0) { 772 drvp->PIO_mode = 0; 773 return ret; 774 } 775 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 776 /* 777 * PIO and DMA timings are the same, use fast timings for PIO 778 * too, else use compat timings. 779 */ 780 if ((piix_isp_pio[drvp->PIO_mode] != 781 piix_isp_dma[drvp->DMA_mode]) || 782 (piix_rtc_pio[drvp->PIO_mode] != 783 piix_rtc_dma[drvp->DMA_mode])) 784 drvp->PIO_mode = 0; 785 /* if PIO mode <= 2, use compat timings for PIO */ 786 if (drvp->PIO_mode <= 2) { 787 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 788 channel); 789 return ret; 790 } 791 } 792 793 /* 794 * Now setup PIO modes. If mode < 2, use compat timings. 795 * Else enable fast timings. Enable IORDY and prefetch/post 796 * if PIO mode >= 3. 797 */ 798 799 if (drvp->PIO_mode < 2) 800 return ret; 801 802 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 803 if (drvp->PIO_mode >= 3) { 804 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 805 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 806 } 807 return ret; 808 } 809 810 /* setup values in SIDETIM registers, based on mode */ 811 static u_int32_t 812 piix_setup_sidetim_timings(mode, dma, channel) 813 u_int8_t mode; 814 u_int8_t dma; 815 u_int8_t channel; 816 { 817 if (dma) 818 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 819 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 820 else 821 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 822 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 823 } 824 825 static void 826 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 827 { 828 struct pciide_channel *cp; 829 bus_size_t cmdsize, ctlsize; 830 pcireg_t interface, cmdsts; 831 int channel; 832 833 if (pciide_chipen(sc, pa) == 0) 834 return; 835 836 aprint_verbose("%s: bus-master DMA support present", 837 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 838 pciide_mapreg_dma(sc, pa); 839 aprint_verbose("\n"); 840 841 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 842 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 843 if (sc->sc_dma_ok) { 844 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 845 sc->sc_wdcdev.irqack = pciide_irqack; 846 /* Do all revisions require DMA alignment workaround? */ 847 sc->sc_wdcdev.dma_init = piix_dma_init; 848 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 849 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 850 } 851 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 852 853 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 854 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 855 856 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 857 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 858 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 859 860 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 861 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 862 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 863 864 interface = PCI_INTERFACE(pa->pa_class); 865 866 wdc_allocate_regs(&sc->sc_wdcdev); 867 868 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 869 channel++) { 870 cp = &sc->pciide_channels[channel]; 871 if (pciide_chansetup(sc, channel, interface) == 0) 872 continue; 873 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 874 pciide_pci_intr); 875 } 876 } 877 878 static int 879 piix_dma_init(void *v, int channel, int drive, void *databuf, 880 size_t datalen, int flags) 881 { 882 883 /* use PIO for unaligned transfer */ 884 if (((uintptr_t)databuf) & 0x1) 885 return EINVAL; 886 887 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 888 } 889
Indexes created Fri Oct 17 09:09:57 GMT 2025