piixide.c revision 1.37.14.2
1 /* $NetBSD: piixide.c,v 1.37.14.2 2007/09/03 16:48:23 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.37.14.2 2007/09/03 16:48:23 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static pnp_status_t piixide_power(device_t, pnp_request_t, void *); 54 static int piixide_match(struct device *, struct cfdata *, void *); 55 static void piixide_attach(struct device *, struct device *, void *); 56 57 static const struct pciide_product_desc pciide_intel_products[] = { 58 { PCI_PRODUCT_INTEL_82092AA, 59 0, 60 "Intel 82092AA IDE controller", 61 default_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371FB_IDE, 64 0, 65 "Intel 82371FB IDE controller (PIIX)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371SB_IDE, 69 0, 70 "Intel 82371SB IDE Interface (PIIX3)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82371AB_IDE, 74 0, 75 "Intel 82371AB IDE controller (PIIX4)", 76 piix_chip_map, 77 }, 78 { PCI_PRODUCT_INTEL_82440MX_IDE, 79 0, 80 "Intel 82440MX IDE controller", 81 piix_chip_map 82 }, 83 { PCI_PRODUCT_INTEL_82801AA_IDE, 84 0, 85 "Intel 82801AA IDE Controller (ICH)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801AB_IDE, 89 0, 90 "Intel 82801AB IDE Controller (ICH0)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BA_IDE, 94 0, 95 "Intel 82801BA IDE Controller (ICH2)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801BAM_IDE, 99 0, 100 "Intel 82801BAM IDE Controller (ICH2-M)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 109 0, 110 "Intel 82801CA IDE Controller (ICH3)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DB_IDE, 114 0, 115 "Intel 82801DB IDE Controller (ICH4)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801DBM_IDE, 119 0, 120 "Intel 82801DBM IDE Controller (ICH4-M)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_IDE, 124 0, 125 "Intel 82801EB IDE Controller (ICH5)", 126 piix_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801EB_SATA, 129 0, 130 "Intel 82801EB Serial ATA Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_82801ER_SATA, 134 0, 135 "Intel 82801ER Serial ATA/Raid Controller", 136 piixsata_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_IDE, 139 0, 140 "Intel 6300ESB IDE Controller (ICH5)", 141 piix_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_6300ESB_SATA, 144 0, 145 "Intel 6300ESB Serial ATA Controller", 146 piixsata_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_6300ESB_RAID, 149 0, 150 "Intel 6300ESB Serial ATA/RAID Controller", 151 piixsata_chip_map, 152 }, 153 { PCI_PRODUCT_INTEL_82801FB_IDE, 154 0, 155 "Intel 82801FB IDE Controller (ICH6)", 156 piix_chip_map, 157 }, 158 { PCI_PRODUCT_INTEL_82801FB_SATA, 159 0, 160 "Intel 82801FB Serial ATA/Raid Controller", 161 piixsata_chip_map, 162 }, 163 { PCI_PRODUCT_INTEL_82801FR_SATA, 164 0, 165 "Intel 82801FR Serial ATA/Raid Controller", 166 piixsata_chip_map, 167 }, 168 { PCI_PRODUCT_INTEL_82801FBM_SATA, 169 0, 170 "Intel 82801FBM Serial ATA Controller (ICH6)", 171 piixsata_chip_map, 172 }, 173 { PCI_PRODUCT_INTEL_82801G_IDE, 174 0, 175 "Intel 82801GB/GR IDE Controller (ICH7)", 176 piix_chip_map, 177 }, 178 { PCI_PRODUCT_INTEL_82801G_SATA, 179 0, 180 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 181 piixsata_chip_map, 182 }, 183 { PCI_PRODUCT_INTEL_82801GBM_SATA, 184 0, 185 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 186 piixsata_chip_map, 187 }, 188 { PCI_PRODUCT_INTEL_82801H_SATA_1, 189 0, 190 "Intel 82801H Serial ATA Controller (ICH8)", 191 piixsata_chip_map, 192 }, 193 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 194 0, 195 "Intel 82801H Serial ATA RAID Controller (ICH8)", 196 piixsata_chip_map, 197 }, 198 { PCI_PRODUCT_INTEL_82801H_SATA_2, 199 0, 200 "Intel 82801H Serial ATA Controller (ICH8)", 201 piixsata_chip_map, 202 }, 203 { PCI_PRODUCT_INTEL_82801HBM_IDE, 204 0, 205 "Intel 82801HBM IDE Controller (ICH8M)", 206 piix_chip_map, 207 }, 208 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 209 0, 210 "Intel 82801HBM Serial ATA Controller (ICH8M)", 211 piixsata_chip_map, 212 }, 213 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 214 0, 215 "Intel 82801HBM Serial ATA Controller (ICH8M)", 216 piixsata_chip_map, 217 }, 218 { PCI_PRODUCT_INTEL_63XXESB_IDE, 219 0, 220 "Intel 631xESB/632xESB IDE Controller", 221 piix_chip_map, 222 }, 223 { PCI_PRODUCT_INTEL_82801I_SATA_1, 224 0, 225 "Intel 82801I Serial ATA Controller (ICH9)", 226 piixsata_chip_map, 227 }, 228 { PCI_PRODUCT_INTEL_82801I_SATA_2, 229 0, 230 "Intel 82801I Serial ATA Controller (ICH9)", 231 piixsata_chip_map, 232 }, 233 { PCI_PRODUCT_INTEL_82801I_SATA_3, 234 0, 235 "Intel 82801I Serial ATA Controller (ICH9)", 236 piixsata_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_63XXESB_SATA, 239 0, 240 "Intel 631xESB/632xESB Serial ATA Controller", 241 piixsata_chip_map, 242 }, 243 { 0, 244 0, 245 NULL, 246 NULL 247 } 248 }; 249 250 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 251 piixide_match, piixide_attach, NULL, NULL); 252 253 static int 254 piixide_match(struct device *parent, struct cfdata *match, 255 void *aux) 256 { 257 struct pci_attach_args *pa = aux; 258 259 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 260 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 261 return (2); 262 } 263 return (0); 264 } 265 266 static void 267 piixide_attach(struct device *parent, struct device *self, void *aux) 268 { 269 struct pci_attach_args *pa = aux; 270 struct pciide_softc *sc = (struct pciide_softc *)self; 271 pnp_status_t status; 272 273 pciide_common_attach(sc, pa, 274 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 275 276 /* Setup our power handler */ 277 status = pnp_register(self, piixide_power); 278 if (status != PNP_STATUS_SUCCESS) 279 aprint_error("%s: couldn't establish power handler\n", 280 device_xname(self)); 281 } 282 283 static pnp_status_t 284 piixide_power(device_t dv, pnp_request_t req, void *aux) 285 { 286 struct pciide_softc *sc = (struct pciide_softc *)dv; 287 pnp_state_t *state; 288 pnp_capabilities_t *caps; 289 pcireg_t val; 290 int off; 291 292 switch (req) { 293 case PNP_REQUEST_GET_CAPABILITIES: 294 caps = (pnp_capabilities_t *)aux; 295 pci_get_capability(sc->sc_pc, sc->sc_tag, 296 PCI_CAP_PWRMGMT, &off, &val); 297 caps->state = pci_pnp_capabilities(val); 298 caps->state |= PNP_STATE_D0 | PNP_STATE_D3; 299 break; 300 case PNP_REQUEST_GET_STATE: 301 state = (pnp_state_t *)aux; 302 if (pci_get_powerstate(sc->sc_pc, sc->sc_tag, &val) != 0) 303 *state = PNP_STATE_D0; 304 else 305 *state = pci_pnp_powerstate(val); 306 break; 307 case PNP_REQUEST_SET_STATE: 308 state = (pnp_state_t *)aux; 309 310 switch (*state) { 311 case PNP_STATE_D3: 312 val = PCI_PMCSR_STATE_D3; 313 pci_conf_capture(sc->sc_pc, sc->sc_tag, 314 &sc->sc_pciconf); 315 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 316 PIIX_IDETIM); 317 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 318 PIIX_UDMATIM); 319 break; 320 case PNP_STATE_D0: 321 val = PCI_PMCSR_STATE_D0; 322 break; 323 default: 324 return PNP_STATUS_UNSUPPORTED; 325 } 326 327 (void)pci_set_powerstate(sc->sc_pc, sc->sc_tag, val); 328 329 if (*state != PNP_STATE_D0) 330 break; 331 332 pci_conf_restore(sc->sc_pc, sc->sc_tag, 333 &sc->sc_pciconf); 334 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 335 sc->sc_idetim); 336 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 337 sc->sc_udmatim); 338 break; 339 default: 340 return PNP_STATUS_UNSUPPORTED; 341 } 342 343 return PNP_STATUS_SUCCESS; 344 } 345 346 static void 347 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 348 { 349 struct pciide_channel *cp; 350 int channel; 351 u_int32_t idetim; 352 bus_size_t cmdsize, ctlsize; 353 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 354 355 if (pciide_chipen(sc, pa) == 0) 356 return; 357 358 aprint_verbose("%s: bus-master DMA support present", 359 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 360 pciide_mapreg_dma(sc, pa); 361 aprint_verbose("\n"); 362 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 363 if (sc->sc_dma_ok) { 364 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 365 sc->sc_wdcdev.irqack = pciide_irqack; 366 /* Do all revisions require DMA alignment workaround? */ 367 sc->sc_wdcdev.dma_init = piix_dma_init; 368 switch(sc->sc_pp->ide_product) { 369 case PCI_PRODUCT_INTEL_82371AB_IDE: 370 case PCI_PRODUCT_INTEL_82440MX_IDE: 371 case PCI_PRODUCT_INTEL_82801AA_IDE: 372 case PCI_PRODUCT_INTEL_82801AB_IDE: 373 case PCI_PRODUCT_INTEL_82801BA_IDE: 374 case PCI_PRODUCT_INTEL_82801BAM_IDE: 375 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 376 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 377 case PCI_PRODUCT_INTEL_82801DB_IDE: 378 case PCI_PRODUCT_INTEL_82801DBM_IDE: 379 case PCI_PRODUCT_INTEL_82801EB_IDE: 380 case PCI_PRODUCT_INTEL_6300ESB_IDE: 381 case PCI_PRODUCT_INTEL_82801FB_IDE: 382 case PCI_PRODUCT_INTEL_82801G_IDE: 383 case PCI_PRODUCT_INTEL_82801HBM_IDE: 384 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 385 } 386 } 387 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 388 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 389 switch(sc->sc_pp->ide_product) { 390 case PCI_PRODUCT_INTEL_82801AA_IDE: 391 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 392 break; 393 case PCI_PRODUCT_INTEL_82801BA_IDE: 394 case PCI_PRODUCT_INTEL_82801BAM_IDE: 395 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 396 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 397 case PCI_PRODUCT_INTEL_82801DB_IDE: 398 case PCI_PRODUCT_INTEL_82801DBM_IDE: 399 case PCI_PRODUCT_INTEL_82801EB_IDE: 400 case PCI_PRODUCT_INTEL_6300ESB_IDE: 401 case PCI_PRODUCT_INTEL_82801FB_IDE: 402 case PCI_PRODUCT_INTEL_82801G_IDE: 403 case PCI_PRODUCT_INTEL_82801HBM_IDE: 404 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 405 break; 406 default: 407 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 408 } 409 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 410 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 411 else 412 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 413 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 414 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 415 416 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 417 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 418 DEBUG_PROBE); 419 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 420 ATADEBUG_PRINT((", sidetim=0x%x", 421 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 422 DEBUG_PROBE); 423 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 424 ATADEBUG_PRINT((", udamreg 0x%x", 425 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 426 DEBUG_PROBE); 427 } 428 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 429 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 430 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 431 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 432 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 433 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 434 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 435 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 436 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 437 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 438 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 439 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 440 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 441 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 442 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 443 DEBUG_PROBE); 444 } 445 446 } 447 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 448 449 wdc_allocate_regs(&sc->sc_wdcdev); 450 451 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 452 channel++) { 453 cp = &sc->pciide_channels[channel]; 454 if (pciide_chansetup(sc, channel, interface) == 0) 455 continue; 456 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 457 if ((PIIX_IDETIM_READ(idetim, channel) & 458 PIIX_IDETIM_IDE) == 0) { 459 #if 1 460 aprint_normal("%s: %s channel ignored (disabled)\n", 461 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 462 cp->ata_channel.ch_flags |= ATACH_DISABLED; 463 continue; 464 #else 465 pcireg_t interface; 466 467 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 468 channel); 469 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 470 idetim); 471 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 472 sc->sc_tag, PCI_CLASS_REG)); 473 aprint_normal("channel %d idetim=%08x interface=%02x\n", 474 channel, idetim, interface); 475 #endif 476 } 477 pciide_mapchan(pa, cp, interface, 478 &cmdsize, &ctlsize, pciide_pci_intr); 479 } 480 481 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 482 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 483 DEBUG_PROBE); 484 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 485 ATADEBUG_PRINT((", sidetim=0x%x", 486 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 487 DEBUG_PROBE); 488 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 489 ATADEBUG_PRINT((", udamreg 0x%x", 490 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 491 DEBUG_PROBE); 492 } 493 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 494 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 495 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 496 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 497 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 498 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 499 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 500 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 501 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 502 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 503 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 504 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 505 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 506 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 507 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 508 DEBUG_PROBE); 509 } 510 } 511 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 512 } 513 514 static void 515 piix_setup_channel(struct ata_channel *chp) 516 { 517 u_int8_t mode[2], drive; 518 u_int32_t oidetim, idetim, idedma_ctl; 519 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 520 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 521 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 522 523 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 524 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 525 idedma_ctl = 0; 526 527 /* set up new idetim: Enable IDE registers decode */ 528 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 529 chp->ch_channel); 530 531 /* setup DMA */ 532 pciide_channel_dma_setup(cp); 533 534 /* 535 * Here we have to mess up with drives mode: PIIX can't have 536 * different timings for master and slave drives. 537 * We need to find the best combination. 538 */ 539 540 /* If both drives supports DMA, take the lower mode */ 541 if ((drvp[0].drive_flags & DRIVE_DMA) && 542 (drvp[1].drive_flags & DRIVE_DMA)) { 543 mode[0] = mode[1] = 544 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 545 drvp[0].DMA_mode = mode[0]; 546 drvp[1].DMA_mode = mode[1]; 547 goto ok; 548 } 549 /* 550 * If only one drive supports DMA, use its mode, and 551 * put the other one in PIO mode 0 if mode not compatible 552 */ 553 if (drvp[0].drive_flags & DRIVE_DMA) { 554 mode[0] = drvp[0].DMA_mode; 555 mode[1] = drvp[1].PIO_mode; 556 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 557 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 558 mode[1] = drvp[1].PIO_mode = 0; 559 goto ok; 560 } 561 if (drvp[1].drive_flags & DRIVE_DMA) { 562 mode[1] = drvp[1].DMA_mode; 563 mode[0] = drvp[0].PIO_mode; 564 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 565 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 566 mode[0] = drvp[0].PIO_mode = 0; 567 goto ok; 568 } 569 /* 570 * If both drives are not DMA, takes the lower mode, unless 571 * one of them is PIO mode < 2 572 */ 573 if (drvp[0].PIO_mode < 2) { 574 mode[0] = drvp[0].PIO_mode = 0; 575 mode[1] = drvp[1].PIO_mode; 576 } else if (drvp[1].PIO_mode < 2) { 577 mode[1] = drvp[1].PIO_mode = 0; 578 mode[0] = drvp[0].PIO_mode; 579 } else { 580 mode[0] = mode[1] = 581 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 582 drvp[0].PIO_mode = mode[0]; 583 drvp[1].PIO_mode = mode[1]; 584 } 585 ok: /* The modes are setup */ 586 for (drive = 0; drive < 2; drive++) { 587 if (drvp[drive].drive_flags & DRIVE_DMA) { 588 idetim |= piix_setup_idetim_timings( 589 mode[drive], 1, chp->ch_channel); 590 goto end; 591 } 592 } 593 /* If we are there, none of the drives are DMA */ 594 if (mode[0] >= 2) 595 idetim |= piix_setup_idetim_timings( 596 mode[0], 0, chp->ch_channel); 597 else 598 idetim |= piix_setup_idetim_timings( 599 mode[1], 0, chp->ch_channel); 600 end: /* 601 * timing mode is now set up in the controller. Enable 602 * it per-drive 603 */ 604 for (drive = 0; drive < 2; drive++) { 605 /* If no drive, skip */ 606 if ((drvp[drive].drive_flags & DRIVE) == 0) 607 continue; 608 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 609 if (drvp[drive].drive_flags & DRIVE_DMA) 610 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 611 } 612 if (idedma_ctl != 0) { 613 /* Add software bits in status register */ 614 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 615 idedma_ctl); 616 } 617 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 618 } 619 620 static void 621 piix3_4_setup_channel(struct ata_channel *chp) 622 { 623 struct ata_drive_datas *drvp; 624 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 625 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 626 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 627 struct wdc_softc *wdc = &sc->sc_wdcdev; 628 int drive, s; 629 int channel = chp->ch_channel; 630 631 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 632 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 633 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 634 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 635 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 636 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 637 PIIX_SIDETIM_RTC_MASK(channel)); 638 idedma_ctl = 0; 639 640 /* set up new idetim: Enable IDE registers decode */ 641 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 642 643 /* setup DMA if needed */ 644 pciide_channel_dma_setup(cp); 645 646 for (drive = 0; drive < 2; drive++) { 647 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 648 PIIX_UDMATIM_SET(0x3, channel, drive)); 649 drvp = &chp->ch_drive[drive]; 650 /* If no drive, skip */ 651 if ((drvp->drive_flags & DRIVE) == 0) 652 continue; 653 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 654 (drvp->drive_flags & DRIVE_UDMA) == 0)) 655 goto pio; 656 657 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 658 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 659 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 660 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 661 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 662 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 663 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 664 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 665 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 666 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 667 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 668 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 669 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 670 ideconf |= PIIX_CONFIG_PINGPONG; 671 } 672 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 673 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 674 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 675 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 676 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 677 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 678 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 679 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 680 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 681 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 682 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 683 /* setup Ultra/100 */ 684 if (drvp->UDMA_mode > 2 && 685 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 686 drvp->UDMA_mode = 2; 687 if (drvp->UDMA_mode > 4) { 688 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 689 } else { 690 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 691 if (drvp->UDMA_mode > 2) { 692 ideconf |= PIIX_CONFIG_UDMA66(channel, 693 drive); 694 } else { 695 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 696 drive); 697 } 698 } 699 } 700 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 701 /* setup Ultra/66 */ 702 if (drvp->UDMA_mode > 2 && 703 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 704 drvp->UDMA_mode = 2; 705 if (drvp->UDMA_mode > 2) 706 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 707 else 708 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 709 } 710 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 711 (drvp->drive_flags & DRIVE_UDMA)) { 712 /* use Ultra/DMA */ 713 s = splbio(); 714 drvp->drive_flags &= ~DRIVE_DMA; 715 splx(s); 716 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 717 udmareg |= PIIX_UDMATIM_SET( 718 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 719 } else { 720 /* use Multiword DMA */ 721 s = splbio(); 722 drvp->drive_flags &= ~DRIVE_UDMA; 723 splx(s); 724 if (drive == 0) { 725 idetim |= piix_setup_idetim_timings( 726 drvp->DMA_mode, 1, channel); 727 } else { 728 sidetim |= piix_setup_sidetim_timings( 729 drvp->DMA_mode, 1, channel); 730 idetim =PIIX_IDETIM_SET(idetim, 731 PIIX_IDETIM_SITRE, channel); 732 } 733 } 734 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 735 736 pio: /* use PIO mode */ 737 idetim |= piix_setup_idetim_drvs(drvp); 738 if (drive == 0) { 739 idetim |= piix_setup_idetim_timings( 740 drvp->PIO_mode, 0, channel); 741 } else { 742 sidetim |= piix_setup_sidetim_timings( 743 drvp->PIO_mode, 0, channel); 744 idetim =PIIX_IDETIM_SET(idetim, 745 PIIX_IDETIM_SITRE, channel); 746 } 747 } 748 if (idedma_ctl != 0) { 749 /* Add software bits in status register */ 750 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 751 idedma_ctl); 752 } 753 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 754 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 755 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 756 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 757 } 758 759 760 /* setup ISP and RTC fields, based on mode */ 761 static u_int32_t 762 piix_setup_idetim_timings(mode, dma, channel) 763 u_int8_t mode; 764 u_int8_t dma; 765 u_int8_t channel; 766 { 767 768 if (dma) 769 return PIIX_IDETIM_SET(0, 770 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 771 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 772 channel); 773 else 774 return PIIX_IDETIM_SET(0, 775 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 776 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 777 channel); 778 } 779 780 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 781 static u_int32_t 782 piix_setup_idetim_drvs(drvp) 783 struct ata_drive_datas *drvp; 784 { 785 u_int32_t ret = 0; 786 struct ata_channel *chp = drvp->chnl_softc; 787 u_int8_t channel = chp->ch_channel; 788 u_int8_t drive = drvp->drive; 789 790 /* 791 * If drive is using UDMA, timings setups are independent 792 * So just check DMA and PIO here. 793 */ 794 if (drvp->drive_flags & DRIVE_DMA) { 795 /* if mode = DMA mode 0, use compatible timings */ 796 if ((drvp->drive_flags & DRIVE_DMA) && 797 drvp->DMA_mode == 0) { 798 drvp->PIO_mode = 0; 799 return ret; 800 } 801 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 802 /* 803 * PIO and DMA timings are the same, use fast timings for PIO 804 * too, else use compat timings. 805 */ 806 if ((piix_isp_pio[drvp->PIO_mode] != 807 piix_isp_dma[drvp->DMA_mode]) || 808 (piix_rtc_pio[drvp->PIO_mode] != 809 piix_rtc_dma[drvp->DMA_mode])) 810 drvp->PIO_mode = 0; 811 /* if PIO mode <= 2, use compat timings for PIO */ 812 if (drvp->PIO_mode <= 2) { 813 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 814 channel); 815 return ret; 816 } 817 } 818 819 /* 820 * Now setup PIO modes. If mode < 2, use compat timings. 821 * Else enable fast timings. Enable IORDY and prefetch/post 822 * if PIO mode >= 3. 823 */ 824 825 if (drvp->PIO_mode < 2) 826 return ret; 827 828 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 829 if (drvp->PIO_mode >= 3) { 830 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 831 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 832 } 833 return ret; 834 } 835 836 /* setup values in SIDETIM registers, based on mode */ 837 static u_int32_t 838 piix_setup_sidetim_timings(mode, dma, channel) 839 u_int8_t mode; 840 u_int8_t dma; 841 u_int8_t channel; 842 { 843 if (dma) 844 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 845 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 846 else 847 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 848 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 849 } 850 851 static void 852 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 853 { 854 struct pciide_channel *cp; 855 bus_size_t cmdsize, ctlsize; 856 pcireg_t interface, cmdsts; 857 int channel; 858 859 if (pciide_chipen(sc, pa) == 0) 860 return; 861 862 aprint_verbose("%s: bus-master DMA support present", 863 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 864 pciide_mapreg_dma(sc, pa); 865 aprint_verbose("\n"); 866 867 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 868 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 869 if (sc->sc_dma_ok) { 870 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 871 sc->sc_wdcdev.irqack = pciide_irqack; 872 /* Do all revisions require DMA alignment workaround? */ 873 sc->sc_wdcdev.dma_init = piix_dma_init; 874 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 875 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 876 } 877 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 878 879 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 880 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 881 882 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 883 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 884 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 885 886 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 887 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 888 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 889 890 interface = PCI_INTERFACE(pa->pa_class); 891 892 wdc_allocate_regs(&sc->sc_wdcdev); 893 894 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 895 channel++) { 896 cp = &sc->pciide_channels[channel]; 897 if (pciide_chansetup(sc, channel, interface) == 0) 898 continue; 899 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 900 pciide_pci_intr); 901 } 902 } 903 904 static int 905 piix_dma_init(void *v, int channel, int drive, void *databuf, 906 size_t datalen, int flags) 907 { 908 909 /* use PIO for unaligned transfer */ 910 if (((uintptr_t)databuf) & 0x1) 911 return EINVAL; 912 913 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 914 } 915
Indexes created Mon Oct 20 05:10:11 GMT 2025