piixide.c revision 1.37.14.3
1 /* $NetBSD: piixide.c,v 1.37.14.3 2007/10/01 05:37:54 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.37.14.3 2007/10/01 05:37:54 joerg Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static void piixide_resume(device_t); 54 static void piixide_suspend(device_t); 55 static int piixide_match(struct device *, struct cfdata *, void *); 56 static void piixide_attach(struct device *, struct device *, void *); 57 58 static const struct pciide_product_desc pciide_intel_products[] = { 59 { PCI_PRODUCT_INTEL_82092AA, 60 0, 61 "Intel 82092AA IDE controller", 62 default_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371FB_IDE, 65 0, 66 "Intel 82371FB IDE controller (PIIX)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371SB_IDE, 70 0, 71 "Intel 82371SB IDE Interface (PIIX3)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82371AB_IDE, 75 0, 76 "Intel 82371AB IDE controller (PIIX4)", 77 piix_chip_map, 78 }, 79 { PCI_PRODUCT_INTEL_82440MX_IDE, 80 0, 81 "Intel 82440MX IDE controller", 82 piix_chip_map 83 }, 84 { PCI_PRODUCT_INTEL_82801AA_IDE, 85 0, 86 "Intel 82801AA IDE Controller (ICH)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801AB_IDE, 90 0, 91 "Intel 82801AB IDE Controller (ICH0)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BA_IDE, 95 0, 96 "Intel 82801BA IDE Controller (ICH2)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801BAM_IDE, 100 0, 101 "Intel 82801BAM IDE Controller (ICH2-M)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 110 0, 111 "Intel 82801CA IDE Controller (ICH3)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DB_IDE, 115 0, 116 "Intel 82801DB IDE Controller (ICH4)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801DBM_IDE, 120 0, 121 "Intel 82801DBM IDE Controller (ICH4-M)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_IDE, 125 0, 126 "Intel 82801EB IDE Controller (ICH5)", 127 piix_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801EB_SATA, 130 0, 131 "Intel 82801EB Serial ATA Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_82801ER_SATA, 135 0, 136 "Intel 82801ER Serial ATA/Raid Controller", 137 piixsata_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_IDE, 140 0, 141 "Intel 6300ESB IDE Controller (ICH5)", 142 piix_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_6300ESB_SATA, 145 0, 146 "Intel 6300ESB Serial ATA Controller", 147 piixsata_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_6300ESB_RAID, 150 0, 151 "Intel 6300ESB Serial ATA/RAID Controller", 152 piixsata_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FB_IDE, 155 0, 156 "Intel 82801FB IDE Controller (ICH6)", 157 piix_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FB_SATA, 160 0, 161 "Intel 82801FB Serial ATA/Raid Controller", 162 piixsata_chip_map, 163 }, 164 { PCI_PRODUCT_INTEL_82801FR_SATA, 165 0, 166 "Intel 82801FR Serial ATA/Raid Controller", 167 piixsata_chip_map, 168 }, 169 { PCI_PRODUCT_INTEL_82801FBM_SATA, 170 0, 171 "Intel 82801FBM Serial ATA Controller (ICH6)", 172 piixsata_chip_map, 173 }, 174 { PCI_PRODUCT_INTEL_82801G_IDE, 175 0, 176 "Intel 82801GB/GR IDE Controller (ICH7)", 177 piix_chip_map, 178 }, 179 { PCI_PRODUCT_INTEL_82801G_SATA, 180 0, 181 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 182 piixsata_chip_map, 183 }, 184 { PCI_PRODUCT_INTEL_82801GBM_SATA, 185 0, 186 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 187 piixsata_chip_map, 188 }, 189 { PCI_PRODUCT_INTEL_82801H_SATA_1, 190 0, 191 "Intel 82801H Serial ATA Controller (ICH8)", 192 piixsata_chip_map, 193 }, 194 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 195 0, 196 "Intel 82801H Serial ATA RAID Controller (ICH8)", 197 piixsata_chip_map, 198 }, 199 { PCI_PRODUCT_INTEL_82801H_SATA_2, 200 0, 201 "Intel 82801H Serial ATA Controller (ICH8)", 202 piixsata_chip_map, 203 }, 204 { PCI_PRODUCT_INTEL_82801HBM_IDE, 205 0, 206 "Intel 82801HBM IDE Controller (ICH8M)", 207 piix_chip_map, 208 }, 209 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 210 0, 211 "Intel 82801HBM Serial ATA Controller (ICH8M)", 212 piixsata_chip_map, 213 }, 214 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 215 0, 216 "Intel 82801HBM Serial ATA Controller (ICH8M)", 217 piixsata_chip_map, 218 }, 219 { PCI_PRODUCT_INTEL_63XXESB_IDE, 220 0, 221 "Intel 631xESB/632xESB IDE Controller", 222 piix_chip_map, 223 }, 224 { PCI_PRODUCT_INTEL_82801I_SATA_1, 225 0, 226 "Intel 82801I Serial ATA Controller (ICH9)", 227 piixsata_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82801I_SATA_2, 230 0, 231 "Intel 82801I Serial ATA Controller (ICH9)", 232 piixsata_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82801I_SATA_3, 235 0, 236 "Intel 82801I Serial ATA Controller (ICH9)", 237 piixsata_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_63XXESB_SATA, 240 0, 241 "Intel 631xESB/632xESB Serial ATA Controller", 242 piixsata_chip_map, 243 }, 244 { 0, 245 0, 246 NULL, 247 NULL 248 } 249 }; 250 251 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 252 piixide_match, piixide_attach, NULL, NULL); 253 254 static int 255 piixide_match(struct device *parent, struct cfdata *match, 256 void *aux) 257 { 258 struct pci_attach_args *pa = aux; 259 260 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 261 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 262 return (2); 263 } 264 return (0); 265 } 266 267 static void 268 piixide_attach(struct device *parent, struct device *self, void *aux) 269 { 270 struct pci_attach_args *pa = aux; 271 struct pciide_softc *sc = (struct pciide_softc *)self; 272 pnp_status_t status; 273 274 pciide_common_attach(sc, pa, 275 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 276 277 status = pci_generic_power_register(self, pa->pa_pc, pa->pa_tag, 278 piixide_suspend, piixide_resume); 279 if (status != PNP_STATUS_SUCCESS) { 280 aprint_error("%s: couldn't establish power handler\n", 281 device_xname(self)); 282 } 283 } 284 285 static void 286 piixide_resume(device_t dv) 287 { 288 struct pciide_softc *sc = device_private(dv); 289 290 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 291 sc->sc_idetim); 292 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 293 sc->sc_udmatim); 294 } 295 296 static void 297 piixide_suspend(device_t dv) 298 { 299 struct pciide_softc *sc = device_private(dv); 300 301 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 302 PIIX_IDETIM); 303 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 304 PIIX_UDMATIM); 305 } 306 307 static void 308 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 309 { 310 struct pciide_channel *cp; 311 int channel; 312 u_int32_t idetim; 313 bus_size_t cmdsize, ctlsize; 314 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 315 316 if (pciide_chipen(sc, pa) == 0) 317 return; 318 319 aprint_verbose("%s: bus-master DMA support present", 320 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 321 pciide_mapreg_dma(sc, pa); 322 aprint_verbose("\n"); 323 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 324 if (sc->sc_dma_ok) { 325 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 326 sc->sc_wdcdev.irqack = pciide_irqack; 327 /* Do all revisions require DMA alignment workaround? */ 328 sc->sc_wdcdev.dma_init = piix_dma_init; 329 switch(sc->sc_pp->ide_product) { 330 case PCI_PRODUCT_INTEL_82371AB_IDE: 331 case PCI_PRODUCT_INTEL_82440MX_IDE: 332 case PCI_PRODUCT_INTEL_82801AA_IDE: 333 case PCI_PRODUCT_INTEL_82801AB_IDE: 334 case PCI_PRODUCT_INTEL_82801BA_IDE: 335 case PCI_PRODUCT_INTEL_82801BAM_IDE: 336 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 337 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 338 case PCI_PRODUCT_INTEL_82801DB_IDE: 339 case PCI_PRODUCT_INTEL_82801DBM_IDE: 340 case PCI_PRODUCT_INTEL_82801EB_IDE: 341 case PCI_PRODUCT_INTEL_6300ESB_IDE: 342 case PCI_PRODUCT_INTEL_82801FB_IDE: 343 case PCI_PRODUCT_INTEL_82801G_IDE: 344 case PCI_PRODUCT_INTEL_82801HBM_IDE: 345 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 346 } 347 } 348 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 349 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 350 switch(sc->sc_pp->ide_product) { 351 case PCI_PRODUCT_INTEL_82801AA_IDE: 352 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 353 break; 354 case PCI_PRODUCT_INTEL_82801BA_IDE: 355 case PCI_PRODUCT_INTEL_82801BAM_IDE: 356 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 357 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 358 case PCI_PRODUCT_INTEL_82801DB_IDE: 359 case PCI_PRODUCT_INTEL_82801DBM_IDE: 360 case PCI_PRODUCT_INTEL_82801EB_IDE: 361 case PCI_PRODUCT_INTEL_6300ESB_IDE: 362 case PCI_PRODUCT_INTEL_82801FB_IDE: 363 case PCI_PRODUCT_INTEL_82801G_IDE: 364 case PCI_PRODUCT_INTEL_82801HBM_IDE: 365 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 366 break; 367 default: 368 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 369 } 370 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 371 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 372 else 373 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 374 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 375 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 376 377 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 378 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 379 DEBUG_PROBE); 380 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 381 ATADEBUG_PRINT((", sidetim=0x%x", 382 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 383 DEBUG_PROBE); 384 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 385 ATADEBUG_PRINT((", udamreg 0x%x", 386 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 387 DEBUG_PROBE); 388 } 389 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 390 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 391 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 392 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 393 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 394 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 395 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 396 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 397 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 398 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 400 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 402 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 403 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 404 DEBUG_PROBE); 405 } 406 407 } 408 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 409 410 wdc_allocate_regs(&sc->sc_wdcdev); 411 412 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 413 channel++) { 414 cp = &sc->pciide_channels[channel]; 415 if (pciide_chansetup(sc, channel, interface) == 0) 416 continue; 417 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 418 if ((PIIX_IDETIM_READ(idetim, channel) & 419 PIIX_IDETIM_IDE) == 0) { 420 #if 1 421 aprint_normal("%s: %s channel ignored (disabled)\n", 422 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 423 cp->ata_channel.ch_flags |= ATACH_DISABLED; 424 continue; 425 #else 426 pcireg_t interface; 427 428 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 429 channel); 430 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 431 idetim); 432 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 433 sc->sc_tag, PCI_CLASS_REG)); 434 aprint_normal("channel %d idetim=%08x interface=%02x\n", 435 channel, idetim, interface); 436 #endif 437 } 438 pciide_mapchan(pa, cp, interface, 439 &cmdsize, &ctlsize, pciide_pci_intr); 440 } 441 442 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 443 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 444 DEBUG_PROBE); 445 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 446 ATADEBUG_PRINT((", sidetim=0x%x", 447 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 448 DEBUG_PROBE); 449 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 450 ATADEBUG_PRINT((", udamreg 0x%x", 451 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 452 DEBUG_PROBE); 453 } 454 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 455 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 456 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 457 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 458 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 459 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 460 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 461 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 462 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 467 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 468 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 469 DEBUG_PROBE); 470 } 471 } 472 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 473 } 474 475 static void 476 piix_setup_channel(struct ata_channel *chp) 477 { 478 u_int8_t mode[2], drive; 479 u_int32_t oidetim, idetim, idedma_ctl; 480 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 481 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 482 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 483 484 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 485 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 486 idedma_ctl = 0; 487 488 /* set up new idetim: Enable IDE registers decode */ 489 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 490 chp->ch_channel); 491 492 /* setup DMA */ 493 pciide_channel_dma_setup(cp); 494 495 /* 496 * Here we have to mess up with drives mode: PIIX can't have 497 * different timings for master and slave drives. 498 * We need to find the best combination. 499 */ 500 501 /* If both drives supports DMA, take the lower mode */ 502 if ((drvp[0].drive_flags & DRIVE_DMA) && 503 (drvp[1].drive_flags & DRIVE_DMA)) { 504 mode[0] = mode[1] = 505 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 506 drvp[0].DMA_mode = mode[0]; 507 drvp[1].DMA_mode = mode[1]; 508 goto ok; 509 } 510 /* 511 * If only one drive supports DMA, use its mode, and 512 * put the other one in PIO mode 0 if mode not compatible 513 */ 514 if (drvp[0].drive_flags & DRIVE_DMA) { 515 mode[0] = drvp[0].DMA_mode; 516 mode[1] = drvp[1].PIO_mode; 517 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 518 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 519 mode[1] = drvp[1].PIO_mode = 0; 520 goto ok; 521 } 522 if (drvp[1].drive_flags & DRIVE_DMA) { 523 mode[1] = drvp[1].DMA_mode; 524 mode[0] = drvp[0].PIO_mode; 525 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 526 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 527 mode[0] = drvp[0].PIO_mode = 0; 528 goto ok; 529 } 530 /* 531 * If both drives are not DMA, takes the lower mode, unless 532 * one of them is PIO mode < 2 533 */ 534 if (drvp[0].PIO_mode < 2) { 535 mode[0] = drvp[0].PIO_mode = 0; 536 mode[1] = drvp[1].PIO_mode; 537 } else if (drvp[1].PIO_mode < 2) { 538 mode[1] = drvp[1].PIO_mode = 0; 539 mode[0] = drvp[0].PIO_mode; 540 } else { 541 mode[0] = mode[1] = 542 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 543 drvp[0].PIO_mode = mode[0]; 544 drvp[1].PIO_mode = mode[1]; 545 } 546 ok: /* The modes are setup */ 547 for (drive = 0; drive < 2; drive++) { 548 if (drvp[drive].drive_flags & DRIVE_DMA) { 549 idetim |= piix_setup_idetim_timings( 550 mode[drive], 1, chp->ch_channel); 551 goto end; 552 } 553 } 554 /* If we are there, none of the drives are DMA */ 555 if (mode[0] >= 2) 556 idetim |= piix_setup_idetim_timings( 557 mode[0], 0, chp->ch_channel); 558 else 559 idetim |= piix_setup_idetim_timings( 560 mode[1], 0, chp->ch_channel); 561 end: /* 562 * timing mode is now set up in the controller. Enable 563 * it per-drive 564 */ 565 for (drive = 0; drive < 2; drive++) { 566 /* If no drive, skip */ 567 if ((drvp[drive].drive_flags & DRIVE) == 0) 568 continue; 569 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 570 if (drvp[drive].drive_flags & DRIVE_DMA) 571 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 572 } 573 if (idedma_ctl != 0) { 574 /* Add software bits in status register */ 575 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 576 idedma_ctl); 577 } 578 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 579 } 580 581 static void 582 piix3_4_setup_channel(struct ata_channel *chp) 583 { 584 struct ata_drive_datas *drvp; 585 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 586 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 587 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 588 struct wdc_softc *wdc = &sc->sc_wdcdev; 589 int drive, s; 590 int channel = chp->ch_channel; 591 592 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 593 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 594 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 595 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 596 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 597 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 598 PIIX_SIDETIM_RTC_MASK(channel)); 599 idedma_ctl = 0; 600 601 /* set up new idetim: Enable IDE registers decode */ 602 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 603 604 /* setup DMA if needed */ 605 pciide_channel_dma_setup(cp); 606 607 for (drive = 0; drive < 2; drive++) { 608 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 609 PIIX_UDMATIM_SET(0x3, channel, drive)); 610 drvp = &chp->ch_drive[drive]; 611 /* If no drive, skip */ 612 if ((drvp->drive_flags & DRIVE) == 0) 613 continue; 614 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 615 (drvp->drive_flags & DRIVE_UDMA) == 0)) 616 goto pio; 617 618 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 619 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 620 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 621 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 622 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 623 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 624 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 625 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 626 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 631 ideconf |= PIIX_CONFIG_PINGPONG; 632 } 633 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 636 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 637 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 638 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 639 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 640 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 641 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 642 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 643 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 644 /* setup Ultra/100 */ 645 if (drvp->UDMA_mode > 2 && 646 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 647 drvp->UDMA_mode = 2; 648 if (drvp->UDMA_mode > 4) { 649 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 650 } else { 651 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 652 if (drvp->UDMA_mode > 2) { 653 ideconf |= PIIX_CONFIG_UDMA66(channel, 654 drive); 655 } else { 656 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 657 drive); 658 } 659 } 660 } 661 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 662 /* setup Ultra/66 */ 663 if (drvp->UDMA_mode > 2 && 664 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 665 drvp->UDMA_mode = 2; 666 if (drvp->UDMA_mode > 2) 667 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 668 else 669 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 670 } 671 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 672 (drvp->drive_flags & DRIVE_UDMA)) { 673 /* use Ultra/DMA */ 674 s = splbio(); 675 drvp->drive_flags &= ~DRIVE_DMA; 676 splx(s); 677 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 678 udmareg |= PIIX_UDMATIM_SET( 679 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 680 } else { 681 /* use Multiword DMA */ 682 s = splbio(); 683 drvp->drive_flags &= ~DRIVE_UDMA; 684 splx(s); 685 if (drive == 0) { 686 idetim |= piix_setup_idetim_timings( 687 drvp->DMA_mode, 1, channel); 688 } else { 689 sidetim |= piix_setup_sidetim_timings( 690 drvp->DMA_mode, 1, channel); 691 idetim =PIIX_IDETIM_SET(idetim, 692 PIIX_IDETIM_SITRE, channel); 693 } 694 } 695 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 696 697 pio: /* use PIO mode */ 698 idetim |= piix_setup_idetim_drvs(drvp); 699 if (drive == 0) { 700 idetim |= piix_setup_idetim_timings( 701 drvp->PIO_mode, 0, channel); 702 } else { 703 sidetim |= piix_setup_sidetim_timings( 704 drvp->PIO_mode, 0, channel); 705 idetim =PIIX_IDETIM_SET(idetim, 706 PIIX_IDETIM_SITRE, channel); 707 } 708 } 709 if (idedma_ctl != 0) { 710 /* Add software bits in status register */ 711 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 712 idedma_ctl); 713 } 714 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 715 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 716 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 717 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 718 } 719 720 721 /* setup ISP and RTC fields, based on mode */ 722 static u_int32_t 723 piix_setup_idetim_timings(mode, dma, channel) 724 u_int8_t mode; 725 u_int8_t dma; 726 u_int8_t channel; 727 { 728 729 if (dma) 730 return PIIX_IDETIM_SET(0, 731 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 732 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 733 channel); 734 else 735 return PIIX_IDETIM_SET(0, 736 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 737 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 738 channel); 739 } 740 741 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 742 static u_int32_t 743 piix_setup_idetim_drvs(drvp) 744 struct ata_drive_datas *drvp; 745 { 746 u_int32_t ret = 0; 747 struct ata_channel *chp = drvp->chnl_softc; 748 u_int8_t channel = chp->ch_channel; 749 u_int8_t drive = drvp->drive; 750 751 /* 752 * If drive is using UDMA, timings setups are independent 753 * So just check DMA and PIO here. 754 */ 755 if (drvp->drive_flags & DRIVE_DMA) { 756 /* if mode = DMA mode 0, use compatible timings */ 757 if ((drvp->drive_flags & DRIVE_DMA) && 758 drvp->DMA_mode == 0) { 759 drvp->PIO_mode = 0; 760 return ret; 761 } 762 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 763 /* 764 * PIO and DMA timings are the same, use fast timings for PIO 765 * too, else use compat timings. 766 */ 767 if ((piix_isp_pio[drvp->PIO_mode] != 768 piix_isp_dma[drvp->DMA_mode]) || 769 (piix_rtc_pio[drvp->PIO_mode] != 770 piix_rtc_dma[drvp->DMA_mode])) 771 drvp->PIO_mode = 0; 772 /* if PIO mode <= 2, use compat timings for PIO */ 773 if (drvp->PIO_mode <= 2) { 774 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 775 channel); 776 return ret; 777 } 778 } 779 780 /* 781 * Now setup PIO modes. If mode < 2, use compat timings. 782 * Else enable fast timings. Enable IORDY and prefetch/post 783 * if PIO mode >= 3. 784 */ 785 786 if (drvp->PIO_mode < 2) 787 return ret; 788 789 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 790 if (drvp->PIO_mode >= 3) { 791 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 792 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 793 } 794 return ret; 795 } 796 797 /* setup values in SIDETIM registers, based on mode */ 798 static u_int32_t 799 piix_setup_sidetim_timings(mode, dma, channel) 800 u_int8_t mode; 801 u_int8_t dma; 802 u_int8_t channel; 803 { 804 if (dma) 805 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 806 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 807 else 808 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 809 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 810 } 811 812 static void 813 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 814 { 815 struct pciide_channel *cp; 816 bus_size_t cmdsize, ctlsize; 817 pcireg_t interface, cmdsts; 818 int channel; 819 820 if (pciide_chipen(sc, pa) == 0) 821 return; 822 823 aprint_verbose("%s: bus-master DMA support present", 824 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 825 pciide_mapreg_dma(sc, pa); 826 aprint_verbose("\n"); 827 828 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 829 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 830 if (sc->sc_dma_ok) { 831 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 832 sc->sc_wdcdev.irqack = pciide_irqack; 833 /* Do all revisions require DMA alignment workaround? */ 834 sc->sc_wdcdev.dma_init = piix_dma_init; 835 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 836 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 837 } 838 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 839 840 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 841 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 842 843 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 844 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 845 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 846 847 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 848 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 849 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 850 851 interface = PCI_INTERFACE(pa->pa_class); 852 853 wdc_allocate_regs(&sc->sc_wdcdev); 854 855 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 856 channel++) { 857 cp = &sc->pciide_channels[channel]; 858 if (pciide_chansetup(sc, channel, interface) == 0) 859 continue; 860 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 861 pciide_pci_intr); 862 } 863 } 864 865 static int 866 piix_dma_init(void *v, int channel, int drive, void *databuf, 867 size_t datalen, int flags) 868 { 869 870 /* use PIO for unaligned transfer */ 871 if (((uintptr_t)databuf) & 0x1) 872 return EINVAL; 873 874 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 875 } 876
Indexes created Wed Oct 22 13:09:56 GMT 2025