piixide.c revision 1.37.16.1
1 /* $NetBSD: piixide.c,v 1.37.16.1 2007/11/06 23:29:29 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.37.16.1 2007/11/06 23:29:29 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static void piixide_powerhook(int, void *); 54 static int piixide_match(struct device *, struct cfdata *, void *); 55 static void piixide_attach(struct device *, struct device *, void *); 56 57 static const struct pciide_product_desc pciide_intel_products[] = { 58 { PCI_PRODUCT_INTEL_82092AA, 59 0, 60 "Intel 82092AA IDE controller", 61 default_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371FB_IDE, 64 0, 65 "Intel 82371FB IDE controller (PIIX)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371SB_IDE, 69 0, 70 "Intel 82371SB IDE Interface (PIIX3)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82371AB_IDE, 74 0, 75 "Intel 82371AB IDE controller (PIIX4)", 76 piix_chip_map, 77 }, 78 { PCI_PRODUCT_INTEL_82440MX_IDE, 79 0, 80 "Intel 82440MX IDE controller", 81 piix_chip_map 82 }, 83 { PCI_PRODUCT_INTEL_82801AA_IDE, 84 0, 85 "Intel 82801AA IDE Controller (ICH)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801AB_IDE, 89 0, 90 "Intel 82801AB IDE Controller (ICH0)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BA_IDE, 94 0, 95 "Intel 82801BA IDE Controller (ICH2)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801BAM_IDE, 99 0, 100 "Intel 82801BAM IDE Controller (ICH2-M)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 109 0, 110 "Intel 82801CA IDE Controller (ICH3)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DB_IDE, 114 0, 115 "Intel 82801DB IDE Controller (ICH4)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801DBM_IDE, 119 0, 120 "Intel 82801DBM IDE Controller (ICH4-M)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_IDE, 124 0, 125 "Intel 82801EB IDE Controller (ICH5)", 126 piix_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801EB_SATA, 129 0, 130 "Intel 82801EB Serial ATA Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_82801ER_SATA, 134 0, 135 "Intel 82801ER Serial ATA/Raid Controller", 136 piixsata_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_IDE, 139 0, 140 "Intel 6300ESB IDE Controller (ICH5)", 141 piix_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_6300ESB_SATA, 144 0, 145 "Intel 6300ESB Serial ATA Controller", 146 piixsata_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_6300ESB_RAID, 149 0, 150 "Intel 6300ESB Serial ATA/RAID Controller", 151 piixsata_chip_map, 152 }, 153 { PCI_PRODUCT_INTEL_82801FB_IDE, 154 0, 155 "Intel 82801FB IDE Controller (ICH6)", 156 piix_chip_map, 157 }, 158 { PCI_PRODUCT_INTEL_82801FB_SATA, 159 0, 160 "Intel 82801FB Serial ATA/Raid Controller", 161 piixsata_chip_map, 162 }, 163 { PCI_PRODUCT_INTEL_82801FR_SATA, 164 0, 165 "Intel 82801FR Serial ATA/Raid Controller", 166 piixsata_chip_map, 167 }, 168 { PCI_PRODUCT_INTEL_82801FBM_SATA, 169 0, 170 "Intel 82801FBM Serial ATA Controller (ICH6)", 171 piixsata_chip_map, 172 }, 173 { PCI_PRODUCT_INTEL_82801G_IDE, 174 0, 175 "Intel 82801GB/GR IDE Controller (ICH7)", 176 piix_chip_map, 177 }, 178 { PCI_PRODUCT_INTEL_82801G_SATA, 179 0, 180 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 181 piixsata_chip_map, 182 }, 183 { PCI_PRODUCT_INTEL_82801GBM_SATA, 184 0, 185 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 186 piixsata_chip_map, 187 }, 188 { PCI_PRODUCT_INTEL_82801H_SATA_1, 189 0, 190 "Intel 82801H Serial ATA Controller (ICH8)", 191 piixsata_chip_map, 192 }, 193 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 194 0, 195 "Intel 82801H Serial ATA RAID Controller (ICH8)", 196 piixsata_chip_map, 197 }, 198 { PCI_PRODUCT_INTEL_82801H_SATA_2, 199 0, 200 "Intel 82801H Serial ATA Controller (ICH8)", 201 piixsata_chip_map, 202 }, 203 { PCI_PRODUCT_INTEL_82801HBM_IDE, 204 0, 205 "Intel 82801HBM IDE Controller (ICH8M)", 206 piix_chip_map, 207 }, 208 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 209 0, 210 "Intel 82801HBM Serial ATA Controller (ICH8M)", 211 piixsata_chip_map, 212 }, 213 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 214 0, 215 "Intel 82801HBM Serial ATA Controller (ICH8M)", 216 piixsata_chip_map, 217 }, 218 { PCI_PRODUCT_INTEL_82801HEM_SATA, 219 0, 220 "Intel 82801HEM Serial ATA Controller (ICH8M)", 221 piixsata_chip_map, 222 }, 223 { PCI_PRODUCT_INTEL_63XXESB_IDE, 224 0, 225 "Intel 631xESB/632xESB IDE Controller", 226 piix_chip_map, 227 }, 228 { PCI_PRODUCT_INTEL_82801I_SATA_1, 229 0, 230 "Intel 82801I Serial ATA Controller (ICH9)", 231 piixsata_chip_map, 232 }, 233 { PCI_PRODUCT_INTEL_82801I_SATA_2, 234 0, 235 "Intel 82801I Serial ATA Controller (ICH9)", 236 piixsata_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_82801I_SATA_3, 239 0, 240 "Intel 82801I Serial ATA Controller (ICH9)", 241 piixsata_chip_map, 242 }, 243 { PCI_PRODUCT_INTEL_63XXESB_SATA, 244 0, 245 "Intel 631xESB/632xESB Serial ATA Controller", 246 piixsata_chip_map, 247 }, 248 { 0, 249 0, 250 NULL, 251 NULL 252 } 253 }; 254 255 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 256 piixide_match, piixide_attach, NULL, NULL); 257 258 static int 259 piixide_match(struct device *parent, struct cfdata *match, 260 void *aux) 261 { 262 struct pci_attach_args *pa = aux; 263 264 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 265 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 266 return (2); 267 } 268 return (0); 269 } 270 271 static void 272 piixide_attach(struct device *parent, struct device *self, void *aux) 273 { 274 struct pci_attach_args *pa = aux; 275 struct pciide_softc *sc = (struct pciide_softc *)self; 276 277 pciide_common_attach(sc, pa, 278 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 279 280 /* Setup our powerhook */ 281 sc->sc_powerhook = powerhook_establish( 282 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, piixide_powerhook, sc); 283 if (sc->sc_powerhook == NULL) 284 printf("%s: WARNING: unable to establish PCI power hook\n", 285 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 286 } 287 288 static void 289 piixide_powerhook(int why, void *hdl) 290 { 291 struct pciide_softc *sc = (struct pciide_softc *)hdl; 292 293 switch (why) { 294 case PWR_SUSPEND: 295 case PWR_STANDBY: 296 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 297 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 298 PIIX_IDETIM); 299 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 300 PIIX_UDMATIM); 301 break; 302 case PWR_RESUME: 303 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 304 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 305 sc->sc_idetim); 306 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 307 sc->sc_udmatim); 308 break; 309 case PWR_SOFTSUSPEND: 310 case PWR_SOFTSTANDBY: 311 case PWR_SOFTRESUME: 312 break; 313 } 314 315 return; 316 } 317 318 static void 319 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 320 { 321 struct pciide_channel *cp; 322 int channel; 323 u_int32_t idetim; 324 bus_size_t cmdsize, ctlsize; 325 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 326 327 if (pciide_chipen(sc, pa) == 0) 328 return; 329 330 aprint_verbose("%s: bus-master DMA support present", 331 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 332 pciide_mapreg_dma(sc, pa); 333 aprint_verbose("\n"); 334 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 335 if (sc->sc_dma_ok) { 336 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 337 sc->sc_wdcdev.irqack = pciide_irqack; 338 /* Do all revisions require DMA alignment workaround? */ 339 sc->sc_wdcdev.dma_init = piix_dma_init; 340 switch(sc->sc_pp->ide_product) { 341 case PCI_PRODUCT_INTEL_82371AB_IDE: 342 case PCI_PRODUCT_INTEL_82440MX_IDE: 343 case PCI_PRODUCT_INTEL_82801AA_IDE: 344 case PCI_PRODUCT_INTEL_82801AB_IDE: 345 case PCI_PRODUCT_INTEL_82801BA_IDE: 346 case PCI_PRODUCT_INTEL_82801BAM_IDE: 347 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 348 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 349 case PCI_PRODUCT_INTEL_82801DB_IDE: 350 case PCI_PRODUCT_INTEL_82801DBM_IDE: 351 case PCI_PRODUCT_INTEL_82801EB_IDE: 352 case PCI_PRODUCT_INTEL_6300ESB_IDE: 353 case PCI_PRODUCT_INTEL_82801FB_IDE: 354 case PCI_PRODUCT_INTEL_82801G_IDE: 355 case PCI_PRODUCT_INTEL_82801HBM_IDE: 356 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 357 } 358 } 359 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 360 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 361 switch(sc->sc_pp->ide_product) { 362 case PCI_PRODUCT_INTEL_82801AA_IDE: 363 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 364 break; 365 case PCI_PRODUCT_INTEL_82801BA_IDE: 366 case PCI_PRODUCT_INTEL_82801BAM_IDE: 367 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 368 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 369 case PCI_PRODUCT_INTEL_82801DB_IDE: 370 case PCI_PRODUCT_INTEL_82801DBM_IDE: 371 case PCI_PRODUCT_INTEL_82801EB_IDE: 372 case PCI_PRODUCT_INTEL_6300ESB_IDE: 373 case PCI_PRODUCT_INTEL_82801FB_IDE: 374 case PCI_PRODUCT_INTEL_82801G_IDE: 375 case PCI_PRODUCT_INTEL_82801HBM_IDE: 376 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 377 break; 378 default: 379 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 380 } 381 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 382 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 383 else 384 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 385 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 386 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 387 388 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 389 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 390 DEBUG_PROBE); 391 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 392 ATADEBUG_PRINT((", sidetim=0x%x", 393 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 394 DEBUG_PROBE); 395 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 396 ATADEBUG_PRINT((", udamreg 0x%x", 397 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 398 DEBUG_PROBE); 399 } 400 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 402 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 404 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 405 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 406 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 407 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 408 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 409 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 410 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 411 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 412 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 413 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 414 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 415 DEBUG_PROBE); 416 } 417 418 } 419 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 420 421 wdc_allocate_regs(&sc->sc_wdcdev); 422 423 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 424 channel++) { 425 cp = &sc->pciide_channels[channel]; 426 if (pciide_chansetup(sc, channel, interface) == 0) 427 continue; 428 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 429 if ((PIIX_IDETIM_READ(idetim, channel) & 430 PIIX_IDETIM_IDE) == 0) { 431 #if 1 432 aprint_normal("%s: %s channel ignored (disabled)\n", 433 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 434 cp->ata_channel.ch_flags |= ATACH_DISABLED; 435 continue; 436 #else 437 pcireg_t interface; 438 439 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 440 channel); 441 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 442 idetim); 443 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 444 sc->sc_tag, PCI_CLASS_REG)); 445 aprint_normal("channel %d idetim=%08x interface=%02x\n", 446 channel, idetim, interface); 447 #endif 448 } 449 pciide_mapchan(pa, cp, interface, 450 &cmdsize, &ctlsize, pciide_pci_intr); 451 } 452 453 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 454 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 455 DEBUG_PROBE); 456 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 457 ATADEBUG_PRINT((", sidetim=0x%x", 458 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 459 DEBUG_PROBE); 460 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 461 ATADEBUG_PRINT((", udamreg 0x%x", 462 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 463 DEBUG_PROBE); 464 } 465 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 472 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 473 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 474 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 475 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 476 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 477 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 478 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 479 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 480 DEBUG_PROBE); 481 } 482 } 483 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 484 } 485 486 static void 487 piix_setup_channel(struct ata_channel *chp) 488 { 489 u_int8_t mode[2], drive; 490 u_int32_t oidetim, idetim, idedma_ctl; 491 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 492 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 493 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 494 495 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 496 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 497 idedma_ctl = 0; 498 499 /* set up new idetim: Enable IDE registers decode */ 500 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 501 chp->ch_channel); 502 503 /* setup DMA */ 504 pciide_channel_dma_setup(cp); 505 506 /* 507 * Here we have to mess up with drives mode: PIIX can't have 508 * different timings for master and slave drives. 509 * We need to find the best combination. 510 */ 511 512 /* If both drives supports DMA, take the lower mode */ 513 if ((drvp[0].drive_flags & DRIVE_DMA) && 514 (drvp[1].drive_flags & DRIVE_DMA)) { 515 mode[0] = mode[1] = 516 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 517 drvp[0].DMA_mode = mode[0]; 518 drvp[1].DMA_mode = mode[1]; 519 goto ok; 520 } 521 /* 522 * If only one drive supports DMA, use its mode, and 523 * put the other one in PIO mode 0 if mode not compatible 524 */ 525 if (drvp[0].drive_flags & DRIVE_DMA) { 526 mode[0] = drvp[0].DMA_mode; 527 mode[1] = drvp[1].PIO_mode; 528 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 529 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 530 mode[1] = drvp[1].PIO_mode = 0; 531 goto ok; 532 } 533 if (drvp[1].drive_flags & DRIVE_DMA) { 534 mode[1] = drvp[1].DMA_mode; 535 mode[0] = drvp[0].PIO_mode; 536 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 537 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 538 mode[0] = drvp[0].PIO_mode = 0; 539 goto ok; 540 } 541 /* 542 * If both drives are not DMA, takes the lower mode, unless 543 * one of them is PIO mode < 2 544 */ 545 if (drvp[0].PIO_mode < 2) { 546 mode[0] = drvp[0].PIO_mode = 0; 547 mode[1] = drvp[1].PIO_mode; 548 } else if (drvp[1].PIO_mode < 2) { 549 mode[1] = drvp[1].PIO_mode = 0; 550 mode[0] = drvp[0].PIO_mode; 551 } else { 552 mode[0] = mode[1] = 553 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 554 drvp[0].PIO_mode = mode[0]; 555 drvp[1].PIO_mode = mode[1]; 556 } 557 ok: /* The modes are setup */ 558 for (drive = 0; drive < 2; drive++) { 559 if (drvp[drive].drive_flags & DRIVE_DMA) { 560 idetim |= piix_setup_idetim_timings( 561 mode[drive], 1, chp->ch_channel); 562 goto end; 563 } 564 } 565 /* If we are there, none of the drives are DMA */ 566 if (mode[0] >= 2) 567 idetim |= piix_setup_idetim_timings( 568 mode[0], 0, chp->ch_channel); 569 else 570 idetim |= piix_setup_idetim_timings( 571 mode[1], 0, chp->ch_channel); 572 end: /* 573 * timing mode is now set up in the controller. Enable 574 * it per-drive 575 */ 576 for (drive = 0; drive < 2; drive++) { 577 /* If no drive, skip */ 578 if ((drvp[drive].drive_flags & DRIVE) == 0) 579 continue; 580 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 581 if (drvp[drive].drive_flags & DRIVE_DMA) 582 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 583 } 584 if (idedma_ctl != 0) { 585 /* Add software bits in status register */ 586 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 587 idedma_ctl); 588 } 589 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 590 } 591 592 static void 593 piix3_4_setup_channel(struct ata_channel *chp) 594 { 595 struct ata_drive_datas *drvp; 596 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 597 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 598 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 599 struct wdc_softc *wdc = &sc->sc_wdcdev; 600 int drive, s; 601 int channel = chp->ch_channel; 602 603 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 604 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 605 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 606 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 607 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 608 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 609 PIIX_SIDETIM_RTC_MASK(channel)); 610 idedma_ctl = 0; 611 612 /* set up new idetim: Enable IDE registers decode */ 613 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 614 615 /* setup DMA if needed */ 616 pciide_channel_dma_setup(cp); 617 618 for (drive = 0; drive < 2; drive++) { 619 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 620 PIIX_UDMATIM_SET(0x3, channel, drive)); 621 drvp = &chp->ch_drive[drive]; 622 /* If no drive, skip */ 623 if ((drvp->drive_flags & DRIVE) == 0) 624 continue; 625 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 626 (drvp->drive_flags & DRIVE_UDMA) == 0)) 627 goto pio; 628 629 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 632 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 633 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 636 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 637 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 638 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 639 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 640 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 641 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 642 ideconf |= PIIX_CONFIG_PINGPONG; 643 } 644 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 645 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 646 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 647 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 648 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 649 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 650 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 651 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 652 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 653 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 654 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 655 /* setup Ultra/100 */ 656 if (drvp->UDMA_mode > 2 && 657 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 658 drvp->UDMA_mode = 2; 659 if (drvp->UDMA_mode > 4) { 660 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 661 } else { 662 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 663 if (drvp->UDMA_mode > 2) { 664 ideconf |= PIIX_CONFIG_UDMA66(channel, 665 drive); 666 } else { 667 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 668 drive); 669 } 670 } 671 } 672 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 673 /* setup Ultra/66 */ 674 if (drvp->UDMA_mode > 2 && 675 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 676 drvp->UDMA_mode = 2; 677 if (drvp->UDMA_mode > 2) 678 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 679 else 680 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 681 } 682 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 683 (drvp->drive_flags & DRIVE_UDMA)) { 684 /* use Ultra/DMA */ 685 s = splbio(); 686 drvp->drive_flags &= ~DRIVE_DMA; 687 splx(s); 688 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 689 udmareg |= PIIX_UDMATIM_SET( 690 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 691 } else { 692 /* use Multiword DMA */ 693 s = splbio(); 694 drvp->drive_flags &= ~DRIVE_UDMA; 695 splx(s); 696 if (drive == 0) { 697 idetim |= piix_setup_idetim_timings( 698 drvp->DMA_mode, 1, channel); 699 } else { 700 sidetim |= piix_setup_sidetim_timings( 701 drvp->DMA_mode, 1, channel); 702 idetim =PIIX_IDETIM_SET(idetim, 703 PIIX_IDETIM_SITRE, channel); 704 } 705 } 706 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 707 708 pio: /* use PIO mode */ 709 idetim |= piix_setup_idetim_drvs(drvp); 710 if (drive == 0) { 711 idetim |= piix_setup_idetim_timings( 712 drvp->PIO_mode, 0, channel); 713 } else { 714 sidetim |= piix_setup_sidetim_timings( 715 drvp->PIO_mode, 0, channel); 716 idetim =PIIX_IDETIM_SET(idetim, 717 PIIX_IDETIM_SITRE, channel); 718 } 719 } 720 if (idedma_ctl != 0) { 721 /* Add software bits in status register */ 722 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 723 idedma_ctl); 724 } 725 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 726 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 727 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 728 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 729 } 730 731 732 /* setup ISP and RTC fields, based on mode */ 733 static u_int32_t 734 piix_setup_idetim_timings(mode, dma, channel) 735 u_int8_t mode; 736 u_int8_t dma; 737 u_int8_t channel; 738 { 739 740 if (dma) 741 return PIIX_IDETIM_SET(0, 742 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 743 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 744 channel); 745 else 746 return PIIX_IDETIM_SET(0, 747 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 748 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 749 channel); 750 } 751 752 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 753 static u_int32_t 754 piix_setup_idetim_drvs(drvp) 755 struct ata_drive_datas *drvp; 756 { 757 u_int32_t ret = 0; 758 struct ata_channel *chp = drvp->chnl_softc; 759 u_int8_t channel = chp->ch_channel; 760 u_int8_t drive = drvp->drive; 761 762 /* 763 * If drive is using UDMA, timings setups are independent 764 * So just check DMA and PIO here. 765 */ 766 if (drvp->drive_flags & DRIVE_DMA) { 767 /* if mode = DMA mode 0, use compatible timings */ 768 if ((drvp->drive_flags & DRIVE_DMA) && 769 drvp->DMA_mode == 0) { 770 drvp->PIO_mode = 0; 771 return ret; 772 } 773 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 774 /* 775 * PIO and DMA timings are the same, use fast timings for PIO 776 * too, else use compat timings. 777 */ 778 if ((piix_isp_pio[drvp->PIO_mode] != 779 piix_isp_dma[drvp->DMA_mode]) || 780 (piix_rtc_pio[drvp->PIO_mode] != 781 piix_rtc_dma[drvp->DMA_mode])) 782 drvp->PIO_mode = 0; 783 /* if PIO mode <= 2, use compat timings for PIO */ 784 if (drvp->PIO_mode <= 2) { 785 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 786 channel); 787 return ret; 788 } 789 } 790 791 /* 792 * Now setup PIO modes. If mode < 2, use compat timings. 793 * Else enable fast timings. Enable IORDY and prefetch/post 794 * if PIO mode >= 3. 795 */ 796 797 if (drvp->PIO_mode < 2) 798 return ret; 799 800 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 801 if (drvp->PIO_mode >= 3) { 802 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 803 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 804 } 805 return ret; 806 } 807 808 /* setup values in SIDETIM registers, based on mode */ 809 static u_int32_t 810 piix_setup_sidetim_timings(mode, dma, channel) 811 u_int8_t mode; 812 u_int8_t dma; 813 u_int8_t channel; 814 { 815 if (dma) 816 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 817 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 818 else 819 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 820 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 821 } 822 823 static void 824 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 825 { 826 struct pciide_channel *cp; 827 bus_size_t cmdsize, ctlsize; 828 pcireg_t interface, cmdsts; 829 int channel; 830 831 if (pciide_chipen(sc, pa) == 0) 832 return; 833 834 aprint_verbose("%s: bus-master DMA support present", 835 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 836 pciide_mapreg_dma(sc, pa); 837 aprint_verbose("\n"); 838 839 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 840 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 841 if (sc->sc_dma_ok) { 842 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 843 sc->sc_wdcdev.irqack = pciide_irqack; 844 /* Do all revisions require DMA alignment workaround? */ 845 sc->sc_wdcdev.dma_init = piix_dma_init; 846 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 847 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 848 } 849 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 850 851 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 852 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 853 854 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 855 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 856 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 857 858 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 859 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 860 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 861 862 interface = PCI_INTERFACE(pa->pa_class); 863 864 wdc_allocate_regs(&sc->sc_wdcdev); 865 866 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 867 channel++) { 868 cp = &sc->pciide_channels[channel]; 869 if (pciide_chansetup(sc, channel, interface) == 0) 870 continue; 871 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 872 pciide_pci_intr); 873 } 874 } 875 876 static int 877 piix_dma_init(void *v, int channel, int drive, void *databuf, 878 size_t datalen, int flags) 879 { 880 881 /* use PIO for unaligned transfer */ 882 if (((uintptr_t)databuf) & 0x1) 883 return EINVAL; 884 885 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 886 } 887
Indexes created Wed Oct 15 16:09:53 GMT 2025