piixide.c revision 1.39
1 /* $NetBSD: piixide.c,v 1.39 2007/08/31 00:01:17 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.39 2007/08/31 00:01:17 xtraeme Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static void piixide_powerhook(int, void *); 54 static int piixide_match(struct device *, struct cfdata *, void *); 55 static void piixide_attach(struct device *, struct device *, void *); 56 57 static const struct pciide_product_desc pciide_intel_products[] = { 58 { PCI_PRODUCT_INTEL_82092AA, 59 0, 60 "Intel 82092AA IDE controller", 61 default_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371FB_IDE, 64 0, 65 "Intel 82371FB IDE controller (PIIX)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371SB_IDE, 69 0, 70 "Intel 82371SB IDE Interface (PIIX3)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82371AB_IDE, 74 0, 75 "Intel 82371AB IDE controller (PIIX4)", 76 piix_chip_map, 77 }, 78 { PCI_PRODUCT_INTEL_82440MX_IDE, 79 0, 80 "Intel 82440MX IDE controller", 81 piix_chip_map 82 }, 83 { PCI_PRODUCT_INTEL_82801AA_IDE, 84 0, 85 "Intel 82801AA IDE Controller (ICH)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801AB_IDE, 89 0, 90 "Intel 82801AB IDE Controller (ICH0)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BA_IDE, 94 0, 95 "Intel 82801BA IDE Controller (ICH2)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801BAM_IDE, 99 0, 100 "Intel 82801BAM IDE Controller (ICH2-M)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 109 0, 110 "Intel 82801CA IDE Controller (ICH3)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DB_IDE, 114 0, 115 "Intel 82801DB IDE Controller (ICH4)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801DBM_IDE, 119 0, 120 "Intel 82801DBM IDE Controller (ICH4-M)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_IDE, 124 0, 125 "Intel 82801EB IDE Controller (ICH5)", 126 piix_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801EB_SATA, 129 0, 130 "Intel 82801EB Serial ATA Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_82801ER_SATA, 134 0, 135 "Intel 82801ER Serial ATA/Raid Controller", 136 piixsata_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_IDE, 139 0, 140 "Intel 6300ESB IDE Controller (ICH5)", 141 piix_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_6300ESB_SATA, 144 0, 145 "Intel 6300ESB Serial ATA Controller", 146 piixsata_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_6300ESB_RAID, 149 0, 150 "Intel 6300ESB Serial ATA/RAID Controller", 151 piixsata_chip_map, 152 }, 153 { PCI_PRODUCT_INTEL_82801FB_IDE, 154 0, 155 "Intel 82801FB IDE Controller (ICH6)", 156 piix_chip_map, 157 }, 158 { PCI_PRODUCT_INTEL_82801FB_SATA, 159 0, 160 "Intel 82801FB Serial ATA/Raid Controller", 161 piixsata_chip_map, 162 }, 163 { PCI_PRODUCT_INTEL_82801FR_SATA, 164 0, 165 "Intel 82801FR Serial ATA/Raid Controller", 166 piixsata_chip_map, 167 }, 168 { PCI_PRODUCT_INTEL_82801FBM_SATA, 169 0, 170 "Intel 82801FBM Serial ATA Controller (ICH6)", 171 piixsata_chip_map, 172 }, 173 { PCI_PRODUCT_INTEL_82801G_IDE, 174 0, 175 "Intel 82801GB/GR IDE Controller (ICH7)", 176 piix_chip_map, 177 }, 178 { PCI_PRODUCT_INTEL_82801G_SATA, 179 0, 180 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 181 piixsata_chip_map, 182 }, 183 { PCI_PRODUCT_INTEL_82801GBM_SATA, 184 0, 185 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 186 piixsata_chip_map, 187 }, 188 { PCI_PRODUCT_INTEL_82801H_SATA_1, 189 0, 190 "Intel 82801H Serial ATA Controller (ICH8)", 191 piixsata_chip_map, 192 }, 193 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 194 0, 195 "Intel 82801H Serial ATA RAID Controller (ICH8)", 196 piixsata_chip_map, 197 }, 198 { PCI_PRODUCT_INTEL_82801H_SATA_2, 199 0, 200 "Intel 82801H Serial ATA Controller (ICH8)", 201 piixsata_chip_map, 202 }, 203 { PCI_PRODUCT_INTEL_82801HBM_IDE, 204 0, 205 "Intel 82801HBM IDE Controller (ICH8M)", 206 piix_chip_map, 207 }, 208 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 209 0, 210 "Intel 82801HBM Serial ATA Controller (ICH8M)", 211 piixsata_chip_map, 212 }, 213 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 214 0, 215 "Intel 82801HBM Serial ATA Controller (ICH8M)", 216 piixsata_chip_map, 217 }, 218 { PCI_PRODUCT_INTEL_63XXESB_IDE, 219 0, 220 "Intel 631xESB/632xESB IDE Controller", 221 piix_chip_map, 222 }, 223 { PCI_PRODUCT_INTEL_82801I_SATA_1, 224 0, 225 "Intel 82801I Serial ATA Controller (ICH9)", 226 piixsata_chip_map, 227 }, 228 { PCI_PRODUCT_INTEL_82801I_SATA_2, 229 0, 230 "Intel 82801I Serial ATA Controller (ICH9)", 231 piixsata_chip_map, 232 }, 233 { PCI_PRODUCT_INTEL_82801I_SATA_3, 234 0, 235 "Intel 82801I Serial ATA Controller (ICH9)", 236 piixsata_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_63XXESB_SATA, 239 0, 240 "Intel 631xESB/632xESB Serial ATA Controller", 241 piixsata_chip_map, 242 }, 243 { 0, 244 0, 245 NULL, 246 NULL 247 } 248 }; 249 250 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 251 piixide_match, piixide_attach, NULL, NULL); 252 253 static int 254 piixide_match(struct device *parent, struct cfdata *match, 255 void *aux) 256 { 257 struct pci_attach_args *pa = aux; 258 259 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 260 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 261 return (2); 262 } 263 return (0); 264 } 265 266 static void 267 piixide_attach(struct device *parent, struct device *self, void *aux) 268 { 269 struct pci_attach_args *pa = aux; 270 struct pciide_softc *sc = (struct pciide_softc *)self; 271 272 pciide_common_attach(sc, pa, 273 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 274 275 /* Setup our powerhook */ 276 sc->sc_powerhook = powerhook_establish( 277 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, piixide_powerhook, sc); 278 if (sc->sc_powerhook == NULL) 279 printf("%s: WARNING: unable to establish PCI power hook\n", 280 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 281 } 282 283 static void 284 piixide_powerhook(int why, void *hdl) 285 { 286 struct pciide_softc *sc = (struct pciide_softc *)hdl; 287 288 switch (why) { 289 case PWR_SUSPEND: 290 case PWR_STANDBY: 291 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 292 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 293 PIIX_IDETIM); 294 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 295 PIIX_UDMATIM); 296 break; 297 case PWR_RESUME: 298 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 299 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 300 sc->sc_idetim); 301 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 302 sc->sc_udmatim); 303 break; 304 case PWR_SOFTSUSPEND: 305 case PWR_SOFTSTANDBY: 306 case PWR_SOFTRESUME: 307 break; 308 } 309 310 return; 311 } 312 313 static void 314 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 315 { 316 struct pciide_channel *cp; 317 int channel; 318 u_int32_t idetim; 319 bus_size_t cmdsize, ctlsize; 320 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 321 322 if (pciide_chipen(sc, pa) == 0) 323 return; 324 325 aprint_verbose("%s: bus-master DMA support present", 326 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 327 pciide_mapreg_dma(sc, pa); 328 aprint_verbose("\n"); 329 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 330 if (sc->sc_dma_ok) { 331 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 332 sc->sc_wdcdev.irqack = pciide_irqack; 333 /* Do all revisions require DMA alignment workaround? */ 334 sc->sc_wdcdev.dma_init = piix_dma_init; 335 switch(sc->sc_pp->ide_product) { 336 case PCI_PRODUCT_INTEL_82371AB_IDE: 337 case PCI_PRODUCT_INTEL_82440MX_IDE: 338 case PCI_PRODUCT_INTEL_82801AA_IDE: 339 case PCI_PRODUCT_INTEL_82801AB_IDE: 340 case PCI_PRODUCT_INTEL_82801BA_IDE: 341 case PCI_PRODUCT_INTEL_82801BAM_IDE: 342 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 343 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 344 case PCI_PRODUCT_INTEL_82801DB_IDE: 345 case PCI_PRODUCT_INTEL_82801DBM_IDE: 346 case PCI_PRODUCT_INTEL_82801EB_IDE: 347 case PCI_PRODUCT_INTEL_6300ESB_IDE: 348 case PCI_PRODUCT_INTEL_82801FB_IDE: 349 case PCI_PRODUCT_INTEL_82801G_IDE: 350 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 351 } 352 } 353 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 354 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 355 switch(sc->sc_pp->ide_product) { 356 case PCI_PRODUCT_INTEL_82801AA_IDE: 357 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 358 break; 359 case PCI_PRODUCT_INTEL_82801BA_IDE: 360 case PCI_PRODUCT_INTEL_82801BAM_IDE: 361 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 362 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 363 case PCI_PRODUCT_INTEL_82801DB_IDE: 364 case PCI_PRODUCT_INTEL_82801DBM_IDE: 365 case PCI_PRODUCT_INTEL_82801EB_IDE: 366 case PCI_PRODUCT_INTEL_6300ESB_IDE: 367 case PCI_PRODUCT_INTEL_82801FB_IDE: 368 case PCI_PRODUCT_INTEL_82801G_IDE: 369 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 370 break; 371 default: 372 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 373 } 374 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 375 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 376 else 377 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 378 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 379 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 380 381 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 382 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 383 DEBUG_PROBE); 384 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 385 ATADEBUG_PRINT((", sidetim=0x%x", 386 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 387 DEBUG_PROBE); 388 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 389 ATADEBUG_PRINT((", udamreg 0x%x", 390 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 391 DEBUG_PROBE); 392 } 393 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 394 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 395 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 396 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 397 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 398 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 400 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 402 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 404 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 405 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 406 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 407 DEBUG_PROBE); 408 } 409 410 } 411 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 412 413 wdc_allocate_regs(&sc->sc_wdcdev); 414 415 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 416 channel++) { 417 cp = &sc->pciide_channels[channel]; 418 if (pciide_chansetup(sc, channel, interface) == 0) 419 continue; 420 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 421 if ((PIIX_IDETIM_READ(idetim, channel) & 422 PIIX_IDETIM_IDE) == 0) { 423 #if 1 424 aprint_normal("%s: %s channel ignored (disabled)\n", 425 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 426 cp->ata_channel.ch_flags |= ATACH_DISABLED; 427 continue; 428 #else 429 pcireg_t interface; 430 431 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 432 channel); 433 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 434 idetim); 435 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 436 sc->sc_tag, PCI_CLASS_REG)); 437 aprint_normal("channel %d idetim=%08x interface=%02x\n", 438 channel, idetim, interface); 439 #endif 440 } 441 pciide_mapchan(pa, cp, interface, 442 &cmdsize, &ctlsize, pciide_pci_intr); 443 } 444 445 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 446 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 447 DEBUG_PROBE); 448 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 449 ATADEBUG_PRINT((", sidetim=0x%x", 450 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 451 DEBUG_PROBE); 452 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 453 ATADEBUG_PRINT((", udamreg 0x%x", 454 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 455 DEBUG_PROBE); 456 } 457 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 458 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 459 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 460 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 461 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 462 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 469 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 470 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 471 DEBUG_PROBE); 472 } 473 } 474 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 475 } 476 477 static void 478 piix_setup_channel(struct ata_channel *chp) 479 { 480 u_int8_t mode[2], drive; 481 u_int32_t oidetim, idetim, idedma_ctl; 482 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 483 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 484 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 485 486 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 487 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 488 idedma_ctl = 0; 489 490 /* set up new idetim: Enable IDE registers decode */ 491 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 492 chp->ch_channel); 493 494 /* setup DMA */ 495 pciide_channel_dma_setup(cp); 496 497 /* 498 * Here we have to mess up with drives mode: PIIX can't have 499 * different timings for master and slave drives. 500 * We need to find the best combination. 501 */ 502 503 /* If both drives supports DMA, take the lower mode */ 504 if ((drvp[0].drive_flags & DRIVE_DMA) && 505 (drvp[1].drive_flags & DRIVE_DMA)) { 506 mode[0] = mode[1] = 507 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 508 drvp[0].DMA_mode = mode[0]; 509 drvp[1].DMA_mode = mode[1]; 510 goto ok; 511 } 512 /* 513 * If only one drive supports DMA, use its mode, and 514 * put the other one in PIO mode 0 if mode not compatible 515 */ 516 if (drvp[0].drive_flags & DRIVE_DMA) { 517 mode[0] = drvp[0].DMA_mode; 518 mode[1] = drvp[1].PIO_mode; 519 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 520 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 521 mode[1] = drvp[1].PIO_mode = 0; 522 goto ok; 523 } 524 if (drvp[1].drive_flags & DRIVE_DMA) { 525 mode[1] = drvp[1].DMA_mode; 526 mode[0] = drvp[0].PIO_mode; 527 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 528 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 529 mode[0] = drvp[0].PIO_mode = 0; 530 goto ok; 531 } 532 /* 533 * If both drives are not DMA, takes the lower mode, unless 534 * one of them is PIO mode < 2 535 */ 536 if (drvp[0].PIO_mode < 2) { 537 mode[0] = drvp[0].PIO_mode = 0; 538 mode[1] = drvp[1].PIO_mode; 539 } else if (drvp[1].PIO_mode < 2) { 540 mode[1] = drvp[1].PIO_mode = 0; 541 mode[0] = drvp[0].PIO_mode; 542 } else { 543 mode[0] = mode[1] = 544 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 545 drvp[0].PIO_mode = mode[0]; 546 drvp[1].PIO_mode = mode[1]; 547 } 548 ok: /* The modes are setup */ 549 for (drive = 0; drive < 2; drive++) { 550 if (drvp[drive].drive_flags & DRIVE_DMA) { 551 idetim |= piix_setup_idetim_timings( 552 mode[drive], 1, chp->ch_channel); 553 goto end; 554 } 555 } 556 /* If we are there, none of the drives are DMA */ 557 if (mode[0] >= 2) 558 idetim |= piix_setup_idetim_timings( 559 mode[0], 0, chp->ch_channel); 560 else 561 idetim |= piix_setup_idetim_timings( 562 mode[1], 0, chp->ch_channel); 563 end: /* 564 * timing mode is now set up in the controller. Enable 565 * it per-drive 566 */ 567 for (drive = 0; drive < 2; drive++) { 568 /* If no drive, skip */ 569 if ((drvp[drive].drive_flags & DRIVE) == 0) 570 continue; 571 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 572 if (drvp[drive].drive_flags & DRIVE_DMA) 573 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 574 } 575 if (idedma_ctl != 0) { 576 /* Add software bits in status register */ 577 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 578 idedma_ctl); 579 } 580 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 581 } 582 583 static void 584 piix3_4_setup_channel(struct ata_channel *chp) 585 { 586 struct ata_drive_datas *drvp; 587 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 588 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 589 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 590 struct wdc_softc *wdc = &sc->sc_wdcdev; 591 int drive, s; 592 int channel = chp->ch_channel; 593 594 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 595 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 596 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 597 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 598 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 599 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 600 PIIX_SIDETIM_RTC_MASK(channel)); 601 idedma_ctl = 0; 602 603 /* set up new idetim: Enable IDE registers decode */ 604 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 605 606 /* setup DMA if needed */ 607 pciide_channel_dma_setup(cp); 608 609 for (drive = 0; drive < 2; drive++) { 610 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 611 PIIX_UDMATIM_SET(0x3, channel, drive)); 612 drvp = &chp->ch_drive[drive]; 613 /* If no drive, skip */ 614 if ((drvp->drive_flags & DRIVE) == 0) 615 continue; 616 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 617 (drvp->drive_flags & DRIVE_UDMA) == 0)) 618 goto pio; 619 620 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 621 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 622 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 623 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 624 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 625 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 626 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 632 ideconf |= PIIX_CONFIG_PINGPONG; 633 } 634 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 636 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 637 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 638 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 639 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 640 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 641 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 642 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 643 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE) { 644 /* setup Ultra/100 */ 645 if (drvp->UDMA_mode > 2 && 646 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 647 drvp->UDMA_mode = 2; 648 if (drvp->UDMA_mode > 4) { 649 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 650 } else { 651 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 652 if (drvp->UDMA_mode > 2) { 653 ideconf |= PIIX_CONFIG_UDMA66(channel, 654 drive); 655 } else { 656 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 657 drive); 658 } 659 } 660 } 661 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 662 /* setup Ultra/66 */ 663 if (drvp->UDMA_mode > 2 && 664 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 665 drvp->UDMA_mode = 2; 666 if (drvp->UDMA_mode > 2) 667 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 668 else 669 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 670 } 671 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 672 (drvp->drive_flags & DRIVE_UDMA)) { 673 /* use Ultra/DMA */ 674 s = splbio(); 675 drvp->drive_flags &= ~DRIVE_DMA; 676 splx(s); 677 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 678 udmareg |= PIIX_UDMATIM_SET( 679 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 680 } else { 681 /* use Multiword DMA */ 682 s = splbio(); 683 drvp->drive_flags &= ~DRIVE_UDMA; 684 splx(s); 685 if (drive == 0) { 686 idetim |= piix_setup_idetim_timings( 687 drvp->DMA_mode, 1, channel); 688 } else { 689 sidetim |= piix_setup_sidetim_timings( 690 drvp->DMA_mode, 1, channel); 691 idetim =PIIX_IDETIM_SET(idetim, 692 PIIX_IDETIM_SITRE, channel); 693 } 694 } 695 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 696 697 pio: /* use PIO mode */ 698 idetim |= piix_setup_idetim_drvs(drvp); 699 if (drive == 0) { 700 idetim |= piix_setup_idetim_timings( 701 drvp->PIO_mode, 0, channel); 702 } else { 703 sidetim |= piix_setup_sidetim_timings( 704 drvp->PIO_mode, 0, channel); 705 idetim =PIIX_IDETIM_SET(idetim, 706 PIIX_IDETIM_SITRE, channel); 707 } 708 } 709 if (idedma_ctl != 0) { 710 /* Add software bits in status register */ 711 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 712 idedma_ctl); 713 } 714 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 715 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 716 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 717 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 718 } 719 720 721 /* setup ISP and RTC fields, based on mode */ 722 static u_int32_t 723 piix_setup_idetim_timings(mode, dma, channel) 724 u_int8_t mode; 725 u_int8_t dma; 726 u_int8_t channel; 727 { 728 729 if (dma) 730 return PIIX_IDETIM_SET(0, 731 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 732 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 733 channel); 734 else 735 return PIIX_IDETIM_SET(0, 736 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 737 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 738 channel); 739 } 740 741 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 742 static u_int32_t 743 piix_setup_idetim_drvs(drvp) 744 struct ata_drive_datas *drvp; 745 { 746 u_int32_t ret = 0; 747 struct ata_channel *chp = drvp->chnl_softc; 748 u_int8_t channel = chp->ch_channel; 749 u_int8_t drive = drvp->drive; 750 751 /* 752 * If drive is using UDMA, timings setups are independent 753 * So just check DMA and PIO here. 754 */ 755 if (drvp->drive_flags & DRIVE_DMA) { 756 /* if mode = DMA mode 0, use compatible timings */ 757 if ((drvp->drive_flags & DRIVE_DMA) && 758 drvp->DMA_mode == 0) { 759 drvp->PIO_mode = 0; 760 return ret; 761 } 762 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 763 /* 764 * PIO and DMA timings are the same, use fast timings for PIO 765 * too, else use compat timings. 766 */ 767 if ((piix_isp_pio[drvp->PIO_mode] != 768 piix_isp_dma[drvp->DMA_mode]) || 769 (piix_rtc_pio[drvp->PIO_mode] != 770 piix_rtc_dma[drvp->DMA_mode])) 771 drvp->PIO_mode = 0; 772 /* if PIO mode <= 2, use compat timings for PIO */ 773 if (drvp->PIO_mode <= 2) { 774 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 775 channel); 776 return ret; 777 } 778 } 779 780 /* 781 * Now setup PIO modes. If mode < 2, use compat timings. 782 * Else enable fast timings. Enable IORDY and prefetch/post 783 * if PIO mode >= 3. 784 */ 785 786 if (drvp->PIO_mode < 2) 787 return ret; 788 789 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 790 if (drvp->PIO_mode >= 3) { 791 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 792 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 793 } 794 return ret; 795 } 796 797 /* setup values in SIDETIM registers, based on mode */ 798 static u_int32_t 799 piix_setup_sidetim_timings(mode, dma, channel) 800 u_int8_t mode; 801 u_int8_t dma; 802 u_int8_t channel; 803 { 804 if (dma) 805 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 806 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 807 else 808 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 809 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 810 } 811 812 static void 813 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 814 { 815 struct pciide_channel *cp; 816 bus_size_t cmdsize, ctlsize; 817 pcireg_t interface, cmdsts; 818 int channel; 819 820 if (pciide_chipen(sc, pa) == 0) 821 return; 822 823 aprint_verbose("%s: bus-master DMA support present", 824 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 825 pciide_mapreg_dma(sc, pa); 826 aprint_verbose("\n"); 827 828 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 829 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 830 if (sc->sc_dma_ok) { 831 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 832 sc->sc_wdcdev.irqack = pciide_irqack; 833 /* Do all revisions require DMA alignment workaround? */ 834 sc->sc_wdcdev.dma_init = piix_dma_init; 835 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 836 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 837 } 838 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 839 840 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 841 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 842 843 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 844 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 845 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 846 847 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 848 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 849 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 850 851 interface = PCI_INTERFACE(pa->pa_class); 852 853 wdc_allocate_regs(&sc->sc_wdcdev); 854 855 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 856 channel++) { 857 cp = &sc->pciide_channels[channel]; 858 if (pciide_chansetup(sc, channel, interface) == 0) 859 continue; 860 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 861 pciide_pci_intr); 862 } 863 } 864 865 static int 866 piix_dma_init(void *v, int channel, int drive, void *databuf, 867 size_t datalen, int flags) 868 { 869 870 /* use PIO for unaligned transfer */ 871 if (((uintptr_t)databuf) & 0x1) 872 return EINVAL; 873 874 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 875 } 876
Indexes created Sat Sep 27 14:09:57 GMT 2025