piixide.c revision 1.4
1 /* $NetBSD: piixide.c,v 1.4 2003/12/05 23:12:41 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct channel_softc *); 43 static void piix3_4_setup_channel(struct channel_softc *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static int piixide_match(struct device *, struct cfdata *, void *); 50 static void piixide_attach(struct device *, struct device *, void *); 51 52 static const struct pciide_product_desc pciide_intel_products[] = { 53 { PCI_PRODUCT_INTEL_82092AA, 54 0, 55 "Intel 82092AA IDE controller", 56 default_chip_map, 57 }, 58 { PCI_PRODUCT_INTEL_82371FB_IDE, 59 0, 60 "Intel 82371FB IDE controller (PIIX)", 61 piix_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371SB_IDE, 64 0, 65 "Intel 82371SB IDE Interface (PIIX3)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371AB_IDE, 69 0, 70 "Intel 82371AB IDE controller (PIIX4)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82440MX_IDE, 74 0, 75 "Intel 82440MX IDE controller", 76 piix_chip_map 77 }, 78 { PCI_PRODUCT_INTEL_82801AA_IDE, 79 0, 80 "Intel 82801AA IDE Controller (ICH)", 81 piix_chip_map, 82 }, 83 { PCI_PRODUCT_INTEL_82801AB_IDE, 84 0, 85 "Intel 82801AB IDE Controller (ICH0)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801BA_IDE, 89 0, 90 "Intel 82801BA IDE Controller (ICH2)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 0, 95 "Intel 82801BAM IDE Controller (ICH2-M)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 0, 100 "Intel 82801CA IDE Controller (ICH3)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801DB_IDE, 109 0, 110 "Intel 82801DB IDE Controller (ICH4)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 0, 115 "Intel 82801DBM IDE Controller (ICH4-M)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801EB_IDE, 119 0, 120 "Intel 82801EB IDE Controller (ICH5)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_31244, 124 0, 125 "Intel 31244 Serial ATA Controller", 126 artisea_chip_map, 127 }, 128 /* 129 * XXX Is this really the same as the 31244? --thorpej 130 */ 131 { PCI_PRODUCT_INTEL_82801EB_SATA, 132 0, 133 "Intel 82801EB Serial ATA Controller", 134 artisea_chip_map, 135 }, 136 { PCI_PRODUCT_INTEL_82801ER_SATA, 137 0, 138 "Intel 82801ER Serial ATA/Raid Controller", 139 artisea_chip_map, 140 }, 141 { 0, 142 0, 143 NULL, 144 NULL 145 } 146 }; 147 148 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 149 piixide_match, piixide_attach, NULL, NULL); 150 151 static int 152 piixide_match(struct device *parent, struct cfdata *match, void *aux) 153 { 154 struct pci_attach_args *pa = aux; 155 156 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 157 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 158 return (2); 159 } 160 return (0); 161 } 162 163 static void 164 piixide_attach(struct device *parent, struct device *self, void *aux) 165 { 166 struct pci_attach_args *pa = aux; 167 struct pciide_softc *sc = (struct pciide_softc *)self; 168 169 pciide_common_attach(sc, pa, 170 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 171 172 } 173 174 static void 175 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 176 { 177 struct pciide_channel *cp; 178 int channel; 179 u_int32_t idetim; 180 bus_size_t cmdsize, ctlsize; 181 182 if (pciide_chipen(sc, pa) == 0) 183 return; 184 185 aprint_normal("%s: bus-master DMA support present", 186 sc->sc_wdcdev.sc_dev.dv_xname); 187 pciide_mapreg_dma(sc, pa); 188 aprint_normal("\n"); 189 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 190 WDC_CAPABILITY_MODE; 191 if (sc->sc_dma_ok) { 192 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 193 sc->sc_wdcdev.irqack = pciide_irqack; 194 switch(sc->sc_pp->ide_product) { 195 case PCI_PRODUCT_INTEL_82371AB_IDE: 196 case PCI_PRODUCT_INTEL_82440MX_IDE: 197 case PCI_PRODUCT_INTEL_82801AA_IDE: 198 case PCI_PRODUCT_INTEL_82801AB_IDE: 199 case PCI_PRODUCT_INTEL_82801BA_IDE: 200 case PCI_PRODUCT_INTEL_82801BAM_IDE: 201 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 202 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 203 case PCI_PRODUCT_INTEL_82801DB_IDE: 204 case PCI_PRODUCT_INTEL_82801DBM_IDE: 205 case PCI_PRODUCT_INTEL_82801EB_IDE: 206 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 207 } 208 } 209 sc->sc_wdcdev.PIO_cap = 4; 210 sc->sc_wdcdev.DMA_cap = 2; 211 switch(sc->sc_pp->ide_product) { 212 case PCI_PRODUCT_INTEL_82801AA_IDE: 213 sc->sc_wdcdev.UDMA_cap = 4; 214 break; 215 case PCI_PRODUCT_INTEL_82801BA_IDE: 216 case PCI_PRODUCT_INTEL_82801BAM_IDE: 217 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 218 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 219 case PCI_PRODUCT_INTEL_82801DB_IDE: 220 case PCI_PRODUCT_INTEL_82801DBM_IDE: 221 case PCI_PRODUCT_INTEL_82801EB_IDE: 222 sc->sc_wdcdev.UDMA_cap = 5; 223 break; 224 default: 225 sc->sc_wdcdev.UDMA_cap = 2; 226 } 227 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 228 sc->sc_wdcdev.set_modes = piix_setup_channel; 229 else 230 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 231 sc->sc_wdcdev.channels = sc->wdc_chanarray; 232 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 233 234 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 235 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 236 DEBUG_PROBE); 237 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 238 WDCDEBUG_PRINT((", sidetim=0x%x", 239 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 240 DEBUG_PROBE); 241 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 242 WDCDEBUG_PRINT((", udamreg 0x%x", 243 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 244 DEBUG_PROBE); 245 } 246 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 247 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 248 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 249 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 250 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 251 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 252 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 253 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 254 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ) { 255 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 256 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 257 DEBUG_PROBE); 258 } 259 260 } 261 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 262 263 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 264 cp = &sc->pciide_channels[channel]; 265 /* PIIX is compat-only */ 266 if (pciide_chansetup(sc, channel, 0) == 0) 267 continue; 268 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 269 if ((PIIX_IDETIM_READ(idetim, channel) & 270 PIIX_IDETIM_IDE) == 0) { 271 #if 1 272 aprint_normal("%s: %s channel ignored (disabled)\n", 273 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 274 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 275 continue; 276 #else 277 pcireg_t interface; 278 279 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 280 channel); 281 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 282 idetim); 283 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 284 sc->sc_tag, PCI_CLASS_REG)); 285 aprint_normal("channel %d idetim=%08x interface=%02x\n", 286 channel, idetim, interface); 287 #endif 288 } 289 /* PIIX are compat-only pciide devices */ 290 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 291 } 292 293 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 294 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 295 DEBUG_PROBE); 296 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 297 WDCDEBUG_PRINT((", sidetim=0x%x", 298 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 299 DEBUG_PROBE); 300 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 301 WDCDEBUG_PRINT((", udamreg 0x%x", 302 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 303 DEBUG_PROBE); 304 } 305 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 306 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 307 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 308 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 309 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 310 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 311 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 312 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 313 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 314 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 315 DEBUG_PROBE); 316 } 317 } 318 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 319 } 320 321 static void 322 piix_setup_channel(struct channel_softc *chp) 323 { 324 u_int8_t mode[2], drive; 325 u_int32_t oidetim, idetim, idedma_ctl; 326 struct pciide_channel *cp = (struct pciide_channel*)chp; 327 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 328 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 329 330 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 331 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 332 idedma_ctl = 0; 333 334 /* set up new idetim: Enable IDE registers decode */ 335 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 336 chp->channel); 337 338 /* setup DMA */ 339 pciide_channel_dma_setup(cp); 340 341 /* 342 * Here we have to mess up with drives mode: PIIX can't have 343 * different timings for master and slave drives. 344 * We need to find the best combination. 345 */ 346 347 /* If both drives supports DMA, take the lower mode */ 348 if ((drvp[0].drive_flags & DRIVE_DMA) && 349 (drvp[1].drive_flags & DRIVE_DMA)) { 350 mode[0] = mode[1] = 351 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 352 drvp[0].DMA_mode = mode[0]; 353 drvp[1].DMA_mode = mode[1]; 354 goto ok; 355 } 356 /* 357 * If only one drive supports DMA, use its mode, and 358 * put the other one in PIO mode 0 if mode not compatible 359 */ 360 if (drvp[0].drive_flags & DRIVE_DMA) { 361 mode[0] = drvp[0].DMA_mode; 362 mode[1] = drvp[1].PIO_mode; 363 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 364 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 365 mode[1] = drvp[1].PIO_mode = 0; 366 goto ok; 367 } 368 if (drvp[1].drive_flags & DRIVE_DMA) { 369 mode[1] = drvp[1].DMA_mode; 370 mode[0] = drvp[0].PIO_mode; 371 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 372 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 373 mode[0] = drvp[0].PIO_mode = 0; 374 goto ok; 375 } 376 /* 377 * If both drives are not DMA, takes the lower mode, unless 378 * one of them is PIO mode < 2 379 */ 380 if (drvp[0].PIO_mode < 2) { 381 mode[0] = drvp[0].PIO_mode = 0; 382 mode[1] = drvp[1].PIO_mode; 383 } else if (drvp[1].PIO_mode < 2) { 384 mode[1] = drvp[1].PIO_mode = 0; 385 mode[0] = drvp[0].PIO_mode; 386 } else { 387 mode[0] = mode[1] = 388 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 389 drvp[0].PIO_mode = mode[0]; 390 drvp[1].PIO_mode = mode[1]; 391 } 392 ok: /* The modes are setup */ 393 for (drive = 0; drive < 2; drive++) { 394 if (drvp[drive].drive_flags & DRIVE_DMA) { 395 idetim |= piix_setup_idetim_timings( 396 mode[drive], 1, chp->channel); 397 goto end; 398 } 399 } 400 /* If we are there, none of the drives are DMA */ 401 if (mode[0] >= 2) 402 idetim |= piix_setup_idetim_timings( 403 mode[0], 0, chp->channel); 404 else 405 idetim |= piix_setup_idetim_timings( 406 mode[1], 0, chp->channel); 407 end: /* 408 * timing mode is now set up in the controller. Enable 409 * it per-drive 410 */ 411 for (drive = 0; drive < 2; drive++) { 412 /* If no drive, skip */ 413 if ((drvp[drive].drive_flags & DRIVE) == 0) 414 continue; 415 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 416 if (drvp[drive].drive_flags & DRIVE_DMA) 417 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 418 } 419 if (idedma_ctl != 0) { 420 /* Add software bits in status register */ 421 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 422 idedma_ctl); 423 } 424 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 425 } 426 427 static void 428 piix3_4_setup_channel(struct channel_softc *chp) 429 { 430 struct ata_drive_datas *drvp; 431 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 432 struct pciide_channel *cp = (struct pciide_channel*)chp; 433 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 434 int drive; 435 int channel = chp->channel; 436 437 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 438 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 439 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 440 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 441 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 442 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 443 PIIX_SIDETIM_RTC_MASK(channel)); 444 idedma_ctl = 0; 445 446 /* set up new idetim: Enable IDE registers decode */ 447 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 448 449 /* setup DMA if needed */ 450 pciide_channel_dma_setup(cp); 451 452 for (drive = 0; drive < 2; drive++) { 453 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 454 PIIX_UDMATIM_SET(0x3, channel, drive)); 455 drvp = &chp->ch_drive[drive]; 456 /* If no drive, skip */ 457 if ((drvp->drive_flags & DRIVE) == 0) 458 continue; 459 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 460 (drvp->drive_flags & DRIVE_UDMA) == 0)) 461 goto pio; 462 463 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 472 ideconf |= PIIX_CONFIG_PINGPONG; 473 } 474 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 475 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 476 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 477 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 478 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 479 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 480 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 481 /* setup Ultra/100 */ 482 if (drvp->UDMA_mode > 2 && 483 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 484 drvp->UDMA_mode = 2; 485 if (drvp->UDMA_mode > 4) { 486 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 487 } else { 488 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 489 if (drvp->UDMA_mode > 2) { 490 ideconf |= PIIX_CONFIG_UDMA66(channel, 491 drive); 492 } else { 493 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 494 drive); 495 } 496 } 497 } 498 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 499 /* setup Ultra/66 */ 500 if (drvp->UDMA_mode > 2 && 501 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 502 drvp->UDMA_mode = 2; 503 if (drvp->UDMA_mode > 2) 504 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 505 else 506 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 507 } 508 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 509 (drvp->drive_flags & DRIVE_UDMA)) { 510 /* use Ultra/DMA */ 511 drvp->drive_flags &= ~DRIVE_DMA; 512 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 513 udmareg |= PIIX_UDMATIM_SET( 514 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 515 } else { 516 /* use Multiword DMA */ 517 drvp->drive_flags &= ~DRIVE_UDMA; 518 if (drive == 0) { 519 idetim |= piix_setup_idetim_timings( 520 drvp->DMA_mode, 1, channel); 521 } else { 522 sidetim |= piix_setup_sidetim_timings( 523 drvp->DMA_mode, 1, channel); 524 idetim =PIIX_IDETIM_SET(idetim, 525 PIIX_IDETIM_SITRE, channel); 526 } 527 } 528 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 529 530 pio: /* use PIO mode */ 531 idetim |= piix_setup_idetim_drvs(drvp); 532 if (drive == 0) { 533 idetim |= piix_setup_idetim_timings( 534 drvp->PIO_mode, 0, channel); 535 } else { 536 sidetim |= piix_setup_sidetim_timings( 537 drvp->PIO_mode, 0, channel); 538 idetim =PIIX_IDETIM_SET(idetim, 539 PIIX_IDETIM_SITRE, channel); 540 } 541 } 542 if (idedma_ctl != 0) { 543 /* Add software bits in status register */ 544 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 545 idedma_ctl); 546 } 547 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 548 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 549 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 550 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 551 } 552 553 554 /* setup ISP and RTC fields, based on mode */ 555 static u_int32_t 556 piix_setup_idetim_timings(mode, dma, channel) 557 u_int8_t mode; 558 u_int8_t dma; 559 u_int8_t channel; 560 { 561 562 if (dma) 563 return PIIX_IDETIM_SET(0, 564 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 565 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 566 channel); 567 else 568 return PIIX_IDETIM_SET(0, 569 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 570 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 571 channel); 572 } 573 574 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 575 static u_int32_t 576 piix_setup_idetim_drvs(drvp) 577 struct ata_drive_datas *drvp; 578 { 579 u_int32_t ret = 0; 580 struct channel_softc *chp = drvp->chnl_softc; 581 u_int8_t channel = chp->channel; 582 u_int8_t drive = drvp->drive; 583 584 /* 585 * If drive is using UDMA, timings setups are independant 586 * So just check DMA and PIO here. 587 */ 588 if (drvp->drive_flags & DRIVE_DMA) { 589 /* if mode = DMA mode 0, use compatible timings */ 590 if ((drvp->drive_flags & DRIVE_DMA) && 591 drvp->DMA_mode == 0) { 592 drvp->PIO_mode = 0; 593 return ret; 594 } 595 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 596 /* 597 * PIO and DMA timings are the same, use fast timings for PIO 598 * too, else use compat timings. 599 */ 600 if ((piix_isp_pio[drvp->PIO_mode] != 601 piix_isp_dma[drvp->DMA_mode]) || 602 (piix_rtc_pio[drvp->PIO_mode] != 603 piix_rtc_dma[drvp->DMA_mode])) 604 drvp->PIO_mode = 0; 605 /* if PIO mode <= 2, use compat timings for PIO */ 606 if (drvp->PIO_mode <= 2) { 607 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 608 channel); 609 return ret; 610 } 611 } 612 613 /* 614 * Now setup PIO modes. If mode < 2, use compat timings. 615 * Else enable fast timings. Enable IORDY and prefetch/post 616 * if PIO mode >= 3. 617 */ 618 619 if (drvp->PIO_mode < 2) 620 return ret; 621 622 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 623 if (drvp->PIO_mode >= 3) { 624 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 625 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 626 } 627 return ret; 628 } 629 630 /* setup values in SIDETIM registers, based on mode */ 631 static u_int32_t 632 piix_setup_sidetim_timings(mode, dma, channel) 633 u_int8_t mode; 634 u_int8_t dma; 635 u_int8_t channel; 636 { 637 if (dma) 638 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 639 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 640 else 641 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 642 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 643 } 644 645 static void 646 artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 647 { 648 struct pciide_channel *cp; 649 bus_size_t cmdsize, ctlsize; 650 pcireg_t interface; 651 int channel; 652 653 if (pciide_chipen(sc, pa) == 0) 654 return; 655 656 aprint_normal("%s: bus-master DMA support present", 657 sc->sc_wdcdev.sc_dev.dv_xname); 658 #ifndef PCIIDE_I31244_ENABLEDMA 659 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 660 PCI_REVISION(pa->pa_class) == 0) { 661 aprint_normal(" but disabled due to rev. 0"); 662 sc->sc_dma_ok = 0; 663 } else 664 #endif 665 pciide_mapreg_dma(sc, pa); 666 aprint_normal("\n"); 667 668 /* 669 * XXX Configure LEDs to show activity. 670 */ 671 672 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 673 WDC_CAPABILITY_MODE; 674 sc->sc_wdcdev.PIO_cap = 4; 675 if (sc->sc_dma_ok) { 676 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 677 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 678 sc->sc_wdcdev.irqack = pciide_irqack; 679 sc->sc_wdcdev.DMA_cap = 2; 680 sc->sc_wdcdev.UDMA_cap = 6; 681 } 682 sc->sc_wdcdev.set_modes = sata_setup_channel; 683 684 sc->sc_wdcdev.channels = sc->wdc_chanarray; 685 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 686 687 interface = PCI_INTERFACE(pa->pa_class); 688 689 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 690 cp = &sc->pciide_channels[channel]; 691 if (pciide_chansetup(sc, channel, interface) == 0) 692 continue; 693 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 694 pciide_pci_intr); 695 } 696 } 697
Indexes created Mon Oct 20 05:10:11 GMT 2025