piixide.c revision 1.40
1 /* $NetBSD: piixide.c,v 1.40 2007/08/31 01:35:07 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.40 2007/08/31 01:35:07 xtraeme Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static void piixide_powerhook(int, void *); 54 static int piixide_match(struct device *, struct cfdata *, void *); 55 static void piixide_attach(struct device *, struct device *, void *); 56 57 static const struct pciide_product_desc pciide_intel_products[] = { 58 { PCI_PRODUCT_INTEL_82092AA, 59 0, 60 "Intel 82092AA IDE controller", 61 default_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371FB_IDE, 64 0, 65 "Intel 82371FB IDE controller (PIIX)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371SB_IDE, 69 0, 70 "Intel 82371SB IDE Interface (PIIX3)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82371AB_IDE, 74 0, 75 "Intel 82371AB IDE controller (PIIX4)", 76 piix_chip_map, 77 }, 78 { PCI_PRODUCT_INTEL_82440MX_IDE, 79 0, 80 "Intel 82440MX IDE controller", 81 piix_chip_map 82 }, 83 { PCI_PRODUCT_INTEL_82801AA_IDE, 84 0, 85 "Intel 82801AA IDE Controller (ICH)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801AB_IDE, 89 0, 90 "Intel 82801AB IDE Controller (ICH0)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BA_IDE, 94 0, 95 "Intel 82801BA IDE Controller (ICH2)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801BAM_IDE, 99 0, 100 "Intel 82801BAM IDE Controller (ICH2-M)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 109 0, 110 "Intel 82801CA IDE Controller (ICH3)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DB_IDE, 114 0, 115 "Intel 82801DB IDE Controller (ICH4)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801DBM_IDE, 119 0, 120 "Intel 82801DBM IDE Controller (ICH4-M)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_IDE, 124 0, 125 "Intel 82801EB IDE Controller (ICH5)", 126 piix_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801EB_SATA, 129 0, 130 "Intel 82801EB Serial ATA Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_82801ER_SATA, 134 0, 135 "Intel 82801ER Serial ATA/Raid Controller", 136 piixsata_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_IDE, 139 0, 140 "Intel 6300ESB IDE Controller (ICH5)", 141 piix_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_6300ESB_SATA, 144 0, 145 "Intel 6300ESB Serial ATA Controller", 146 piixsata_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_6300ESB_RAID, 149 0, 150 "Intel 6300ESB Serial ATA/RAID Controller", 151 piixsata_chip_map, 152 }, 153 { PCI_PRODUCT_INTEL_82801FB_IDE, 154 0, 155 "Intel 82801FB IDE Controller (ICH6)", 156 piix_chip_map, 157 }, 158 { PCI_PRODUCT_INTEL_82801FB_SATA, 159 0, 160 "Intel 82801FB Serial ATA/Raid Controller", 161 piixsata_chip_map, 162 }, 163 { PCI_PRODUCT_INTEL_82801FR_SATA, 164 0, 165 "Intel 82801FR Serial ATA/Raid Controller", 166 piixsata_chip_map, 167 }, 168 { PCI_PRODUCT_INTEL_82801FBM_SATA, 169 0, 170 "Intel 82801FBM Serial ATA Controller (ICH6)", 171 piixsata_chip_map, 172 }, 173 { PCI_PRODUCT_INTEL_82801G_IDE, 174 0, 175 "Intel 82801GB/GR IDE Controller (ICH7)", 176 piix_chip_map, 177 }, 178 { PCI_PRODUCT_INTEL_82801G_SATA, 179 0, 180 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 181 piixsata_chip_map, 182 }, 183 { PCI_PRODUCT_INTEL_82801GBM_SATA, 184 0, 185 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 186 piixsata_chip_map, 187 }, 188 { PCI_PRODUCT_INTEL_82801H_SATA_1, 189 0, 190 "Intel 82801H Serial ATA Controller (ICH8)", 191 piixsata_chip_map, 192 }, 193 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 194 0, 195 "Intel 82801H Serial ATA RAID Controller (ICH8)", 196 piixsata_chip_map, 197 }, 198 { PCI_PRODUCT_INTEL_82801H_SATA_2, 199 0, 200 "Intel 82801H Serial ATA Controller (ICH8)", 201 piixsata_chip_map, 202 }, 203 { PCI_PRODUCT_INTEL_82801HBM_IDE, 204 0, 205 "Intel 82801HBM IDE Controller (ICH8M)", 206 piix_chip_map, 207 }, 208 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 209 0, 210 "Intel 82801HBM Serial ATA Controller (ICH8M)", 211 piixsata_chip_map, 212 }, 213 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 214 0, 215 "Intel 82801HBM Serial ATA Controller (ICH8M)", 216 piixsata_chip_map, 217 }, 218 { PCI_PRODUCT_INTEL_63XXESB_IDE, 219 0, 220 "Intel 631xESB/632xESB IDE Controller", 221 piix_chip_map, 222 }, 223 { PCI_PRODUCT_INTEL_82801I_SATA_1, 224 0, 225 "Intel 82801I Serial ATA Controller (ICH9)", 226 piixsata_chip_map, 227 }, 228 { PCI_PRODUCT_INTEL_82801I_SATA_2, 229 0, 230 "Intel 82801I Serial ATA Controller (ICH9)", 231 piixsata_chip_map, 232 }, 233 { PCI_PRODUCT_INTEL_82801I_SATA_3, 234 0, 235 "Intel 82801I Serial ATA Controller (ICH9)", 236 piixsata_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_63XXESB_SATA, 239 0, 240 "Intel 631xESB/632xESB Serial ATA Controller", 241 piixsata_chip_map, 242 }, 243 { 0, 244 0, 245 NULL, 246 NULL 247 } 248 }; 249 250 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 251 piixide_match, piixide_attach, NULL, NULL); 252 253 static int 254 piixide_match(struct device *parent, struct cfdata *match, 255 void *aux) 256 { 257 struct pci_attach_args *pa = aux; 258 259 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 260 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 261 return (2); 262 } 263 return (0); 264 } 265 266 static void 267 piixide_attach(struct device *parent, struct device *self, void *aux) 268 { 269 struct pci_attach_args *pa = aux; 270 struct pciide_softc *sc = (struct pciide_softc *)self; 271 272 pciide_common_attach(sc, pa, 273 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 274 275 /* Setup our powerhook */ 276 sc->sc_powerhook = powerhook_establish( 277 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, piixide_powerhook, sc); 278 if (sc->sc_powerhook == NULL) 279 printf("%s: WARNING: unable to establish PCI power hook\n", 280 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 281 } 282 283 static void 284 piixide_powerhook(int why, void *hdl) 285 { 286 struct pciide_softc *sc = (struct pciide_softc *)hdl; 287 288 switch (why) { 289 case PWR_SUSPEND: 290 case PWR_STANDBY: 291 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 292 sc->sc_idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 293 PIIX_IDETIM); 294 sc->sc_udmatim = pci_conf_read(sc->sc_pc, sc->sc_tag, 295 PIIX_UDMATIM); 296 break; 297 case PWR_RESUME: 298 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 299 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 300 sc->sc_idetim); 301 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 302 sc->sc_udmatim); 303 break; 304 case PWR_SOFTSUSPEND: 305 case PWR_SOFTSTANDBY: 306 case PWR_SOFTRESUME: 307 break; 308 } 309 310 return; 311 } 312 313 static void 314 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 315 { 316 struct pciide_channel *cp; 317 int channel; 318 u_int32_t idetim; 319 bus_size_t cmdsize, ctlsize; 320 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 321 322 if (pciide_chipen(sc, pa) == 0) 323 return; 324 325 aprint_verbose("%s: bus-master DMA support present", 326 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 327 pciide_mapreg_dma(sc, pa); 328 aprint_verbose("\n"); 329 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 330 if (sc->sc_dma_ok) { 331 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 332 sc->sc_wdcdev.irqack = pciide_irqack; 333 /* Do all revisions require DMA alignment workaround? */ 334 sc->sc_wdcdev.dma_init = piix_dma_init; 335 switch(sc->sc_pp->ide_product) { 336 case PCI_PRODUCT_INTEL_82371AB_IDE: 337 case PCI_PRODUCT_INTEL_82440MX_IDE: 338 case PCI_PRODUCT_INTEL_82801AA_IDE: 339 case PCI_PRODUCT_INTEL_82801AB_IDE: 340 case PCI_PRODUCT_INTEL_82801BA_IDE: 341 case PCI_PRODUCT_INTEL_82801BAM_IDE: 342 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 343 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 344 case PCI_PRODUCT_INTEL_82801DB_IDE: 345 case PCI_PRODUCT_INTEL_82801DBM_IDE: 346 case PCI_PRODUCT_INTEL_82801EB_IDE: 347 case PCI_PRODUCT_INTEL_6300ESB_IDE: 348 case PCI_PRODUCT_INTEL_82801FB_IDE: 349 case PCI_PRODUCT_INTEL_82801G_IDE: 350 case PCI_PRODUCT_INTEL_82801HBM_IDE: 351 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 352 } 353 } 354 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 355 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 356 switch(sc->sc_pp->ide_product) { 357 case PCI_PRODUCT_INTEL_82801AA_IDE: 358 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 359 break; 360 case PCI_PRODUCT_INTEL_82801BA_IDE: 361 case PCI_PRODUCT_INTEL_82801BAM_IDE: 362 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 363 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 364 case PCI_PRODUCT_INTEL_82801DB_IDE: 365 case PCI_PRODUCT_INTEL_82801DBM_IDE: 366 case PCI_PRODUCT_INTEL_82801EB_IDE: 367 case PCI_PRODUCT_INTEL_6300ESB_IDE: 368 case PCI_PRODUCT_INTEL_82801FB_IDE: 369 case PCI_PRODUCT_INTEL_82801G_IDE: 370 case PCI_PRODUCT_INTEL_82801HBM_IDE: 371 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 372 break; 373 default: 374 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 375 } 376 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 377 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 378 else 379 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 380 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 381 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 382 383 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 384 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 385 DEBUG_PROBE); 386 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 387 ATADEBUG_PRINT((", sidetim=0x%x", 388 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 389 DEBUG_PROBE); 390 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 391 ATADEBUG_PRINT((", udamreg 0x%x", 392 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 393 DEBUG_PROBE); 394 } 395 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 396 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 397 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 398 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 400 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 402 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 404 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 405 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 406 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 407 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 408 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 409 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 410 DEBUG_PROBE); 411 } 412 413 } 414 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 415 416 wdc_allocate_regs(&sc->sc_wdcdev); 417 418 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 419 channel++) { 420 cp = &sc->pciide_channels[channel]; 421 if (pciide_chansetup(sc, channel, interface) == 0) 422 continue; 423 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 424 if ((PIIX_IDETIM_READ(idetim, channel) & 425 PIIX_IDETIM_IDE) == 0) { 426 #if 1 427 aprint_normal("%s: %s channel ignored (disabled)\n", 428 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 429 cp->ata_channel.ch_flags |= ATACH_DISABLED; 430 continue; 431 #else 432 pcireg_t interface; 433 434 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 435 channel); 436 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 437 idetim); 438 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 439 sc->sc_tag, PCI_CLASS_REG)); 440 aprint_normal("channel %d idetim=%08x interface=%02x\n", 441 channel, idetim, interface); 442 #endif 443 } 444 pciide_mapchan(pa, cp, interface, 445 &cmdsize, &ctlsize, pciide_pci_intr); 446 } 447 448 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 449 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 450 DEBUG_PROBE); 451 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 452 ATADEBUG_PRINT((", sidetim=0x%x", 453 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 454 DEBUG_PROBE); 455 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 456 ATADEBUG_PRINT((", udamreg 0x%x", 457 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 458 DEBUG_PROBE); 459 } 460 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 461 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 462 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 472 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 473 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 474 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 475 DEBUG_PROBE); 476 } 477 } 478 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 479 } 480 481 static void 482 piix_setup_channel(struct ata_channel *chp) 483 { 484 u_int8_t mode[2], drive; 485 u_int32_t oidetim, idetim, idedma_ctl; 486 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 487 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 488 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 489 490 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 491 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 492 idedma_ctl = 0; 493 494 /* set up new idetim: Enable IDE registers decode */ 495 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 496 chp->ch_channel); 497 498 /* setup DMA */ 499 pciide_channel_dma_setup(cp); 500 501 /* 502 * Here we have to mess up with drives mode: PIIX can't have 503 * different timings for master and slave drives. 504 * We need to find the best combination. 505 */ 506 507 /* If both drives supports DMA, take the lower mode */ 508 if ((drvp[0].drive_flags & DRIVE_DMA) && 509 (drvp[1].drive_flags & DRIVE_DMA)) { 510 mode[0] = mode[1] = 511 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 512 drvp[0].DMA_mode = mode[0]; 513 drvp[1].DMA_mode = mode[1]; 514 goto ok; 515 } 516 /* 517 * If only one drive supports DMA, use its mode, and 518 * put the other one in PIO mode 0 if mode not compatible 519 */ 520 if (drvp[0].drive_flags & DRIVE_DMA) { 521 mode[0] = drvp[0].DMA_mode; 522 mode[1] = drvp[1].PIO_mode; 523 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 524 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 525 mode[1] = drvp[1].PIO_mode = 0; 526 goto ok; 527 } 528 if (drvp[1].drive_flags & DRIVE_DMA) { 529 mode[1] = drvp[1].DMA_mode; 530 mode[0] = drvp[0].PIO_mode; 531 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 532 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 533 mode[0] = drvp[0].PIO_mode = 0; 534 goto ok; 535 } 536 /* 537 * If both drives are not DMA, takes the lower mode, unless 538 * one of them is PIO mode < 2 539 */ 540 if (drvp[0].PIO_mode < 2) { 541 mode[0] = drvp[0].PIO_mode = 0; 542 mode[1] = drvp[1].PIO_mode; 543 } else if (drvp[1].PIO_mode < 2) { 544 mode[1] = drvp[1].PIO_mode = 0; 545 mode[0] = drvp[0].PIO_mode; 546 } else { 547 mode[0] = mode[1] = 548 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 549 drvp[0].PIO_mode = mode[0]; 550 drvp[1].PIO_mode = mode[1]; 551 } 552 ok: /* The modes are setup */ 553 for (drive = 0; drive < 2; drive++) { 554 if (drvp[drive].drive_flags & DRIVE_DMA) { 555 idetim |= piix_setup_idetim_timings( 556 mode[drive], 1, chp->ch_channel); 557 goto end; 558 } 559 } 560 /* If we are there, none of the drives are DMA */ 561 if (mode[0] >= 2) 562 idetim |= piix_setup_idetim_timings( 563 mode[0], 0, chp->ch_channel); 564 else 565 idetim |= piix_setup_idetim_timings( 566 mode[1], 0, chp->ch_channel); 567 end: /* 568 * timing mode is now set up in the controller. Enable 569 * it per-drive 570 */ 571 for (drive = 0; drive < 2; drive++) { 572 /* If no drive, skip */ 573 if ((drvp[drive].drive_flags & DRIVE) == 0) 574 continue; 575 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 576 if (drvp[drive].drive_flags & DRIVE_DMA) 577 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 578 } 579 if (idedma_ctl != 0) { 580 /* Add software bits in status register */ 581 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 582 idedma_ctl); 583 } 584 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 585 } 586 587 static void 588 piix3_4_setup_channel(struct ata_channel *chp) 589 { 590 struct ata_drive_datas *drvp; 591 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 592 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 593 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 594 struct wdc_softc *wdc = &sc->sc_wdcdev; 595 int drive, s; 596 int channel = chp->ch_channel; 597 598 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 599 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 600 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 601 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 602 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 603 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 604 PIIX_SIDETIM_RTC_MASK(channel)); 605 idedma_ctl = 0; 606 607 /* set up new idetim: Enable IDE registers decode */ 608 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 609 610 /* setup DMA if needed */ 611 pciide_channel_dma_setup(cp); 612 613 for (drive = 0; drive < 2; drive++) { 614 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 615 PIIX_UDMATIM_SET(0x3, channel, drive)); 616 drvp = &chp->ch_drive[drive]; 617 /* If no drive, skip */ 618 if ((drvp->drive_flags & DRIVE) == 0) 619 continue; 620 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 621 (drvp->drive_flags & DRIVE_UDMA) == 0)) 622 goto pio; 623 624 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 625 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 626 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 632 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 633 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 636 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 637 ideconf |= PIIX_CONFIG_PINGPONG; 638 } 639 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 640 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 641 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 642 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 643 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 644 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 645 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 646 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 647 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 648 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 649 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 650 /* setup Ultra/100 */ 651 if (drvp->UDMA_mode > 2 && 652 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 653 drvp->UDMA_mode = 2; 654 if (drvp->UDMA_mode > 4) { 655 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 656 } else { 657 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 658 if (drvp->UDMA_mode > 2) { 659 ideconf |= PIIX_CONFIG_UDMA66(channel, 660 drive); 661 } else { 662 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 663 drive); 664 } 665 } 666 } 667 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 668 /* setup Ultra/66 */ 669 if (drvp->UDMA_mode > 2 && 670 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 671 drvp->UDMA_mode = 2; 672 if (drvp->UDMA_mode > 2) 673 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 674 else 675 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 676 } 677 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 678 (drvp->drive_flags & DRIVE_UDMA)) { 679 /* use Ultra/DMA */ 680 s = splbio(); 681 drvp->drive_flags &= ~DRIVE_DMA; 682 splx(s); 683 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 684 udmareg |= PIIX_UDMATIM_SET( 685 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 686 } else { 687 /* use Multiword DMA */ 688 s = splbio(); 689 drvp->drive_flags &= ~DRIVE_UDMA; 690 splx(s); 691 if (drive == 0) { 692 idetim |= piix_setup_idetim_timings( 693 drvp->DMA_mode, 1, channel); 694 } else { 695 sidetim |= piix_setup_sidetim_timings( 696 drvp->DMA_mode, 1, channel); 697 idetim =PIIX_IDETIM_SET(idetim, 698 PIIX_IDETIM_SITRE, channel); 699 } 700 } 701 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 702 703 pio: /* use PIO mode */ 704 idetim |= piix_setup_idetim_drvs(drvp); 705 if (drive == 0) { 706 idetim |= piix_setup_idetim_timings( 707 drvp->PIO_mode, 0, channel); 708 } else { 709 sidetim |= piix_setup_sidetim_timings( 710 drvp->PIO_mode, 0, channel); 711 idetim =PIIX_IDETIM_SET(idetim, 712 PIIX_IDETIM_SITRE, channel); 713 } 714 } 715 if (idedma_ctl != 0) { 716 /* Add software bits in status register */ 717 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 718 idedma_ctl); 719 } 720 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 721 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 722 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 723 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 724 } 725 726 727 /* setup ISP and RTC fields, based on mode */ 728 static u_int32_t 729 piix_setup_idetim_timings(mode, dma, channel) 730 u_int8_t mode; 731 u_int8_t dma; 732 u_int8_t channel; 733 { 734 735 if (dma) 736 return PIIX_IDETIM_SET(0, 737 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 738 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 739 channel); 740 else 741 return PIIX_IDETIM_SET(0, 742 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 743 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 744 channel); 745 } 746 747 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 748 static u_int32_t 749 piix_setup_idetim_drvs(drvp) 750 struct ata_drive_datas *drvp; 751 { 752 u_int32_t ret = 0; 753 struct ata_channel *chp = drvp->chnl_softc; 754 u_int8_t channel = chp->ch_channel; 755 u_int8_t drive = drvp->drive; 756 757 /* 758 * If drive is using UDMA, timings setups are independent 759 * So just check DMA and PIO here. 760 */ 761 if (drvp->drive_flags & DRIVE_DMA) { 762 /* if mode = DMA mode 0, use compatible timings */ 763 if ((drvp->drive_flags & DRIVE_DMA) && 764 drvp->DMA_mode == 0) { 765 drvp->PIO_mode = 0; 766 return ret; 767 } 768 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 769 /* 770 * PIO and DMA timings are the same, use fast timings for PIO 771 * too, else use compat timings. 772 */ 773 if ((piix_isp_pio[drvp->PIO_mode] != 774 piix_isp_dma[drvp->DMA_mode]) || 775 (piix_rtc_pio[drvp->PIO_mode] != 776 piix_rtc_dma[drvp->DMA_mode])) 777 drvp->PIO_mode = 0; 778 /* if PIO mode <= 2, use compat timings for PIO */ 779 if (drvp->PIO_mode <= 2) { 780 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 781 channel); 782 return ret; 783 } 784 } 785 786 /* 787 * Now setup PIO modes. If mode < 2, use compat timings. 788 * Else enable fast timings. Enable IORDY and prefetch/post 789 * if PIO mode >= 3. 790 */ 791 792 if (drvp->PIO_mode < 2) 793 return ret; 794 795 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 796 if (drvp->PIO_mode >= 3) { 797 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 798 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 799 } 800 return ret; 801 } 802 803 /* setup values in SIDETIM registers, based on mode */ 804 static u_int32_t 805 piix_setup_sidetim_timings(mode, dma, channel) 806 u_int8_t mode; 807 u_int8_t dma; 808 u_int8_t channel; 809 { 810 if (dma) 811 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 812 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 813 else 814 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 815 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 816 } 817 818 static void 819 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 820 { 821 struct pciide_channel *cp; 822 bus_size_t cmdsize, ctlsize; 823 pcireg_t interface, cmdsts; 824 int channel; 825 826 if (pciide_chipen(sc, pa) == 0) 827 return; 828 829 aprint_verbose("%s: bus-master DMA support present", 830 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 831 pciide_mapreg_dma(sc, pa); 832 aprint_verbose("\n"); 833 834 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 835 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 836 if (sc->sc_dma_ok) { 837 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 838 sc->sc_wdcdev.irqack = pciide_irqack; 839 /* Do all revisions require DMA alignment workaround? */ 840 sc->sc_wdcdev.dma_init = piix_dma_init; 841 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 842 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 843 } 844 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 845 846 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 847 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 848 849 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 850 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 851 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 852 853 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 854 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 855 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 856 857 interface = PCI_INTERFACE(pa->pa_class); 858 859 wdc_allocate_regs(&sc->sc_wdcdev); 860 861 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 862 channel++) { 863 cp = &sc->pciide_channels[channel]; 864 if (pciide_chansetup(sc, channel, interface) == 0) 865 continue; 866 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 867 pciide_pci_intr); 868 } 869 } 870 871 static int 872 piix_dma_init(void *v, int channel, int drive, void *databuf, 873 size_t datalen, int flags) 874 { 875 876 /* use PIO for unaligned transfer */ 877 if (((uintptr_t)databuf) & 0x1) 878 return EINVAL; 879 880 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 881 } 882
Indexes created Wed Oct 15 16:09:53 GMT 2025