piixide.c revision 1.41.6.1
1 /* $NetBSD: piixide.c,v 1.41.6.1 2008/02/18 21:05:58 mjf Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.41.6.1 2008/02/18 21:05:58 mjf Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static void piixide_powerhook(int, void *); 54 static int piixide_match(struct device *, struct cfdata *, void *); 55 static void piixide_attach(struct device *, struct device *, void *); 56 57 static const struct pciide_product_desc pciide_intel_products[] = { 58 { PCI_PRODUCT_INTEL_82092AA, 59 0, 60 "Intel 82092AA IDE controller", 61 default_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371FB_IDE, 64 0, 65 "Intel 82371FB IDE controller (PIIX)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371SB_IDE, 69 0, 70 "Intel 82371SB IDE Interface (PIIX3)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82371AB_IDE, 74 0, 75 "Intel 82371AB IDE controller (PIIX4)", 76 piix_chip_map, 77 }, 78 { PCI_PRODUCT_INTEL_82440MX_IDE, 79 0, 80 "Intel 82440MX IDE controller", 81 piix_chip_map 82 }, 83 { PCI_PRODUCT_INTEL_82801AA_IDE, 84 0, 85 "Intel 82801AA IDE Controller (ICH)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801AB_IDE, 89 0, 90 "Intel 82801AB IDE Controller (ICH0)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BA_IDE, 94 0, 95 "Intel 82801BA IDE Controller (ICH2)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801BAM_IDE, 99 0, 100 "Intel 82801BAM IDE Controller (ICH2-M)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 109 0, 110 "Intel 82801CA IDE Controller (ICH3)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DB_IDE, 114 0, 115 "Intel 82801DB IDE Controller (ICH4)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801DBM_IDE, 119 0, 120 "Intel 82801DBM IDE Controller (ICH4-M)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_IDE, 124 0, 125 "Intel 82801EB IDE Controller (ICH5)", 126 piix_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801EB_SATA, 129 0, 130 "Intel 82801EB Serial ATA Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_82801ER_SATA, 134 0, 135 "Intel 82801ER Serial ATA/Raid Controller", 136 piixsata_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_IDE, 139 0, 140 "Intel 6300ESB IDE Controller (ICH5)", 141 piix_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_6300ESB_SATA, 144 0, 145 "Intel 6300ESB Serial ATA Controller", 146 piixsata_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_6300ESB_RAID, 149 0, 150 "Intel 6300ESB Serial ATA/RAID Controller", 151 piixsata_chip_map, 152 }, 153 { PCI_PRODUCT_INTEL_82801FB_IDE, 154 0, 155 "Intel 82801FB IDE Controller (ICH6)", 156 piix_chip_map, 157 }, 158 { PCI_PRODUCT_INTEL_82801FB_SATA, 159 0, 160 "Intel 82801FB Serial ATA/Raid Controller", 161 piixsata_chip_map, 162 }, 163 { PCI_PRODUCT_INTEL_82801FR_SATA, 164 0, 165 "Intel 82801FR Serial ATA/Raid Controller", 166 piixsata_chip_map, 167 }, 168 { PCI_PRODUCT_INTEL_82801FBM_SATA, 169 0, 170 "Intel 82801FBM Serial ATA Controller (ICH6)", 171 piixsata_chip_map, 172 }, 173 { PCI_PRODUCT_INTEL_82801G_IDE, 174 0, 175 "Intel 82801GB/GR IDE Controller (ICH7)", 176 piix_chip_map, 177 }, 178 { PCI_PRODUCT_INTEL_82801G_SATA, 179 0, 180 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 181 piixsata_chip_map, 182 }, 183 { PCI_PRODUCT_INTEL_82801GBM_SATA, 184 0, 185 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 186 piixsata_chip_map, 187 }, 188 { PCI_PRODUCT_INTEL_82801H_SATA_1, 189 0, 190 "Intel 82801H Serial ATA Controller (ICH8)", 191 piixsata_chip_map, 192 }, 193 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 194 0, 195 "Intel 82801H Serial ATA RAID Controller (ICH8)", 196 piixsata_chip_map, 197 }, 198 { PCI_PRODUCT_INTEL_82801H_SATA_2, 199 0, 200 "Intel 82801H Serial ATA Controller (ICH8)", 201 piixsata_chip_map, 202 }, 203 { PCI_PRODUCT_INTEL_82801HBM_IDE, 204 0, 205 "Intel 82801HBM IDE Controller (ICH8M)", 206 piix_chip_map, 207 }, 208 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 209 0, 210 "Intel 82801HBM Serial ATA Controller (ICH8M)", 211 piixsata_chip_map, 212 }, 213 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 214 0, 215 "Intel 82801HBM Serial ATA Controller (ICH8M)", 216 piixsata_chip_map, 217 }, 218 { PCI_PRODUCT_INTEL_82801HEM_SATA, 219 0, 220 "Intel 82801HEM Serial ATA Controller (ICH8M)", 221 piixsata_chip_map, 222 }, 223 { PCI_PRODUCT_INTEL_63XXESB_IDE, 224 0, 225 "Intel 631xESB/632xESB IDE Controller", 226 piix_chip_map, 227 }, 228 { PCI_PRODUCT_INTEL_82801I_SATA_1, 229 0, 230 "Intel 82801I Serial ATA Controller (ICH9)", 231 piixsata_chip_map, 232 }, 233 { PCI_PRODUCT_INTEL_82801I_SATA_2, 234 0, 235 "Intel 82801I Serial ATA Controller (ICH9)", 236 piixsata_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_82801I_SATA_3, 239 0, 240 "Intel 82801I Serial ATA Controller (ICH9)", 241 piixsata_chip_map, 242 }, 243 { PCI_PRODUCT_INTEL_63XXESB_SATA, 244 0, 245 "Intel 631xESB/632xESB Serial ATA Controller", 246 piixsata_chip_map, 247 }, 248 { 0, 249 0, 250 NULL, 251 NULL 252 } 253 }; 254 255 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 256 piixide_match, piixide_attach, NULL, NULL); 257 258 static int 259 piixide_match(struct device *parent, struct cfdata *match, 260 void *aux) 261 { 262 struct pci_attach_args *pa = aux; 263 264 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 265 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 266 return (2); 267 } 268 return (0); 269 } 270 271 static void 272 piixide_attach(struct device *parent, struct device *self, void *aux) 273 { 274 struct pci_attach_args *pa = aux; 275 struct pciide_softc *sc = (struct pciide_softc *)self; 276 277 pciide_common_attach(sc, pa, 278 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 279 280 /* Setup our powerhook */ 281 sc->sc_powerhook = powerhook_establish( 282 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, piixide_powerhook, sc); 283 if (sc->sc_powerhook == NULL) 284 printf("%s: WARNING: unable to establish PCI power hook\n", 285 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 286 } 287 288 static void 289 piixide_powerhook(int why, void *hdl) 290 { 291 struct pciide_softc *sc = (struct pciide_softc *)hdl; 292 293 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 294 sc->sc_pm_reg[0]); 295 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 296 sc->sc_pm_reg[1]); 297 298 return true; 299 } 300 301 static bool 302 piixide_suspend(device_t dv) 303 { 304 struct pciide_softc *sc = device_private(dv); 305 306 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 307 PIIX_IDETIM); 308 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 309 PIIX_UDMAREG); 310 311 return; 312 } 313 314 static void 315 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 316 { 317 struct pciide_channel *cp; 318 int channel; 319 u_int32_t idetim; 320 bus_size_t cmdsize, ctlsize; 321 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 322 323 if (pciide_chipen(sc, pa) == 0) 324 return; 325 326 aprint_verbose("%s: bus-master DMA support present", 327 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 328 pciide_mapreg_dma(sc, pa); 329 aprint_verbose("\n"); 330 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 331 if (sc->sc_dma_ok) { 332 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 333 sc->sc_wdcdev.irqack = pciide_irqack; 334 /* Do all revisions require DMA alignment workaround? */ 335 sc->sc_wdcdev.dma_init = piix_dma_init; 336 switch(sc->sc_pp->ide_product) { 337 case PCI_PRODUCT_INTEL_82371AB_IDE: 338 case PCI_PRODUCT_INTEL_82440MX_IDE: 339 case PCI_PRODUCT_INTEL_82801AA_IDE: 340 case PCI_PRODUCT_INTEL_82801AB_IDE: 341 case PCI_PRODUCT_INTEL_82801BA_IDE: 342 case PCI_PRODUCT_INTEL_82801BAM_IDE: 343 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 344 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 345 case PCI_PRODUCT_INTEL_82801DB_IDE: 346 case PCI_PRODUCT_INTEL_82801DBM_IDE: 347 case PCI_PRODUCT_INTEL_82801EB_IDE: 348 case PCI_PRODUCT_INTEL_6300ESB_IDE: 349 case PCI_PRODUCT_INTEL_82801FB_IDE: 350 case PCI_PRODUCT_INTEL_82801G_IDE: 351 case PCI_PRODUCT_INTEL_82801HBM_IDE: 352 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 353 } 354 } 355 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 356 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 357 switch(sc->sc_pp->ide_product) { 358 case PCI_PRODUCT_INTEL_82801AA_IDE: 359 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 360 break; 361 case PCI_PRODUCT_INTEL_82801BA_IDE: 362 case PCI_PRODUCT_INTEL_82801BAM_IDE: 363 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 364 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 365 case PCI_PRODUCT_INTEL_82801DB_IDE: 366 case PCI_PRODUCT_INTEL_82801DBM_IDE: 367 case PCI_PRODUCT_INTEL_82801EB_IDE: 368 case PCI_PRODUCT_INTEL_6300ESB_IDE: 369 case PCI_PRODUCT_INTEL_82801FB_IDE: 370 case PCI_PRODUCT_INTEL_82801G_IDE: 371 case PCI_PRODUCT_INTEL_82801HBM_IDE: 372 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 373 break; 374 default: 375 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 376 } 377 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 378 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 379 else 380 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 381 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 382 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 383 384 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 385 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 386 DEBUG_PROBE); 387 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 388 ATADEBUG_PRINT((", sidetim=0x%x", 389 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 390 DEBUG_PROBE); 391 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 392 ATADEBUG_PRINT((", udamreg 0x%x", 393 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 394 DEBUG_PROBE); 395 } 396 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 397 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 398 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 400 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 402 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 404 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 405 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 406 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 407 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 408 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 409 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 410 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 411 DEBUG_PROBE); 412 } 413 414 } 415 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 416 417 wdc_allocate_regs(&sc->sc_wdcdev); 418 419 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 420 channel++) { 421 cp = &sc->pciide_channels[channel]; 422 if (pciide_chansetup(sc, channel, interface) == 0) 423 continue; 424 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 425 if ((PIIX_IDETIM_READ(idetim, channel) & 426 PIIX_IDETIM_IDE) == 0) { 427 #if 1 428 aprint_normal("%s: %s channel ignored (disabled)\n", 429 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 430 cp->ata_channel.ch_flags |= ATACH_DISABLED; 431 continue; 432 #else 433 pcireg_t interface; 434 435 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 436 channel); 437 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 438 idetim); 439 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 440 sc->sc_tag, PCI_CLASS_REG)); 441 aprint_normal("channel %d idetim=%08x interface=%02x\n", 442 channel, idetim, interface); 443 #endif 444 } 445 pciide_mapchan(pa, cp, interface, 446 &cmdsize, &ctlsize, pciide_pci_intr); 447 } 448 449 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 450 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 451 DEBUG_PROBE); 452 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 453 ATADEBUG_PRINT((", sidetim=0x%x", 454 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 455 DEBUG_PROBE); 456 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 457 ATADEBUG_PRINT((", udamreg 0x%x", 458 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 459 DEBUG_PROBE); 460 } 461 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 462 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 472 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 473 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 474 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 475 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 476 DEBUG_PROBE); 477 } 478 } 479 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 480 } 481 482 static void 483 piix_setup_channel(struct ata_channel *chp) 484 { 485 u_int8_t mode[2], drive; 486 u_int32_t oidetim, idetim, idedma_ctl; 487 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 488 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 489 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 490 491 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 492 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 493 idedma_ctl = 0; 494 495 /* set up new idetim: Enable IDE registers decode */ 496 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 497 chp->ch_channel); 498 499 /* setup DMA */ 500 pciide_channel_dma_setup(cp); 501 502 /* 503 * Here we have to mess up with drives mode: PIIX can't have 504 * different timings for master and slave drives. 505 * We need to find the best combination. 506 */ 507 508 /* If both drives supports DMA, take the lower mode */ 509 if ((drvp[0].drive_flags & DRIVE_DMA) && 510 (drvp[1].drive_flags & DRIVE_DMA)) { 511 mode[0] = mode[1] = 512 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 513 drvp[0].DMA_mode = mode[0]; 514 drvp[1].DMA_mode = mode[1]; 515 goto ok; 516 } 517 /* 518 * If only one drive supports DMA, use its mode, and 519 * put the other one in PIO mode 0 if mode not compatible 520 */ 521 if (drvp[0].drive_flags & DRIVE_DMA) { 522 mode[0] = drvp[0].DMA_mode; 523 mode[1] = drvp[1].PIO_mode; 524 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 525 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 526 mode[1] = drvp[1].PIO_mode = 0; 527 goto ok; 528 } 529 if (drvp[1].drive_flags & DRIVE_DMA) { 530 mode[1] = drvp[1].DMA_mode; 531 mode[0] = drvp[0].PIO_mode; 532 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 533 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 534 mode[0] = drvp[0].PIO_mode = 0; 535 goto ok; 536 } 537 /* 538 * If both drives are not DMA, takes the lower mode, unless 539 * one of them is PIO mode < 2 540 */ 541 if (drvp[0].PIO_mode < 2) { 542 mode[0] = drvp[0].PIO_mode = 0; 543 mode[1] = drvp[1].PIO_mode; 544 } else if (drvp[1].PIO_mode < 2) { 545 mode[1] = drvp[1].PIO_mode = 0; 546 mode[0] = drvp[0].PIO_mode; 547 } else { 548 mode[0] = mode[1] = 549 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 550 drvp[0].PIO_mode = mode[0]; 551 drvp[1].PIO_mode = mode[1]; 552 } 553 ok: /* The modes are setup */ 554 for (drive = 0; drive < 2; drive++) { 555 if (drvp[drive].drive_flags & DRIVE_DMA) { 556 idetim |= piix_setup_idetim_timings( 557 mode[drive], 1, chp->ch_channel); 558 goto end; 559 } 560 } 561 /* If we are there, none of the drives are DMA */ 562 if (mode[0] >= 2) 563 idetim |= piix_setup_idetim_timings( 564 mode[0], 0, chp->ch_channel); 565 else 566 idetim |= piix_setup_idetim_timings( 567 mode[1], 0, chp->ch_channel); 568 end: /* 569 * timing mode is now set up in the controller. Enable 570 * it per-drive 571 */ 572 for (drive = 0; drive < 2; drive++) { 573 /* If no drive, skip */ 574 if ((drvp[drive].drive_flags & DRIVE) == 0) 575 continue; 576 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 577 if (drvp[drive].drive_flags & DRIVE_DMA) 578 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 579 } 580 if (idedma_ctl != 0) { 581 /* Add software bits in status register */ 582 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 583 idedma_ctl); 584 } 585 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 586 } 587 588 static void 589 piix3_4_setup_channel(struct ata_channel *chp) 590 { 591 struct ata_drive_datas *drvp; 592 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 593 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 594 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 595 struct wdc_softc *wdc = &sc->sc_wdcdev; 596 int drive, s; 597 int channel = chp->ch_channel; 598 599 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 600 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 601 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 602 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 603 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 604 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 605 PIIX_SIDETIM_RTC_MASK(channel)); 606 idedma_ctl = 0; 607 608 /* set up new idetim: Enable IDE registers decode */ 609 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 610 611 /* setup DMA if needed */ 612 pciide_channel_dma_setup(cp); 613 614 for (drive = 0; drive < 2; drive++) { 615 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 616 PIIX_UDMATIM_SET(0x3, channel, drive)); 617 drvp = &chp->ch_drive[drive]; 618 /* If no drive, skip */ 619 if ((drvp->drive_flags & DRIVE) == 0) 620 continue; 621 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 622 (drvp->drive_flags & DRIVE_UDMA) == 0)) 623 goto pio; 624 625 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 626 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 632 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 633 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 636 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 637 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 638 ideconf |= PIIX_CONFIG_PINGPONG; 639 } 640 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 641 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 642 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 643 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 644 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 645 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 646 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 647 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 648 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 649 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 650 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 651 /* setup Ultra/100 */ 652 if (drvp->UDMA_mode > 2 && 653 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 654 drvp->UDMA_mode = 2; 655 if (drvp->UDMA_mode > 4) { 656 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 657 } else { 658 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 659 if (drvp->UDMA_mode > 2) { 660 ideconf |= PIIX_CONFIG_UDMA66(channel, 661 drive); 662 } else { 663 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 664 drive); 665 } 666 } 667 } 668 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 669 /* setup Ultra/66 */ 670 if (drvp->UDMA_mode > 2 && 671 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 672 drvp->UDMA_mode = 2; 673 if (drvp->UDMA_mode > 2) 674 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 675 else 676 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 677 } 678 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 679 (drvp->drive_flags & DRIVE_UDMA)) { 680 /* use Ultra/DMA */ 681 s = splbio(); 682 drvp->drive_flags &= ~DRIVE_DMA; 683 splx(s); 684 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 685 udmareg |= PIIX_UDMATIM_SET( 686 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 687 } else { 688 /* use Multiword DMA */ 689 s = splbio(); 690 drvp->drive_flags &= ~DRIVE_UDMA; 691 splx(s); 692 if (drive == 0) { 693 idetim |= piix_setup_idetim_timings( 694 drvp->DMA_mode, 1, channel); 695 } else { 696 sidetim |= piix_setup_sidetim_timings( 697 drvp->DMA_mode, 1, channel); 698 idetim =PIIX_IDETIM_SET(idetim, 699 PIIX_IDETIM_SITRE, channel); 700 } 701 } 702 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 703 704 pio: /* use PIO mode */ 705 idetim |= piix_setup_idetim_drvs(drvp); 706 if (drive == 0) { 707 idetim |= piix_setup_idetim_timings( 708 drvp->PIO_mode, 0, channel); 709 } else { 710 sidetim |= piix_setup_sidetim_timings( 711 drvp->PIO_mode, 0, channel); 712 idetim =PIIX_IDETIM_SET(idetim, 713 PIIX_IDETIM_SITRE, channel); 714 } 715 } 716 if (idedma_ctl != 0) { 717 /* Add software bits in status register */ 718 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 719 idedma_ctl); 720 } 721 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 722 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 723 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 724 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 725 } 726 727 728 /* setup ISP and RTC fields, based on mode */ 729 static u_int32_t 730 piix_setup_idetim_timings(mode, dma, channel) 731 u_int8_t mode; 732 u_int8_t dma; 733 u_int8_t channel; 734 { 735 736 if (dma) 737 return PIIX_IDETIM_SET(0, 738 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 739 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 740 channel); 741 else 742 return PIIX_IDETIM_SET(0, 743 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 744 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 745 channel); 746 } 747 748 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 749 static u_int32_t 750 piix_setup_idetim_drvs(drvp) 751 struct ata_drive_datas *drvp; 752 { 753 u_int32_t ret = 0; 754 struct ata_channel *chp = drvp->chnl_softc; 755 u_int8_t channel = chp->ch_channel; 756 u_int8_t drive = drvp->drive; 757 758 /* 759 * If drive is using UDMA, timings setups are independent 760 * So just check DMA and PIO here. 761 */ 762 if (drvp->drive_flags & DRIVE_DMA) { 763 /* if mode = DMA mode 0, use compatible timings */ 764 if ((drvp->drive_flags & DRIVE_DMA) && 765 drvp->DMA_mode == 0) { 766 drvp->PIO_mode = 0; 767 return ret; 768 } 769 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 770 /* 771 * PIO and DMA timings are the same, use fast timings for PIO 772 * too, else use compat timings. 773 */ 774 if ((piix_isp_pio[drvp->PIO_mode] != 775 piix_isp_dma[drvp->DMA_mode]) || 776 (piix_rtc_pio[drvp->PIO_mode] != 777 piix_rtc_dma[drvp->DMA_mode])) 778 drvp->PIO_mode = 0; 779 /* if PIO mode <= 2, use compat timings for PIO */ 780 if (drvp->PIO_mode <= 2) { 781 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 782 channel); 783 return ret; 784 } 785 } 786 787 /* 788 * Now setup PIO modes. If mode < 2, use compat timings. 789 * Else enable fast timings. Enable IORDY and prefetch/post 790 * if PIO mode >= 3. 791 */ 792 793 if (drvp->PIO_mode < 2) 794 return ret; 795 796 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 797 if (drvp->PIO_mode >= 3) { 798 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 799 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 800 } 801 return ret; 802 } 803 804 /* setup values in SIDETIM registers, based on mode */ 805 static u_int32_t 806 piix_setup_sidetim_timings(mode, dma, channel) 807 u_int8_t mode; 808 u_int8_t dma; 809 u_int8_t channel; 810 { 811 if (dma) 812 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 813 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 814 else 815 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 816 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 817 } 818 819 static void 820 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 821 { 822 struct pciide_channel *cp; 823 bus_size_t cmdsize, ctlsize; 824 pcireg_t interface, cmdsts; 825 int channel; 826 827 if (pciide_chipen(sc, pa) == 0) 828 return; 829 830 aprint_verbose("%s: bus-master DMA support present", 831 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 832 pciide_mapreg_dma(sc, pa); 833 aprint_verbose("\n"); 834 835 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 836 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 837 if (sc->sc_dma_ok) { 838 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 839 sc->sc_wdcdev.irqack = pciide_irqack; 840 /* Do all revisions require DMA alignment workaround? */ 841 sc->sc_wdcdev.dma_init = piix_dma_init; 842 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 843 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 844 } 845 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 846 847 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 848 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 849 850 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 851 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 852 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 853 854 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 855 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 856 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 857 858 interface = PCI_INTERFACE(pa->pa_class); 859 860 wdc_allocate_regs(&sc->sc_wdcdev); 861 862 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 863 channel++) { 864 cp = &sc->pciide_channels[channel]; 865 if (pciide_chansetup(sc, channel, interface) == 0) 866 continue; 867 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 868 pciide_pci_intr); 869 } 870 } 871 872 static int 873 piix_dma_init(void *v, int channel, int drive, void *databuf, 874 size_t datalen, int flags) 875 { 876 877 /* use PIO for unaligned transfer */ 878 if (((uintptr_t)databuf) & 0x1) 879 return EINVAL; 880 881 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 882 } 883
Indexes created Sat Oct 25 16:10:12 GMT 2025