piixide.c revision 1.42.2.1
1 /* $NetBSD: piixide.c,v 1.42.2.1 2008/01/08 22:11:17 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.42.2.1 2008/01/08 22:11:17 bouyer Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static bool piixide_resume(device_t); 54 static bool piixide_suspend(device_t); 55 static int piixide_match(struct device *, struct cfdata *, void *); 56 static void piixide_attach(struct device *, struct device *, void *); 57 58 static const struct pciide_product_desc pciide_intel_products[] = { 59 { PCI_PRODUCT_INTEL_82092AA, 60 0, 61 "Intel 82092AA IDE controller", 62 default_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371FB_IDE, 65 0, 66 "Intel 82371FB IDE controller (PIIX)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371SB_IDE, 70 0, 71 "Intel 82371SB IDE Interface (PIIX3)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82371AB_IDE, 75 0, 76 "Intel 82371AB IDE controller (PIIX4)", 77 piix_chip_map, 78 }, 79 { PCI_PRODUCT_INTEL_82440MX_IDE, 80 0, 81 "Intel 82440MX IDE controller", 82 piix_chip_map 83 }, 84 { PCI_PRODUCT_INTEL_82801AA_IDE, 85 0, 86 "Intel 82801AA IDE Controller (ICH)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801AB_IDE, 90 0, 91 "Intel 82801AB IDE Controller (ICH0)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BA_IDE, 95 0, 96 "Intel 82801BA IDE Controller (ICH2)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801BAM_IDE, 100 0, 101 "Intel 82801BAM IDE Controller (ICH2-M)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 110 0, 111 "Intel 82801CA IDE Controller (ICH3)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DB_IDE, 115 0, 116 "Intel 82801DB IDE Controller (ICH4)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801DBM_IDE, 120 0, 121 "Intel 82801DBM IDE Controller (ICH4-M)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_IDE, 125 0, 126 "Intel 82801EB IDE Controller (ICH5)", 127 piix_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801EB_SATA, 130 0, 131 "Intel 82801EB Serial ATA Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_82801ER_SATA, 135 0, 136 "Intel 82801ER Serial ATA/Raid Controller", 137 piixsata_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_IDE, 140 0, 141 "Intel 6300ESB IDE Controller (ICH5)", 142 piix_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_6300ESB_SATA, 145 0, 146 "Intel 6300ESB Serial ATA Controller", 147 piixsata_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_6300ESB_RAID, 150 0, 151 "Intel 6300ESB Serial ATA/RAID Controller", 152 piixsata_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FB_IDE, 155 0, 156 "Intel 82801FB IDE Controller (ICH6)", 157 piix_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FB_SATA, 160 0, 161 "Intel 82801FB Serial ATA/Raid Controller", 162 piixsata_chip_map, 163 }, 164 { PCI_PRODUCT_INTEL_82801FR_SATA, 165 0, 166 "Intel 82801FR Serial ATA/Raid Controller", 167 piixsata_chip_map, 168 }, 169 { PCI_PRODUCT_INTEL_82801FBM_SATA, 170 0, 171 "Intel 82801FBM Serial ATA Controller (ICH6)", 172 piixsata_chip_map, 173 }, 174 { PCI_PRODUCT_INTEL_82801G_IDE, 175 0, 176 "Intel 82801GB/GR IDE Controller (ICH7)", 177 piix_chip_map, 178 }, 179 { PCI_PRODUCT_INTEL_82801G_SATA, 180 0, 181 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 182 piixsata_chip_map, 183 }, 184 { PCI_PRODUCT_INTEL_82801GBM_SATA, 185 0, 186 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 187 piixsata_chip_map, 188 }, 189 { PCI_PRODUCT_INTEL_82801H_SATA_1, 190 0, 191 "Intel 82801H Serial ATA Controller (ICH8)", 192 piixsata_chip_map, 193 }, 194 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 195 0, 196 "Intel 82801H Serial ATA RAID Controller (ICH8)", 197 piixsata_chip_map, 198 }, 199 { PCI_PRODUCT_INTEL_82801H_SATA_2, 200 0, 201 "Intel 82801H Serial ATA Controller (ICH8)", 202 piixsata_chip_map, 203 }, 204 { PCI_PRODUCT_INTEL_82801HBM_IDE, 205 0, 206 "Intel 82801HBM IDE Controller (ICH8M)", 207 piix_chip_map, 208 }, 209 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 210 0, 211 "Intel 82801HBM Serial ATA Controller (ICH8M)", 212 piixsata_chip_map, 213 }, 214 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 215 0, 216 "Intel 82801HBM Serial ATA Controller (ICH8M)", 217 piixsata_chip_map, 218 }, 219 { PCI_PRODUCT_INTEL_82801HEM_SATA, 220 0, 221 "Intel 82801HEM Serial ATA Controller (ICH8M)", 222 piixsata_chip_map, 223 }, 224 { PCI_PRODUCT_INTEL_63XXESB_IDE, 225 0, 226 "Intel 631xESB/632xESB IDE Controller", 227 piix_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82801I_SATA_1, 230 0, 231 "Intel 82801I Serial ATA Controller (ICH9)", 232 piixsata_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82801I_SATA_2, 235 0, 236 "Intel 82801I Serial ATA Controller (ICH9)", 237 piixsata_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82801I_SATA_3, 240 0, 241 "Intel 82801I Serial ATA Controller (ICH9)", 242 piixsata_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_63XXESB_SATA, 245 0, 246 "Intel 631xESB/632xESB Serial ATA Controller", 247 piixsata_chip_map, 248 }, 249 { 0, 250 0, 251 NULL, 252 NULL 253 } 254 }; 255 256 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 257 piixide_match, piixide_attach, NULL, NULL); 258 259 static int 260 piixide_match(struct device *parent, struct cfdata *match, 261 void *aux) 262 { 263 struct pci_attach_args *pa = aux; 264 265 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 266 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 267 return (2); 268 } 269 return (0); 270 } 271 272 static void 273 piixide_attach(struct device *parent, struct device *self, void *aux) 274 { 275 struct pci_attach_args *pa = aux; 276 struct pciide_softc *sc = (struct pciide_softc *)self; 277 278 pciide_common_attach(sc, pa, 279 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 280 281 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 282 aprint_error_dev(self, "couldn't establish power handler\n"); 283 } 284 285 static bool 286 piixide_resume(device_t dv) 287 { 288 struct pciide_softc *sc = device_private(dv); 289 290 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 291 sc->sc_pm_reg[0]); 292 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMATIM, 293 sc->sc_pm_reg[1]); 294 295 return true; 296 } 297 298 static bool 299 piixide_suspend(device_t dv) 300 { 301 struct pciide_softc *sc = device_private(dv); 302 303 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 304 PIIX_IDETIM); 305 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 306 PIIX_UDMATIM); 307 308 return true; 309 } 310 311 static void 312 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 313 { 314 struct pciide_channel *cp; 315 int channel; 316 u_int32_t idetim; 317 bus_size_t cmdsize, ctlsize; 318 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 319 320 if (pciide_chipen(sc, pa) == 0) 321 return; 322 323 aprint_verbose("%s: bus-master DMA support present", 324 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 325 pciide_mapreg_dma(sc, pa); 326 aprint_verbose("\n"); 327 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 328 if (sc->sc_dma_ok) { 329 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 330 sc->sc_wdcdev.irqack = pciide_irqack; 331 /* Do all revisions require DMA alignment workaround? */ 332 sc->sc_wdcdev.dma_init = piix_dma_init; 333 switch(sc->sc_pp->ide_product) { 334 case PCI_PRODUCT_INTEL_82371AB_IDE: 335 case PCI_PRODUCT_INTEL_82440MX_IDE: 336 case PCI_PRODUCT_INTEL_82801AA_IDE: 337 case PCI_PRODUCT_INTEL_82801AB_IDE: 338 case PCI_PRODUCT_INTEL_82801BA_IDE: 339 case PCI_PRODUCT_INTEL_82801BAM_IDE: 340 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 341 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 342 case PCI_PRODUCT_INTEL_82801DB_IDE: 343 case PCI_PRODUCT_INTEL_82801DBM_IDE: 344 case PCI_PRODUCT_INTEL_82801EB_IDE: 345 case PCI_PRODUCT_INTEL_6300ESB_IDE: 346 case PCI_PRODUCT_INTEL_82801FB_IDE: 347 case PCI_PRODUCT_INTEL_82801G_IDE: 348 case PCI_PRODUCT_INTEL_82801HBM_IDE: 349 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 350 } 351 } 352 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 353 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 354 switch(sc->sc_pp->ide_product) { 355 case PCI_PRODUCT_INTEL_82801AA_IDE: 356 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 357 break; 358 case PCI_PRODUCT_INTEL_82801BA_IDE: 359 case PCI_PRODUCT_INTEL_82801BAM_IDE: 360 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 361 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 362 case PCI_PRODUCT_INTEL_82801DB_IDE: 363 case PCI_PRODUCT_INTEL_82801DBM_IDE: 364 case PCI_PRODUCT_INTEL_82801EB_IDE: 365 case PCI_PRODUCT_INTEL_6300ESB_IDE: 366 case PCI_PRODUCT_INTEL_82801FB_IDE: 367 case PCI_PRODUCT_INTEL_82801G_IDE: 368 case PCI_PRODUCT_INTEL_82801HBM_IDE: 369 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 370 break; 371 default: 372 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 373 } 374 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 375 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 376 else 377 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 378 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 379 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 380 381 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 382 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 383 DEBUG_PROBE); 384 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 385 ATADEBUG_PRINT((", sidetim=0x%x", 386 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 387 DEBUG_PROBE); 388 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 389 ATADEBUG_PRINT((", udamreg 0x%x", 390 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 391 DEBUG_PROBE); 392 } 393 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 394 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 395 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 396 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 397 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 398 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 400 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 402 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 404 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 405 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 406 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 407 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 408 DEBUG_PROBE); 409 } 410 411 } 412 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 413 414 wdc_allocate_regs(&sc->sc_wdcdev); 415 416 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 417 channel++) { 418 cp = &sc->pciide_channels[channel]; 419 if (pciide_chansetup(sc, channel, interface) == 0) 420 continue; 421 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 422 if ((PIIX_IDETIM_READ(idetim, channel) & 423 PIIX_IDETIM_IDE) == 0) { 424 #if 1 425 aprint_normal("%s: %s channel ignored (disabled)\n", 426 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 427 cp->ata_channel.ch_flags |= ATACH_DISABLED; 428 continue; 429 #else 430 pcireg_t interface; 431 432 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 433 channel); 434 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 435 idetim); 436 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 437 sc->sc_tag, PCI_CLASS_REG)); 438 aprint_normal("channel %d idetim=%08x interface=%02x\n", 439 channel, idetim, interface); 440 #endif 441 } 442 pciide_mapchan(pa, cp, interface, 443 &cmdsize, &ctlsize, pciide_pci_intr); 444 } 445 446 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 447 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 448 DEBUG_PROBE); 449 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 450 ATADEBUG_PRINT((", sidetim=0x%x", 451 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 452 DEBUG_PROBE); 453 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 454 ATADEBUG_PRINT((", udamreg 0x%x", 455 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 456 DEBUG_PROBE); 457 } 458 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 459 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 460 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 461 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 462 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 471 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 472 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 473 DEBUG_PROBE); 474 } 475 } 476 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 477 } 478 479 static void 480 piix_setup_channel(struct ata_channel *chp) 481 { 482 u_int8_t mode[2], drive; 483 u_int32_t oidetim, idetim, idedma_ctl; 484 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 485 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 486 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 487 488 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 489 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 490 idedma_ctl = 0; 491 492 /* set up new idetim: Enable IDE registers decode */ 493 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 494 chp->ch_channel); 495 496 /* setup DMA */ 497 pciide_channel_dma_setup(cp); 498 499 /* 500 * Here we have to mess up with drives mode: PIIX can't have 501 * different timings for master and slave drives. 502 * We need to find the best combination. 503 */ 504 505 /* If both drives supports DMA, take the lower mode */ 506 if ((drvp[0].drive_flags & DRIVE_DMA) && 507 (drvp[1].drive_flags & DRIVE_DMA)) { 508 mode[0] = mode[1] = 509 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 510 drvp[0].DMA_mode = mode[0]; 511 drvp[1].DMA_mode = mode[1]; 512 goto ok; 513 } 514 /* 515 * If only one drive supports DMA, use its mode, and 516 * put the other one in PIO mode 0 if mode not compatible 517 */ 518 if (drvp[0].drive_flags & DRIVE_DMA) { 519 mode[0] = drvp[0].DMA_mode; 520 mode[1] = drvp[1].PIO_mode; 521 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 522 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 523 mode[1] = drvp[1].PIO_mode = 0; 524 goto ok; 525 } 526 if (drvp[1].drive_flags & DRIVE_DMA) { 527 mode[1] = drvp[1].DMA_mode; 528 mode[0] = drvp[0].PIO_mode; 529 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 530 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 531 mode[0] = drvp[0].PIO_mode = 0; 532 goto ok; 533 } 534 /* 535 * If both drives are not DMA, takes the lower mode, unless 536 * one of them is PIO mode < 2 537 */ 538 if (drvp[0].PIO_mode < 2) { 539 mode[0] = drvp[0].PIO_mode = 0; 540 mode[1] = drvp[1].PIO_mode; 541 } else if (drvp[1].PIO_mode < 2) { 542 mode[1] = drvp[1].PIO_mode = 0; 543 mode[0] = drvp[0].PIO_mode; 544 } else { 545 mode[0] = mode[1] = 546 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 547 drvp[0].PIO_mode = mode[0]; 548 drvp[1].PIO_mode = mode[1]; 549 } 550 ok: /* The modes are setup */ 551 for (drive = 0; drive < 2; drive++) { 552 if (drvp[drive].drive_flags & DRIVE_DMA) { 553 idetim |= piix_setup_idetim_timings( 554 mode[drive], 1, chp->ch_channel); 555 goto end; 556 } 557 } 558 /* If we are there, none of the drives are DMA */ 559 if (mode[0] >= 2) 560 idetim |= piix_setup_idetim_timings( 561 mode[0], 0, chp->ch_channel); 562 else 563 idetim |= piix_setup_idetim_timings( 564 mode[1], 0, chp->ch_channel); 565 end: /* 566 * timing mode is now set up in the controller. Enable 567 * it per-drive 568 */ 569 for (drive = 0; drive < 2; drive++) { 570 /* If no drive, skip */ 571 if ((drvp[drive].drive_flags & DRIVE) == 0) 572 continue; 573 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 574 if (drvp[drive].drive_flags & DRIVE_DMA) 575 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 576 } 577 if (idedma_ctl != 0) { 578 /* Add software bits in status register */ 579 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 580 idedma_ctl); 581 } 582 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 583 } 584 585 static void 586 piix3_4_setup_channel(struct ata_channel *chp) 587 { 588 struct ata_drive_datas *drvp; 589 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 590 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 591 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 592 struct wdc_softc *wdc = &sc->sc_wdcdev; 593 int drive, s; 594 int channel = chp->ch_channel; 595 596 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 597 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 598 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 599 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 600 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 601 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 602 PIIX_SIDETIM_RTC_MASK(channel)); 603 idedma_ctl = 0; 604 605 /* set up new idetim: Enable IDE registers decode */ 606 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 607 608 /* setup DMA if needed */ 609 pciide_channel_dma_setup(cp); 610 611 for (drive = 0; drive < 2; drive++) { 612 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 613 PIIX_UDMATIM_SET(0x3, channel, drive)); 614 drvp = &chp->ch_drive[drive]; 615 /* If no drive, skip */ 616 if ((drvp->drive_flags & DRIVE) == 0) 617 continue; 618 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 619 (drvp->drive_flags & DRIVE_UDMA) == 0)) 620 goto pio; 621 622 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 623 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 624 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 625 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 626 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 632 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 633 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 635 ideconf |= PIIX_CONFIG_PINGPONG; 636 } 637 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 638 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 639 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 640 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 641 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 642 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 643 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 644 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 645 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 646 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 647 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 648 /* setup Ultra/100 */ 649 if (drvp->UDMA_mode > 2 && 650 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 651 drvp->UDMA_mode = 2; 652 if (drvp->UDMA_mode > 4) { 653 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 654 } else { 655 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 656 if (drvp->UDMA_mode > 2) { 657 ideconf |= PIIX_CONFIG_UDMA66(channel, 658 drive); 659 } else { 660 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 661 drive); 662 } 663 } 664 } 665 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 666 /* setup Ultra/66 */ 667 if (drvp->UDMA_mode > 2 && 668 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 669 drvp->UDMA_mode = 2; 670 if (drvp->UDMA_mode > 2) 671 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 672 else 673 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 674 } 675 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 676 (drvp->drive_flags & DRIVE_UDMA)) { 677 /* use Ultra/DMA */ 678 s = splbio(); 679 drvp->drive_flags &= ~DRIVE_DMA; 680 splx(s); 681 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 682 udmareg |= PIIX_UDMATIM_SET( 683 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 684 } else { 685 /* use Multiword DMA */ 686 s = splbio(); 687 drvp->drive_flags &= ~DRIVE_UDMA; 688 splx(s); 689 if (drive == 0) { 690 idetim |= piix_setup_idetim_timings( 691 drvp->DMA_mode, 1, channel); 692 } else { 693 sidetim |= piix_setup_sidetim_timings( 694 drvp->DMA_mode, 1, channel); 695 idetim =PIIX_IDETIM_SET(idetim, 696 PIIX_IDETIM_SITRE, channel); 697 } 698 } 699 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 700 701 pio: /* use PIO mode */ 702 idetim |= piix_setup_idetim_drvs(drvp); 703 if (drive == 0) { 704 idetim |= piix_setup_idetim_timings( 705 drvp->PIO_mode, 0, channel); 706 } else { 707 sidetim |= piix_setup_sidetim_timings( 708 drvp->PIO_mode, 0, channel); 709 idetim =PIIX_IDETIM_SET(idetim, 710 PIIX_IDETIM_SITRE, channel); 711 } 712 } 713 if (idedma_ctl != 0) { 714 /* Add software bits in status register */ 715 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 716 idedma_ctl); 717 } 718 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 719 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 720 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 721 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 722 } 723 724 725 /* setup ISP and RTC fields, based on mode */ 726 static u_int32_t 727 piix_setup_idetim_timings(mode, dma, channel) 728 u_int8_t mode; 729 u_int8_t dma; 730 u_int8_t channel; 731 { 732 733 if (dma) 734 return PIIX_IDETIM_SET(0, 735 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 736 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 737 channel); 738 else 739 return PIIX_IDETIM_SET(0, 740 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 741 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 742 channel); 743 } 744 745 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 746 static u_int32_t 747 piix_setup_idetim_drvs(drvp) 748 struct ata_drive_datas *drvp; 749 { 750 u_int32_t ret = 0; 751 struct ata_channel *chp = drvp->chnl_softc; 752 u_int8_t channel = chp->ch_channel; 753 u_int8_t drive = drvp->drive; 754 755 /* 756 * If drive is using UDMA, timings setups are independent 757 * So just check DMA and PIO here. 758 */ 759 if (drvp->drive_flags & DRIVE_DMA) { 760 /* if mode = DMA mode 0, use compatible timings */ 761 if ((drvp->drive_flags & DRIVE_DMA) && 762 drvp->DMA_mode == 0) { 763 drvp->PIO_mode = 0; 764 return ret; 765 } 766 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 767 /* 768 * PIO and DMA timings are the same, use fast timings for PIO 769 * too, else use compat timings. 770 */ 771 if ((piix_isp_pio[drvp->PIO_mode] != 772 piix_isp_dma[drvp->DMA_mode]) || 773 (piix_rtc_pio[drvp->PIO_mode] != 774 piix_rtc_dma[drvp->DMA_mode])) 775 drvp->PIO_mode = 0; 776 /* if PIO mode <= 2, use compat timings for PIO */ 777 if (drvp->PIO_mode <= 2) { 778 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 779 channel); 780 return ret; 781 } 782 } 783 784 /* 785 * Now setup PIO modes. If mode < 2, use compat timings. 786 * Else enable fast timings. Enable IORDY and prefetch/post 787 * if PIO mode >= 3. 788 */ 789 790 if (drvp->PIO_mode < 2) 791 return ret; 792 793 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 794 if (drvp->PIO_mode >= 3) { 795 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 796 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 797 } 798 return ret; 799 } 800 801 /* setup values in SIDETIM registers, based on mode */ 802 static u_int32_t 803 piix_setup_sidetim_timings(mode, dma, channel) 804 u_int8_t mode; 805 u_int8_t dma; 806 u_int8_t channel; 807 { 808 if (dma) 809 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 810 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 811 else 812 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 813 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 814 } 815 816 static void 817 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 818 { 819 struct pciide_channel *cp; 820 bus_size_t cmdsize, ctlsize; 821 pcireg_t interface, cmdsts; 822 int channel; 823 824 if (pciide_chipen(sc, pa) == 0) 825 return; 826 827 aprint_verbose("%s: bus-master DMA support present", 828 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 829 pciide_mapreg_dma(sc, pa); 830 aprint_verbose("\n"); 831 832 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 833 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 834 if (sc->sc_dma_ok) { 835 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 836 sc->sc_wdcdev.irqack = pciide_irqack; 837 /* Do all revisions require DMA alignment workaround? */ 838 sc->sc_wdcdev.dma_init = piix_dma_init; 839 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 840 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 841 } 842 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 843 844 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 845 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 846 847 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 848 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 849 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 850 851 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 852 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 853 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 854 855 interface = PCI_INTERFACE(pa->pa_class); 856 857 wdc_allocate_regs(&sc->sc_wdcdev); 858 859 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 860 channel++) { 861 cp = &sc->pciide_channels[channel]; 862 if (pciide_chansetup(sc, channel, interface) == 0) 863 continue; 864 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 865 pciide_pci_intr); 866 } 867 } 868 869 static int 870 piix_dma_init(void *v, int channel, int drive, void *databuf, 871 size_t datalen, int flags) 872 { 873 874 /* use PIO for unaligned transfer */ 875 if (((uintptr_t)databuf) & 0x1) 876 return EINVAL; 877 878 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 879 } 880
Indexes created Wed Oct 15 16:09:53 GMT 2025