piixide.c revision 1.44.6.2
1 /* $NetBSD: piixide.c,v 1.44.6.2 2008/10/05 20:11:30 mjf Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.44.6.2 2008/10/05 20:11:30 mjf Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static bool piixide_resume(device_t PMF_FN_PROTO); 54 static bool piixide_suspend(device_t PMF_FN_PROTO); 55 static int piixide_match(device_t, cfdata_t, void *); 56 static void piixide_attach(device_t, device_t, void *); 57 58 static const struct pciide_product_desc pciide_intel_products[] = { 59 { PCI_PRODUCT_INTEL_82092AA, 60 0, 61 "Intel 82092AA IDE controller", 62 default_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371FB_IDE, 65 0, 66 "Intel 82371FB IDE controller (PIIX)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371SB_IDE, 70 0, 71 "Intel 82371SB IDE Interface (PIIX3)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82371AB_IDE, 75 0, 76 "Intel 82371AB IDE controller (PIIX4)", 77 piix_chip_map, 78 }, 79 { PCI_PRODUCT_INTEL_82440MX_IDE, 80 0, 81 "Intel 82440MX IDE controller", 82 piix_chip_map 83 }, 84 { PCI_PRODUCT_INTEL_82801AA_IDE, 85 0, 86 "Intel 82801AA IDE Controller (ICH)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801AB_IDE, 90 0, 91 "Intel 82801AB IDE Controller (ICH0)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BA_IDE, 95 0, 96 "Intel 82801BA IDE Controller (ICH2)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801BAM_IDE, 100 0, 101 "Intel 82801BAM IDE Controller (ICH2-M)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 110 0, 111 "Intel 82801CA IDE Controller (ICH3)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DB_IDE, 115 0, 116 "Intel 82801DB IDE Controller (ICH4)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801DBM_IDE, 120 0, 121 "Intel 82801DBM IDE Controller (ICH4-M)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_IDE, 125 0, 126 "Intel 82801EB IDE Controller (ICH5)", 127 piix_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801EB_SATA, 130 0, 131 "Intel 82801EB Serial ATA Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_82801ER_SATA, 135 0, 136 "Intel 82801ER Serial ATA/Raid Controller", 137 piixsata_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_IDE, 140 0, 141 "Intel 6300ESB IDE Controller (ICH5)", 142 piix_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_6300ESB_SATA, 145 0, 146 "Intel 6300ESB Serial ATA Controller", 147 piixsata_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_6300ESB_RAID, 150 0, 151 "Intel 6300ESB Serial ATA/RAID Controller", 152 piixsata_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FB_IDE, 155 0, 156 "Intel 82801FB IDE Controller (ICH6)", 157 piix_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FB_SATA, 160 0, 161 "Intel 82801FB Serial ATA/Raid Controller", 162 piixsata_chip_map, 163 }, 164 { PCI_PRODUCT_INTEL_82801FR_SATA, 165 0, 166 "Intel 82801FR Serial ATA/Raid Controller", 167 piixsata_chip_map, 168 }, 169 { PCI_PRODUCT_INTEL_82801FBM_SATA, 170 0, 171 "Intel 82801FBM Serial ATA Controller (ICH6)", 172 piixsata_chip_map, 173 }, 174 { PCI_PRODUCT_INTEL_82801G_IDE, 175 0, 176 "Intel 82801GB/GR IDE Controller (ICH7)", 177 piix_chip_map, 178 }, 179 { PCI_PRODUCT_INTEL_82801G_SATA, 180 0, 181 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 182 piixsata_chip_map, 183 }, 184 { PCI_PRODUCT_INTEL_82801GBM_SATA, 185 0, 186 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 187 piixsata_chip_map, 188 }, 189 { PCI_PRODUCT_INTEL_82801H_SATA_1, 190 0, 191 "Intel 82801H Serial ATA Controller (ICH8)", 192 piixsata_chip_map, 193 }, 194 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 195 0, 196 "Intel 82801H Serial ATA RAID Controller (ICH8)", 197 piixsata_chip_map, 198 }, 199 { PCI_PRODUCT_INTEL_82801H_SATA_2, 200 0, 201 "Intel 82801H Serial ATA Controller (ICH8)", 202 piixsata_chip_map, 203 }, 204 { PCI_PRODUCT_INTEL_82801HBM_IDE, 205 0, 206 "Intel 82801HBM IDE Controller (ICH8M)", 207 piix_chip_map, 208 }, 209 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 210 0, 211 "Intel 82801HBM Serial ATA Controller (ICH8M)", 212 piixsata_chip_map, 213 }, 214 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 215 0, 216 "Intel 82801HBM Serial ATA Controller (ICH8M)", 217 piixsata_chip_map, 218 }, 219 { PCI_PRODUCT_INTEL_82801HEM_SATA, 220 0, 221 "Intel 82801HEM Serial ATA Controller (ICH8M)", 222 piixsata_chip_map, 223 }, 224 { PCI_PRODUCT_INTEL_63XXESB_IDE, 225 0, 226 "Intel 631xESB/632xESB IDE Controller", 227 piix_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82801I_SATA_1, 230 0, 231 "Intel 82801I Serial ATA Controller (ICH9)", 232 piixsata_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82801I_SATA_2, 235 0, 236 "Intel 82801I Serial ATA Controller (ICH9)", 237 piixsata_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82801I_SATA_3, 240 0, 241 "Intel 82801I Serial ATA Controller (ICH9)", 242 piixsata_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_63XXESB_SATA, 245 0, 246 "Intel 631xESB/632xESB Serial ATA Controller", 247 piixsata_chip_map, 248 }, 249 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x1, 250 0, 251 "Intel ICH10 Serial ATA 2 Controller 2x1", 252 piixsata_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x2, 255 0, 256 "Intel ICH10 Serial ATA 2 Controller 2x2", 257 piixsata_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x1, 260 0, 261 "Intel ICH10 Serial ATA 2 Controller 4x1", 262 piixsata_chip_map, 263 }, 264 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x2, 265 0, 266 "Intel ICH10 Serial ATA 2 Controller 4x2", 267 piixsata_chip_map, 268 }, 269 { 0, 270 0, 271 NULL, 272 NULL 273 } 274 }; 275 276 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), 277 piixide_match, piixide_attach, NULL, NULL); 278 279 static int 280 piixide_match(device_t parent, cfdata_t match, void *aux) 281 { 282 struct pci_attach_args *pa = aux; 283 284 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 285 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 286 return (2); 287 } 288 return (0); 289 } 290 291 static void 292 piixide_attach(device_t parent, device_t self, void *aux) 293 { 294 struct pci_attach_args *pa = aux; 295 struct pciide_softc *sc = device_private(self); 296 297 sc->sc_wdcdev.sc_atac.atac_dev = self; 298 299 pciide_common_attach(sc, pa, 300 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 301 302 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 303 aprint_error_dev(self, "couldn't establish power handler\n"); 304 } 305 306 static bool 307 piixide_resume(device_t dv PMF_FN_ARGS) 308 { 309 struct pciide_softc *sc = device_private(dv); 310 311 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 312 sc->sc_pm_reg[0]); 313 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 314 sc->sc_pm_reg[1]); 315 316 return true; 317 } 318 319 static bool 320 piixide_suspend(device_t dv PMF_FN_ARGS) 321 { 322 struct pciide_softc *sc = device_private(dv); 323 324 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 325 PIIX_IDETIM); 326 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 327 PIIX_UDMAREG); 328 329 return true; 330 } 331 332 static void 333 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 334 { 335 struct pciide_channel *cp; 336 int channel; 337 u_int32_t idetim; 338 bus_size_t cmdsize, ctlsize; 339 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 340 341 if (pciide_chipen(sc, pa) == 0) 342 return; 343 344 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 345 "bus-master DMA support present"); 346 pciide_mapreg_dma(sc, pa); 347 aprint_verbose("\n"); 348 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 349 if (sc->sc_dma_ok) { 350 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 351 sc->sc_wdcdev.irqack = pciide_irqack; 352 /* Do all revisions require DMA alignment workaround? */ 353 sc->sc_wdcdev.dma_init = piix_dma_init; 354 switch(sc->sc_pp->ide_product) { 355 case PCI_PRODUCT_INTEL_82371AB_IDE: 356 case PCI_PRODUCT_INTEL_82440MX_IDE: 357 case PCI_PRODUCT_INTEL_82801AA_IDE: 358 case PCI_PRODUCT_INTEL_82801AB_IDE: 359 case PCI_PRODUCT_INTEL_82801BA_IDE: 360 case PCI_PRODUCT_INTEL_82801BAM_IDE: 361 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 362 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 363 case PCI_PRODUCT_INTEL_82801DB_IDE: 364 case PCI_PRODUCT_INTEL_82801DBM_IDE: 365 case PCI_PRODUCT_INTEL_82801EB_IDE: 366 case PCI_PRODUCT_INTEL_6300ESB_IDE: 367 case PCI_PRODUCT_INTEL_82801FB_IDE: 368 case PCI_PRODUCT_INTEL_82801G_IDE: 369 case PCI_PRODUCT_INTEL_82801HBM_IDE: 370 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 371 } 372 } 373 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 374 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 375 switch(sc->sc_pp->ide_product) { 376 case PCI_PRODUCT_INTEL_82801AA_IDE: 377 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 378 break; 379 case PCI_PRODUCT_INTEL_82801BA_IDE: 380 case PCI_PRODUCT_INTEL_82801BAM_IDE: 381 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 382 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 383 case PCI_PRODUCT_INTEL_82801DB_IDE: 384 case PCI_PRODUCT_INTEL_82801DBM_IDE: 385 case PCI_PRODUCT_INTEL_82801EB_IDE: 386 case PCI_PRODUCT_INTEL_6300ESB_IDE: 387 case PCI_PRODUCT_INTEL_82801FB_IDE: 388 case PCI_PRODUCT_INTEL_82801G_IDE: 389 case PCI_PRODUCT_INTEL_82801HBM_IDE: 390 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 391 break; 392 default: 393 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 394 } 395 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 396 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 397 else 398 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 399 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 400 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 401 402 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 403 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 404 DEBUG_PROBE); 405 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 406 ATADEBUG_PRINT((", sidetim=0x%x", 407 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 408 DEBUG_PROBE); 409 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 410 ATADEBUG_PRINT((", udamreg 0x%x", 411 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 412 DEBUG_PROBE); 413 } 414 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 415 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 416 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 417 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 418 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 419 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 420 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 421 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 422 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 423 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 424 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 425 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 426 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 427 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 428 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 429 DEBUG_PROBE); 430 } 431 432 } 433 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 434 435 wdc_allocate_regs(&sc->sc_wdcdev); 436 437 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 438 channel++) { 439 cp = &sc->pciide_channels[channel]; 440 if (pciide_chansetup(sc, channel, interface) == 0) 441 continue; 442 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 443 if ((PIIX_IDETIM_READ(idetim, channel) & 444 PIIX_IDETIM_IDE) == 0) { 445 #if 1 446 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 447 "%s channel ignored (disabled)\n", cp->name); 448 cp->ata_channel.ch_flags |= ATACH_DISABLED; 449 continue; 450 #else 451 pcireg_t interface; 452 453 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 454 channel); 455 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 456 idetim); 457 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 458 sc->sc_tag, PCI_CLASS_REG)); 459 aprint_normal("channel %d idetim=%08x interface=%02x\n", 460 channel, idetim, interface); 461 #endif 462 } 463 pciide_mapchan(pa, cp, interface, 464 &cmdsize, &ctlsize, pciide_pci_intr); 465 } 466 467 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 468 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 469 DEBUG_PROBE); 470 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 471 ATADEBUG_PRINT((", sidetim=0x%x", 472 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 473 DEBUG_PROBE); 474 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 475 ATADEBUG_PRINT((", udamreg 0x%x", 476 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 477 DEBUG_PROBE); 478 } 479 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 480 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 481 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 482 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 483 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 484 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 485 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 486 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 487 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 488 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 489 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 490 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 491 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 492 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 493 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 494 DEBUG_PROBE); 495 } 496 } 497 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 498 } 499 500 static void 501 piix_setup_channel(struct ata_channel *chp) 502 { 503 u_int8_t mode[2], drive; 504 u_int32_t oidetim, idetim, idedma_ctl; 505 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 506 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 507 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 508 509 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 510 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 511 idedma_ctl = 0; 512 513 /* set up new idetim: Enable IDE registers decode */ 514 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 515 chp->ch_channel); 516 517 /* setup DMA */ 518 pciide_channel_dma_setup(cp); 519 520 /* 521 * Here we have to mess up with drives mode: PIIX can't have 522 * different timings for master and slave drives. 523 * We need to find the best combination. 524 */ 525 526 /* If both drives supports DMA, take the lower mode */ 527 if ((drvp[0].drive_flags & DRIVE_DMA) && 528 (drvp[1].drive_flags & DRIVE_DMA)) { 529 mode[0] = mode[1] = 530 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 531 drvp[0].DMA_mode = mode[0]; 532 drvp[1].DMA_mode = mode[1]; 533 goto ok; 534 } 535 /* 536 * If only one drive supports DMA, use its mode, and 537 * put the other one in PIO mode 0 if mode not compatible 538 */ 539 if (drvp[0].drive_flags & DRIVE_DMA) { 540 mode[0] = drvp[0].DMA_mode; 541 mode[1] = drvp[1].PIO_mode; 542 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 543 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 544 mode[1] = drvp[1].PIO_mode = 0; 545 goto ok; 546 } 547 if (drvp[1].drive_flags & DRIVE_DMA) { 548 mode[1] = drvp[1].DMA_mode; 549 mode[0] = drvp[0].PIO_mode; 550 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 551 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 552 mode[0] = drvp[0].PIO_mode = 0; 553 goto ok; 554 } 555 /* 556 * If both drives are not DMA, takes the lower mode, unless 557 * one of them is PIO mode < 2 558 */ 559 if (drvp[0].PIO_mode < 2) { 560 mode[0] = drvp[0].PIO_mode = 0; 561 mode[1] = drvp[1].PIO_mode; 562 } else if (drvp[1].PIO_mode < 2) { 563 mode[1] = drvp[1].PIO_mode = 0; 564 mode[0] = drvp[0].PIO_mode; 565 } else { 566 mode[0] = mode[1] = 567 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 568 drvp[0].PIO_mode = mode[0]; 569 drvp[1].PIO_mode = mode[1]; 570 } 571 ok: /* The modes are setup */ 572 for (drive = 0; drive < 2; drive++) { 573 if (drvp[drive].drive_flags & DRIVE_DMA) { 574 idetim |= piix_setup_idetim_timings( 575 mode[drive], 1, chp->ch_channel); 576 goto end; 577 } 578 } 579 /* If we are there, none of the drives are DMA */ 580 if (mode[0] >= 2) 581 idetim |= piix_setup_idetim_timings( 582 mode[0], 0, chp->ch_channel); 583 else 584 idetim |= piix_setup_idetim_timings( 585 mode[1], 0, chp->ch_channel); 586 end: /* 587 * timing mode is now set up in the controller. Enable 588 * it per-drive 589 */ 590 for (drive = 0; drive < 2; drive++) { 591 /* If no drive, skip */ 592 if ((drvp[drive].drive_flags & DRIVE) == 0) 593 continue; 594 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 595 if (drvp[drive].drive_flags & DRIVE_DMA) 596 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 597 } 598 if (idedma_ctl != 0) { 599 /* Add software bits in status register */ 600 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 601 idedma_ctl); 602 } 603 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 604 } 605 606 static void 607 piix3_4_setup_channel(struct ata_channel *chp) 608 { 609 struct ata_drive_datas *drvp; 610 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 611 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 612 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 613 struct wdc_softc *wdc = &sc->sc_wdcdev; 614 int drive, s; 615 int channel = chp->ch_channel; 616 617 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 618 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 619 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 620 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 621 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 622 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 623 PIIX_SIDETIM_RTC_MASK(channel)); 624 idedma_ctl = 0; 625 626 /* set up new idetim: Enable IDE registers decode */ 627 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 628 629 /* setup DMA if needed */ 630 pciide_channel_dma_setup(cp); 631 632 for (drive = 0; drive < 2; drive++) { 633 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 634 PIIX_UDMATIM_SET(0x3, channel, drive)); 635 drvp = &chp->ch_drive[drive]; 636 /* If no drive, skip */ 637 if ((drvp->drive_flags & DRIVE) == 0) 638 continue; 639 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 640 (drvp->drive_flags & DRIVE_UDMA) == 0)) 641 goto pio; 642 643 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 644 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 645 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 646 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 647 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 648 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 649 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 650 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 651 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 652 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 653 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 654 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 655 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 656 ideconf |= PIIX_CONFIG_PINGPONG; 657 } 658 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 659 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 660 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 661 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 662 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 663 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 664 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 665 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 666 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 667 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 668 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 669 /* setup Ultra/100 */ 670 if (drvp->UDMA_mode > 2 && 671 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 672 drvp->UDMA_mode = 2; 673 if (drvp->UDMA_mode > 4) { 674 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 675 } else { 676 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 677 if (drvp->UDMA_mode > 2) { 678 ideconf |= PIIX_CONFIG_UDMA66(channel, 679 drive); 680 } else { 681 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 682 drive); 683 } 684 } 685 } 686 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 687 /* setup Ultra/66 */ 688 if (drvp->UDMA_mode > 2 && 689 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 690 drvp->UDMA_mode = 2; 691 if (drvp->UDMA_mode > 2) 692 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 693 else 694 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 695 } 696 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 697 (drvp->drive_flags & DRIVE_UDMA)) { 698 /* use Ultra/DMA */ 699 s = splbio(); 700 drvp->drive_flags &= ~DRIVE_DMA; 701 splx(s); 702 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 703 udmareg |= PIIX_UDMATIM_SET( 704 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 705 } else { 706 /* use Multiword DMA */ 707 s = splbio(); 708 drvp->drive_flags &= ~DRIVE_UDMA; 709 splx(s); 710 if (drive == 0) { 711 idetim |= piix_setup_idetim_timings( 712 drvp->DMA_mode, 1, channel); 713 } else { 714 sidetim |= piix_setup_sidetim_timings( 715 drvp->DMA_mode, 1, channel); 716 idetim =PIIX_IDETIM_SET(idetim, 717 PIIX_IDETIM_SITRE, channel); 718 } 719 } 720 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 721 722 pio: /* use PIO mode */ 723 idetim |= piix_setup_idetim_drvs(drvp); 724 if (drive == 0) { 725 idetim |= piix_setup_idetim_timings( 726 drvp->PIO_mode, 0, channel); 727 } else { 728 sidetim |= piix_setup_sidetim_timings( 729 drvp->PIO_mode, 0, channel); 730 idetim =PIIX_IDETIM_SET(idetim, 731 PIIX_IDETIM_SITRE, channel); 732 } 733 } 734 if (idedma_ctl != 0) { 735 /* Add software bits in status register */ 736 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 737 idedma_ctl); 738 } 739 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 740 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 741 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 742 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 743 } 744 745 746 /* setup ISP and RTC fields, based on mode */ 747 static u_int32_t 748 piix_setup_idetim_timings(mode, dma, channel) 749 u_int8_t mode; 750 u_int8_t dma; 751 u_int8_t channel; 752 { 753 754 if (dma) 755 return PIIX_IDETIM_SET(0, 756 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 757 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 758 channel); 759 else 760 return PIIX_IDETIM_SET(0, 761 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 762 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 763 channel); 764 } 765 766 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 767 static u_int32_t 768 piix_setup_idetim_drvs(drvp) 769 struct ata_drive_datas *drvp; 770 { 771 u_int32_t ret = 0; 772 struct ata_channel *chp = drvp->chnl_softc; 773 u_int8_t channel = chp->ch_channel; 774 u_int8_t drive = drvp->drive; 775 776 /* 777 * If drive is using UDMA, timings setups are independent 778 * So just check DMA and PIO here. 779 */ 780 if (drvp->drive_flags & DRIVE_DMA) { 781 /* if mode = DMA mode 0, use compatible timings */ 782 if ((drvp->drive_flags & DRIVE_DMA) && 783 drvp->DMA_mode == 0) { 784 drvp->PIO_mode = 0; 785 return ret; 786 } 787 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 788 /* 789 * PIO and DMA timings are the same, use fast timings for PIO 790 * too, else use compat timings. 791 */ 792 if ((piix_isp_pio[drvp->PIO_mode] != 793 piix_isp_dma[drvp->DMA_mode]) || 794 (piix_rtc_pio[drvp->PIO_mode] != 795 piix_rtc_dma[drvp->DMA_mode])) 796 drvp->PIO_mode = 0; 797 /* if PIO mode <= 2, use compat timings for PIO */ 798 if (drvp->PIO_mode <= 2) { 799 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 800 channel); 801 return ret; 802 } 803 } 804 805 /* 806 * Now setup PIO modes. If mode < 2, use compat timings. 807 * Else enable fast timings. Enable IORDY and prefetch/post 808 * if PIO mode >= 3. 809 */ 810 811 if (drvp->PIO_mode < 2) 812 return ret; 813 814 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 815 if (drvp->PIO_mode >= 3) { 816 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 817 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 818 } 819 return ret; 820 } 821 822 /* setup values in SIDETIM registers, based on mode */ 823 static u_int32_t 824 piix_setup_sidetim_timings(mode, dma, channel) 825 u_int8_t mode; 826 u_int8_t dma; 827 u_int8_t channel; 828 { 829 if (dma) 830 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 831 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 832 else 833 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 834 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 835 } 836 837 static void 838 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 839 { 840 struct pciide_channel *cp; 841 bus_size_t cmdsize, ctlsize; 842 pcireg_t interface, cmdsts; 843 int channel; 844 845 if (pciide_chipen(sc, pa) == 0) 846 return; 847 848 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 849 "bus-master DMA support present"); 850 pciide_mapreg_dma(sc, pa); 851 aprint_verbose("\n"); 852 853 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 854 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 855 if (sc->sc_dma_ok) { 856 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 857 sc->sc_wdcdev.irqack = pciide_irqack; 858 /* Do all revisions require DMA alignment workaround? */ 859 sc->sc_wdcdev.dma_init = piix_dma_init; 860 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 861 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 862 } 863 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 864 865 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 866 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 867 868 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 869 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 870 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 871 872 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 873 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 874 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 875 876 interface = PCI_INTERFACE(pa->pa_class); 877 878 wdc_allocate_regs(&sc->sc_wdcdev); 879 880 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 881 channel++) { 882 cp = &sc->pciide_channels[channel]; 883 if (pciide_chansetup(sc, channel, interface) == 0) 884 continue; 885 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 886 pciide_pci_intr); 887 } 888 } 889 890 static int 891 piix_dma_init(void *v, int channel, int drive, void *databuf, 892 size_t datalen, int flags) 893 { 894 895 /* use PIO for unaligned transfer */ 896 if (((uintptr_t)databuf) & 0x1) 897 return EINVAL; 898 899 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 900 } 901
Indexes created Sun Oct 19 02:09:48 GMT 2025