piixide.c revision 1.46
1 /* $NetBSD: piixide.c,v 1.46 2008/03/18 20:46:37 cube Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.46 2008/03/18 20:46:37 cube Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static bool piixide_resume(device_t PMF_FN_PROTO); 54 static bool piixide_suspend(device_t PMF_FN_PROTO); 55 static int piixide_match(device_t, cfdata_t, void *); 56 static void piixide_attach(device_t, device_t, void *); 57 58 static const struct pciide_product_desc pciide_intel_products[] = { 59 { PCI_PRODUCT_INTEL_82092AA, 60 0, 61 "Intel 82092AA IDE controller", 62 default_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371FB_IDE, 65 0, 66 "Intel 82371FB IDE controller (PIIX)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371SB_IDE, 70 0, 71 "Intel 82371SB IDE Interface (PIIX3)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82371AB_IDE, 75 0, 76 "Intel 82371AB IDE controller (PIIX4)", 77 piix_chip_map, 78 }, 79 { PCI_PRODUCT_INTEL_82440MX_IDE, 80 0, 81 "Intel 82440MX IDE controller", 82 piix_chip_map 83 }, 84 { PCI_PRODUCT_INTEL_82801AA_IDE, 85 0, 86 "Intel 82801AA IDE Controller (ICH)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801AB_IDE, 90 0, 91 "Intel 82801AB IDE Controller (ICH0)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BA_IDE, 95 0, 96 "Intel 82801BA IDE Controller (ICH2)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801BAM_IDE, 100 0, 101 "Intel 82801BAM IDE Controller (ICH2-M)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 110 0, 111 "Intel 82801CA IDE Controller (ICH3)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DB_IDE, 115 0, 116 "Intel 82801DB IDE Controller (ICH4)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801DBM_IDE, 120 0, 121 "Intel 82801DBM IDE Controller (ICH4-M)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_IDE, 125 0, 126 "Intel 82801EB IDE Controller (ICH5)", 127 piix_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801EB_SATA, 130 0, 131 "Intel 82801EB Serial ATA Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_82801ER_SATA, 135 0, 136 "Intel 82801ER Serial ATA/Raid Controller", 137 piixsata_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_IDE, 140 0, 141 "Intel 6300ESB IDE Controller (ICH5)", 142 piix_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_6300ESB_SATA, 145 0, 146 "Intel 6300ESB Serial ATA Controller", 147 piixsata_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_6300ESB_RAID, 150 0, 151 "Intel 6300ESB Serial ATA/RAID Controller", 152 piixsata_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FB_IDE, 155 0, 156 "Intel 82801FB IDE Controller (ICH6)", 157 piix_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FB_SATA, 160 0, 161 "Intel 82801FB Serial ATA/Raid Controller", 162 piixsata_chip_map, 163 }, 164 { PCI_PRODUCT_INTEL_82801FR_SATA, 165 0, 166 "Intel 82801FR Serial ATA/Raid Controller", 167 piixsata_chip_map, 168 }, 169 { PCI_PRODUCT_INTEL_82801FBM_SATA, 170 0, 171 "Intel 82801FBM Serial ATA Controller (ICH6)", 172 piixsata_chip_map, 173 }, 174 { PCI_PRODUCT_INTEL_82801G_IDE, 175 0, 176 "Intel 82801GB/GR IDE Controller (ICH7)", 177 piix_chip_map, 178 }, 179 { PCI_PRODUCT_INTEL_82801G_SATA, 180 0, 181 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 182 piixsata_chip_map, 183 }, 184 { PCI_PRODUCT_INTEL_82801GBM_SATA, 185 0, 186 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 187 piixsata_chip_map, 188 }, 189 { PCI_PRODUCT_INTEL_82801H_SATA_1, 190 0, 191 "Intel 82801H Serial ATA Controller (ICH8)", 192 piixsata_chip_map, 193 }, 194 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 195 0, 196 "Intel 82801H Serial ATA RAID Controller (ICH8)", 197 piixsata_chip_map, 198 }, 199 { PCI_PRODUCT_INTEL_82801H_SATA_2, 200 0, 201 "Intel 82801H Serial ATA Controller (ICH8)", 202 piixsata_chip_map, 203 }, 204 { PCI_PRODUCT_INTEL_82801HBM_IDE, 205 0, 206 "Intel 82801HBM IDE Controller (ICH8M)", 207 piix_chip_map, 208 }, 209 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 210 0, 211 "Intel 82801HBM Serial ATA Controller (ICH8M)", 212 piixsata_chip_map, 213 }, 214 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 215 0, 216 "Intel 82801HBM Serial ATA Controller (ICH8M)", 217 piixsata_chip_map, 218 }, 219 { PCI_PRODUCT_INTEL_82801HEM_SATA, 220 0, 221 "Intel 82801HEM Serial ATA Controller (ICH8M)", 222 piixsata_chip_map, 223 }, 224 { PCI_PRODUCT_INTEL_63XXESB_IDE, 225 0, 226 "Intel 631xESB/632xESB IDE Controller", 227 piix_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82801I_SATA_1, 230 0, 231 "Intel 82801I Serial ATA Controller (ICH9)", 232 piixsata_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82801I_SATA_2, 235 0, 236 "Intel 82801I Serial ATA Controller (ICH9)", 237 piixsata_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82801I_SATA_3, 240 0, 241 "Intel 82801I Serial ATA Controller (ICH9)", 242 piixsata_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_63XXESB_SATA, 245 0, 246 "Intel 631xESB/632xESB Serial ATA Controller", 247 piixsata_chip_map, 248 }, 249 { 0, 250 0, 251 NULL, 252 NULL 253 } 254 }; 255 256 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), 257 piixide_match, piixide_attach, NULL, NULL); 258 259 static int 260 piixide_match(device_t parent, cfdata_t match, void *aux) 261 { 262 struct pci_attach_args *pa = aux; 263 264 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 265 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 266 return (2); 267 } 268 return (0); 269 } 270 271 static void 272 piixide_attach(device_t parent, device_t self, void *aux) 273 { 274 struct pci_attach_args *pa = aux; 275 struct pciide_softc *sc = device_private(self); 276 277 sc->sc_wdcdev.sc_atac.atac_dev = self; 278 279 pciide_common_attach(sc, pa, 280 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 281 282 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 283 aprint_error_dev(self, "couldn't establish power handler\n"); 284 } 285 286 static bool 287 piixide_resume(device_t dv PMF_FN_ARGS) 288 { 289 struct pciide_softc *sc = device_private(dv); 290 291 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 292 sc->sc_pm_reg[0]); 293 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 294 sc->sc_pm_reg[1]); 295 296 return true; 297 } 298 299 static bool 300 piixide_suspend(device_t dv PMF_FN_ARGS) 301 { 302 struct pciide_softc *sc = device_private(dv); 303 304 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 305 PIIX_IDETIM); 306 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 307 PIIX_UDMAREG); 308 309 return true; 310 } 311 312 static void 313 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 314 { 315 struct pciide_channel *cp; 316 int channel; 317 u_int32_t idetim; 318 bus_size_t cmdsize, ctlsize; 319 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 320 321 if (pciide_chipen(sc, pa) == 0) 322 return; 323 324 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 325 "bus-master DMA support present"); 326 pciide_mapreg_dma(sc, pa); 327 aprint_verbose("\n"); 328 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 329 if (sc->sc_dma_ok) { 330 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 331 sc->sc_wdcdev.irqack = pciide_irqack; 332 /* Do all revisions require DMA alignment workaround? */ 333 sc->sc_wdcdev.dma_init = piix_dma_init; 334 switch(sc->sc_pp->ide_product) { 335 case PCI_PRODUCT_INTEL_82371AB_IDE: 336 case PCI_PRODUCT_INTEL_82440MX_IDE: 337 case PCI_PRODUCT_INTEL_82801AA_IDE: 338 case PCI_PRODUCT_INTEL_82801AB_IDE: 339 case PCI_PRODUCT_INTEL_82801BA_IDE: 340 case PCI_PRODUCT_INTEL_82801BAM_IDE: 341 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 342 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 343 case PCI_PRODUCT_INTEL_82801DB_IDE: 344 case PCI_PRODUCT_INTEL_82801DBM_IDE: 345 case PCI_PRODUCT_INTEL_82801EB_IDE: 346 case PCI_PRODUCT_INTEL_6300ESB_IDE: 347 case PCI_PRODUCT_INTEL_82801FB_IDE: 348 case PCI_PRODUCT_INTEL_82801G_IDE: 349 case PCI_PRODUCT_INTEL_82801HBM_IDE: 350 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 351 } 352 } 353 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 354 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 355 switch(sc->sc_pp->ide_product) { 356 case PCI_PRODUCT_INTEL_82801AA_IDE: 357 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 358 break; 359 case PCI_PRODUCT_INTEL_82801BA_IDE: 360 case PCI_PRODUCT_INTEL_82801BAM_IDE: 361 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 362 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 363 case PCI_PRODUCT_INTEL_82801DB_IDE: 364 case PCI_PRODUCT_INTEL_82801DBM_IDE: 365 case PCI_PRODUCT_INTEL_82801EB_IDE: 366 case PCI_PRODUCT_INTEL_6300ESB_IDE: 367 case PCI_PRODUCT_INTEL_82801FB_IDE: 368 case PCI_PRODUCT_INTEL_82801G_IDE: 369 case PCI_PRODUCT_INTEL_82801HBM_IDE: 370 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 371 break; 372 default: 373 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 374 } 375 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 376 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 377 else 378 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 379 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 380 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 381 382 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 383 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 384 DEBUG_PROBE); 385 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 386 ATADEBUG_PRINT((", sidetim=0x%x", 387 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 388 DEBUG_PROBE); 389 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 390 ATADEBUG_PRINT((", udamreg 0x%x", 391 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 392 DEBUG_PROBE); 393 } 394 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 395 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 396 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 397 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 398 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 400 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 402 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 404 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 405 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 406 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 407 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 408 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 409 DEBUG_PROBE); 410 } 411 412 } 413 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 414 415 wdc_allocate_regs(&sc->sc_wdcdev); 416 417 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 418 channel++) { 419 cp = &sc->pciide_channels[channel]; 420 if (pciide_chansetup(sc, channel, interface) == 0) 421 continue; 422 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 423 if ((PIIX_IDETIM_READ(idetim, channel) & 424 PIIX_IDETIM_IDE) == 0) { 425 #if 1 426 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 427 "%s channel ignored (disabled)\n", cp->name); 428 cp->ata_channel.ch_flags |= ATACH_DISABLED; 429 continue; 430 #else 431 pcireg_t interface; 432 433 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 434 channel); 435 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 436 idetim); 437 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 438 sc->sc_tag, PCI_CLASS_REG)); 439 aprint_normal("channel %d idetim=%08x interface=%02x\n", 440 channel, idetim, interface); 441 #endif 442 } 443 pciide_mapchan(pa, cp, interface, 444 &cmdsize, &ctlsize, pciide_pci_intr); 445 } 446 447 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 448 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 449 DEBUG_PROBE); 450 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 451 ATADEBUG_PRINT((", sidetim=0x%x", 452 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 453 DEBUG_PROBE); 454 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 455 ATADEBUG_PRINT((", udamreg 0x%x", 456 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 457 DEBUG_PROBE); 458 } 459 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 460 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 461 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 462 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 472 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 473 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 474 DEBUG_PROBE); 475 } 476 } 477 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 478 } 479 480 static void 481 piix_setup_channel(struct ata_channel *chp) 482 { 483 u_int8_t mode[2], drive; 484 u_int32_t oidetim, idetim, idedma_ctl; 485 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 486 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 487 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 488 489 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 490 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 491 idedma_ctl = 0; 492 493 /* set up new idetim: Enable IDE registers decode */ 494 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 495 chp->ch_channel); 496 497 /* setup DMA */ 498 pciide_channel_dma_setup(cp); 499 500 /* 501 * Here we have to mess up with drives mode: PIIX can't have 502 * different timings for master and slave drives. 503 * We need to find the best combination. 504 */ 505 506 /* If both drives supports DMA, take the lower mode */ 507 if ((drvp[0].drive_flags & DRIVE_DMA) && 508 (drvp[1].drive_flags & DRIVE_DMA)) { 509 mode[0] = mode[1] = 510 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 511 drvp[0].DMA_mode = mode[0]; 512 drvp[1].DMA_mode = mode[1]; 513 goto ok; 514 } 515 /* 516 * If only one drive supports DMA, use its mode, and 517 * put the other one in PIO mode 0 if mode not compatible 518 */ 519 if (drvp[0].drive_flags & DRIVE_DMA) { 520 mode[0] = drvp[0].DMA_mode; 521 mode[1] = drvp[1].PIO_mode; 522 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 523 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 524 mode[1] = drvp[1].PIO_mode = 0; 525 goto ok; 526 } 527 if (drvp[1].drive_flags & DRIVE_DMA) { 528 mode[1] = drvp[1].DMA_mode; 529 mode[0] = drvp[0].PIO_mode; 530 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 531 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 532 mode[0] = drvp[0].PIO_mode = 0; 533 goto ok; 534 } 535 /* 536 * If both drives are not DMA, takes the lower mode, unless 537 * one of them is PIO mode < 2 538 */ 539 if (drvp[0].PIO_mode < 2) { 540 mode[0] = drvp[0].PIO_mode = 0; 541 mode[1] = drvp[1].PIO_mode; 542 } else if (drvp[1].PIO_mode < 2) { 543 mode[1] = drvp[1].PIO_mode = 0; 544 mode[0] = drvp[0].PIO_mode; 545 } else { 546 mode[0] = mode[1] = 547 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 548 drvp[0].PIO_mode = mode[0]; 549 drvp[1].PIO_mode = mode[1]; 550 } 551 ok: /* The modes are setup */ 552 for (drive = 0; drive < 2; drive++) { 553 if (drvp[drive].drive_flags & DRIVE_DMA) { 554 idetim |= piix_setup_idetim_timings( 555 mode[drive], 1, chp->ch_channel); 556 goto end; 557 } 558 } 559 /* If we are there, none of the drives are DMA */ 560 if (mode[0] >= 2) 561 idetim |= piix_setup_idetim_timings( 562 mode[0], 0, chp->ch_channel); 563 else 564 idetim |= piix_setup_idetim_timings( 565 mode[1], 0, chp->ch_channel); 566 end: /* 567 * timing mode is now set up in the controller. Enable 568 * it per-drive 569 */ 570 for (drive = 0; drive < 2; drive++) { 571 /* If no drive, skip */ 572 if ((drvp[drive].drive_flags & DRIVE) == 0) 573 continue; 574 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 575 if (drvp[drive].drive_flags & DRIVE_DMA) 576 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 577 } 578 if (idedma_ctl != 0) { 579 /* Add software bits in status register */ 580 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 581 idedma_ctl); 582 } 583 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 584 } 585 586 static void 587 piix3_4_setup_channel(struct ata_channel *chp) 588 { 589 struct ata_drive_datas *drvp; 590 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 591 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 592 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 593 struct wdc_softc *wdc = &sc->sc_wdcdev; 594 int drive, s; 595 int channel = chp->ch_channel; 596 597 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 598 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 599 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 600 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 601 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 602 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 603 PIIX_SIDETIM_RTC_MASK(channel)); 604 idedma_ctl = 0; 605 606 /* set up new idetim: Enable IDE registers decode */ 607 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 608 609 /* setup DMA if needed */ 610 pciide_channel_dma_setup(cp); 611 612 for (drive = 0; drive < 2; drive++) { 613 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 614 PIIX_UDMATIM_SET(0x3, channel, drive)); 615 drvp = &chp->ch_drive[drive]; 616 /* If no drive, skip */ 617 if ((drvp->drive_flags & DRIVE) == 0) 618 continue; 619 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 620 (drvp->drive_flags & DRIVE_UDMA) == 0)) 621 goto pio; 622 623 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 624 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 625 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 626 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 627 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 628 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 629 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 630 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 632 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 633 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 636 ideconf |= PIIX_CONFIG_PINGPONG; 637 } 638 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 639 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 640 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 641 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 642 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 643 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 644 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 645 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 646 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 647 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 648 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 649 /* setup Ultra/100 */ 650 if (drvp->UDMA_mode > 2 && 651 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 652 drvp->UDMA_mode = 2; 653 if (drvp->UDMA_mode > 4) { 654 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 655 } else { 656 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 657 if (drvp->UDMA_mode > 2) { 658 ideconf |= PIIX_CONFIG_UDMA66(channel, 659 drive); 660 } else { 661 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 662 drive); 663 } 664 } 665 } 666 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 667 /* setup Ultra/66 */ 668 if (drvp->UDMA_mode > 2 && 669 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 670 drvp->UDMA_mode = 2; 671 if (drvp->UDMA_mode > 2) 672 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 673 else 674 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 675 } 676 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 677 (drvp->drive_flags & DRIVE_UDMA)) { 678 /* use Ultra/DMA */ 679 s = splbio(); 680 drvp->drive_flags &= ~DRIVE_DMA; 681 splx(s); 682 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 683 udmareg |= PIIX_UDMATIM_SET( 684 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 685 } else { 686 /* use Multiword DMA */ 687 s = splbio(); 688 drvp->drive_flags &= ~DRIVE_UDMA; 689 splx(s); 690 if (drive == 0) { 691 idetim |= piix_setup_idetim_timings( 692 drvp->DMA_mode, 1, channel); 693 } else { 694 sidetim |= piix_setup_sidetim_timings( 695 drvp->DMA_mode, 1, channel); 696 idetim =PIIX_IDETIM_SET(idetim, 697 PIIX_IDETIM_SITRE, channel); 698 } 699 } 700 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 701 702 pio: /* use PIO mode */ 703 idetim |= piix_setup_idetim_drvs(drvp); 704 if (drive == 0) { 705 idetim |= piix_setup_idetim_timings( 706 drvp->PIO_mode, 0, channel); 707 } else { 708 sidetim |= piix_setup_sidetim_timings( 709 drvp->PIO_mode, 0, channel); 710 idetim =PIIX_IDETIM_SET(idetim, 711 PIIX_IDETIM_SITRE, channel); 712 } 713 } 714 if (idedma_ctl != 0) { 715 /* Add software bits in status register */ 716 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 717 idedma_ctl); 718 } 719 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 720 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 721 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 722 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 723 } 724 725 726 /* setup ISP and RTC fields, based on mode */ 727 static u_int32_t 728 piix_setup_idetim_timings(mode, dma, channel) 729 u_int8_t mode; 730 u_int8_t dma; 731 u_int8_t channel; 732 { 733 734 if (dma) 735 return PIIX_IDETIM_SET(0, 736 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 737 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 738 channel); 739 else 740 return PIIX_IDETIM_SET(0, 741 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 742 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 743 channel); 744 } 745 746 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 747 static u_int32_t 748 piix_setup_idetim_drvs(drvp) 749 struct ata_drive_datas *drvp; 750 { 751 u_int32_t ret = 0; 752 struct ata_channel *chp = drvp->chnl_softc; 753 u_int8_t channel = chp->ch_channel; 754 u_int8_t drive = drvp->drive; 755 756 /* 757 * If drive is using UDMA, timings setups are independent 758 * So just check DMA and PIO here. 759 */ 760 if (drvp->drive_flags & DRIVE_DMA) { 761 /* if mode = DMA mode 0, use compatible timings */ 762 if ((drvp->drive_flags & DRIVE_DMA) && 763 drvp->DMA_mode == 0) { 764 drvp->PIO_mode = 0; 765 return ret; 766 } 767 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 768 /* 769 * PIO and DMA timings are the same, use fast timings for PIO 770 * too, else use compat timings. 771 */ 772 if ((piix_isp_pio[drvp->PIO_mode] != 773 piix_isp_dma[drvp->DMA_mode]) || 774 (piix_rtc_pio[drvp->PIO_mode] != 775 piix_rtc_dma[drvp->DMA_mode])) 776 drvp->PIO_mode = 0; 777 /* if PIO mode <= 2, use compat timings for PIO */ 778 if (drvp->PIO_mode <= 2) { 779 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 780 channel); 781 return ret; 782 } 783 } 784 785 /* 786 * Now setup PIO modes. If mode < 2, use compat timings. 787 * Else enable fast timings. Enable IORDY and prefetch/post 788 * if PIO mode >= 3. 789 */ 790 791 if (drvp->PIO_mode < 2) 792 return ret; 793 794 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 795 if (drvp->PIO_mode >= 3) { 796 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 797 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 798 } 799 return ret; 800 } 801 802 /* setup values in SIDETIM registers, based on mode */ 803 static u_int32_t 804 piix_setup_sidetim_timings(mode, dma, channel) 805 u_int8_t mode; 806 u_int8_t dma; 807 u_int8_t channel; 808 { 809 if (dma) 810 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 811 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 812 else 813 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 814 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 815 } 816 817 static void 818 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 819 { 820 struct pciide_channel *cp; 821 bus_size_t cmdsize, ctlsize; 822 pcireg_t interface, cmdsts; 823 int channel; 824 825 if (pciide_chipen(sc, pa) == 0) 826 return; 827 828 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 829 "bus-master DMA support present"); 830 pciide_mapreg_dma(sc, pa); 831 aprint_verbose("\n"); 832 833 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 834 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 835 if (sc->sc_dma_ok) { 836 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 837 sc->sc_wdcdev.irqack = pciide_irqack; 838 /* Do all revisions require DMA alignment workaround? */ 839 sc->sc_wdcdev.dma_init = piix_dma_init; 840 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 841 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 842 } 843 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 844 845 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 846 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 847 848 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 849 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 850 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 851 852 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 853 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 854 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 855 856 interface = PCI_INTERFACE(pa->pa_class); 857 858 wdc_allocate_regs(&sc->sc_wdcdev); 859 860 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 861 channel++) { 862 cp = &sc->pciide_channels[channel]; 863 if (pciide_chansetup(sc, channel, interface) == 0) 864 continue; 865 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 866 pciide_pci_intr); 867 } 868 } 869 870 static int 871 piix_dma_init(void *v, int channel, int drive, void *databuf, 872 size_t datalen, int flags) 873 { 874 875 /* use PIO for unaligned transfer */ 876 if (((uintptr_t)databuf) & 0x1) 877 return EINVAL; 878 879 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 880 } 881
Indexes created Fri Sep 26 20:09:58 GMT 2025