piixide.c revision 1.47.2.1
1 /* $NetBSD: piixide.c,v 1.47.2.1 2009/03/03 18:31:09 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.47.2.1 2009/03/03 18:31:09 skrll Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static bool piixide_resume(device_t PMF_FN_PROTO); 54 static bool piixide_suspend(device_t PMF_FN_PROTO); 55 static int piixide_match(device_t, cfdata_t, void *); 56 static void piixide_attach(device_t, device_t, void *); 57 58 static const struct pciide_product_desc pciide_intel_products[] = { 59 { PCI_PRODUCT_INTEL_82092AA, 60 0, 61 "Intel 82092AA IDE controller", 62 default_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371FB_IDE, 65 0, 66 "Intel 82371FB IDE controller (PIIX)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371SB_IDE, 70 0, 71 "Intel 82371SB IDE Interface (PIIX3)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82371AB_IDE, 75 0, 76 "Intel 82371AB IDE controller (PIIX4)", 77 piix_chip_map, 78 }, 79 { PCI_PRODUCT_INTEL_82440MX_IDE, 80 0, 81 "Intel 82440MX IDE controller", 82 piix_chip_map 83 }, 84 { PCI_PRODUCT_INTEL_82801AA_IDE, 85 0, 86 "Intel 82801AA IDE Controller (ICH)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801AB_IDE, 90 0, 91 "Intel 82801AB IDE Controller (ICH0)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BA_IDE, 95 0, 96 "Intel 82801BA IDE Controller (ICH2)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801BAM_IDE, 100 0, 101 "Intel 82801BAM IDE Controller (ICH2-M)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 110 0, 111 "Intel 82801CA IDE Controller (ICH3)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DB_IDE, 115 0, 116 "Intel 82801DB IDE Controller (ICH4)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801DBM_IDE, 120 0, 121 "Intel 82801DBM IDE Controller (ICH4-M)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_IDE, 125 0, 126 "Intel 82801EB IDE Controller (ICH5)", 127 piix_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801EB_SATA, 130 0, 131 "Intel 82801EB Serial ATA Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_82801ER_SATA, 135 0, 136 "Intel 82801ER Serial ATA/Raid Controller", 137 piixsata_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_IDE, 140 0, 141 "Intel 6300ESB IDE Controller (ICH5)", 142 piix_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_6300ESB_SATA, 145 0, 146 "Intel 6300ESB Serial ATA Controller", 147 piixsata_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_6300ESB_RAID, 150 0, 151 "Intel 6300ESB Serial ATA/RAID Controller", 152 piixsata_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FB_IDE, 155 0, 156 "Intel 82801FB IDE Controller (ICH6)", 157 piix_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FB_SATA, 160 0, 161 "Intel 82801FB Serial ATA/Raid Controller", 162 piixsata_chip_map, 163 }, 164 { PCI_PRODUCT_INTEL_82801FR_SATA, 165 0, 166 "Intel 82801FR Serial ATA/Raid Controller", 167 piixsata_chip_map, 168 }, 169 { PCI_PRODUCT_INTEL_82801FBM_SATA, 170 0, 171 "Intel 82801FBM Serial ATA Controller (ICH6)", 172 piixsata_chip_map, 173 }, 174 { PCI_PRODUCT_INTEL_82801G_IDE, 175 0, 176 "Intel 82801GB/GR IDE Controller (ICH7)", 177 piix_chip_map, 178 }, 179 { PCI_PRODUCT_INTEL_82801G_SATA, 180 0, 181 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 182 piixsata_chip_map, 183 }, 184 { PCI_PRODUCT_INTEL_82801GBM_SATA, 185 0, 186 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 187 piixsata_chip_map, 188 }, 189 { PCI_PRODUCT_INTEL_82801H_SATA_1, 190 0, 191 "Intel 82801H Serial ATA Controller (ICH8)", 192 piixsata_chip_map, 193 }, 194 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 195 0, 196 "Intel 82801H Serial ATA RAID Controller (ICH8)", 197 piixsata_chip_map, 198 }, 199 { PCI_PRODUCT_INTEL_82801H_SATA_2, 200 0, 201 "Intel 82801H Serial ATA Controller (ICH8)", 202 piixsata_chip_map, 203 }, 204 { PCI_PRODUCT_INTEL_82801HBM_IDE, 205 0, 206 "Intel 82801HBM IDE Controller (ICH8M)", 207 piix_chip_map, 208 }, 209 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 210 0, 211 "Intel 82801HBM Serial ATA Controller (ICH8M)", 212 piixsata_chip_map, 213 }, 214 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 215 0, 216 "Intel 82801HBM Serial ATA Controller (ICH8M)", 217 piixsata_chip_map, 218 }, 219 { PCI_PRODUCT_INTEL_82801HEM_SATA, 220 0, 221 "Intel 82801HEM Serial ATA Controller (ICH8M)", 222 piixsata_chip_map, 223 }, 224 { PCI_PRODUCT_INTEL_63XXESB_IDE, 225 0, 226 "Intel 631xESB/632xESB IDE Controller", 227 piix_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82801I_SATA_1, 230 0, 231 "Intel 82801I Serial ATA Controller (ICH9)", 232 piixsata_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82801I_SATA_2, 235 0, 236 "Intel 82801I Serial ATA Controller (ICH9)", 237 piixsata_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82801I_SATA_3, 240 0, 241 "Intel 82801I Serial ATA Controller (ICH9)", 242 piixsata_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_82801I_SATA_4, 245 0, 246 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 247 piixsata_chip_map, 248 }, 249 { PCI_PRODUCT_INTEL_82801I_SATA_5, 250 0, 251 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 252 piixsata_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82801I_SATA_6, 255 0, 256 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 257 piixsata_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_82801I_SATA_7, 260 0, 261 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 262 piixsata_chip_map, 263 }, 264 { PCI_PRODUCT_INTEL_63XXESB_SATA, 265 0, 266 "Intel 631xESB/632xESB Serial ATA Controller", 267 piixsata_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x1, 270 0, 271 "Intel ICH10 Serial ATA 2 Controller 2x1", 272 piixsata_chip_map, 273 }, 274 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x2, 275 0, 276 "Intel ICH10 Serial ATA 2 Controller 2x2", 277 piixsata_chip_map, 278 }, 279 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x1, 280 0, 281 "Intel ICH10 Serial ATA 2 Controller 4x1", 282 piixsata_chip_map, 283 }, 284 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x2, 285 0, 286 "Intel ICH10 Serial ATA 2 Controller 4x2", 287 piixsata_chip_map, 288 }, 289 { 0, 290 0, 291 NULL, 292 NULL 293 } 294 }; 295 296 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), 297 piixide_match, piixide_attach, NULL, NULL); 298 299 static int 300 piixide_match(device_t parent, cfdata_t match, void *aux) 301 { 302 struct pci_attach_args *pa = aux; 303 304 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 305 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 306 return (2); 307 } 308 return (0); 309 } 310 311 static void 312 piixide_attach(device_t parent, device_t self, void *aux) 313 { 314 struct pci_attach_args *pa = aux; 315 struct pciide_softc *sc = device_private(self); 316 317 sc->sc_wdcdev.sc_atac.atac_dev = self; 318 319 pciide_common_attach(sc, pa, 320 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 321 322 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 323 aprint_error_dev(self, "couldn't establish power handler\n"); 324 } 325 326 static bool 327 piixide_resume(device_t dv PMF_FN_ARGS) 328 { 329 struct pciide_softc *sc = device_private(dv); 330 331 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 332 sc->sc_pm_reg[0]); 333 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 334 sc->sc_pm_reg[1]); 335 336 return true; 337 } 338 339 static bool 340 piixide_suspend(device_t dv PMF_FN_ARGS) 341 { 342 struct pciide_softc *sc = device_private(dv); 343 344 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 345 PIIX_IDETIM); 346 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 347 PIIX_UDMAREG); 348 349 return true; 350 } 351 352 static void 353 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 354 { 355 struct pciide_channel *cp; 356 int channel; 357 u_int32_t idetim; 358 bus_size_t cmdsize, ctlsize; 359 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 360 361 if (pciide_chipen(sc, pa) == 0) 362 return; 363 364 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 365 "bus-master DMA support present"); 366 pciide_mapreg_dma(sc, pa); 367 aprint_verbose("\n"); 368 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 369 if (sc->sc_dma_ok) { 370 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 371 sc->sc_wdcdev.irqack = pciide_irqack; 372 /* Do all revisions require DMA alignment workaround? */ 373 sc->sc_wdcdev.dma_init = piix_dma_init; 374 switch(sc->sc_pp->ide_product) { 375 case PCI_PRODUCT_INTEL_82371AB_IDE: 376 case PCI_PRODUCT_INTEL_82440MX_IDE: 377 case PCI_PRODUCT_INTEL_82801AA_IDE: 378 case PCI_PRODUCT_INTEL_82801AB_IDE: 379 case PCI_PRODUCT_INTEL_82801BA_IDE: 380 case PCI_PRODUCT_INTEL_82801BAM_IDE: 381 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 382 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 383 case PCI_PRODUCT_INTEL_82801DB_IDE: 384 case PCI_PRODUCT_INTEL_82801DBM_IDE: 385 case PCI_PRODUCT_INTEL_82801EB_IDE: 386 case PCI_PRODUCT_INTEL_6300ESB_IDE: 387 case PCI_PRODUCT_INTEL_82801FB_IDE: 388 case PCI_PRODUCT_INTEL_82801G_IDE: 389 case PCI_PRODUCT_INTEL_82801HBM_IDE: 390 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 391 } 392 } 393 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 394 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 395 switch(sc->sc_pp->ide_product) { 396 case PCI_PRODUCT_INTEL_82801AA_IDE: 397 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 398 break; 399 case PCI_PRODUCT_INTEL_82801BA_IDE: 400 case PCI_PRODUCT_INTEL_82801BAM_IDE: 401 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 402 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 403 case PCI_PRODUCT_INTEL_82801DB_IDE: 404 case PCI_PRODUCT_INTEL_82801DBM_IDE: 405 case PCI_PRODUCT_INTEL_82801EB_IDE: 406 case PCI_PRODUCT_INTEL_6300ESB_IDE: 407 case PCI_PRODUCT_INTEL_82801FB_IDE: 408 case PCI_PRODUCT_INTEL_82801G_IDE: 409 case PCI_PRODUCT_INTEL_82801HBM_IDE: 410 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 411 break; 412 default: 413 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 414 } 415 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 416 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 417 else 418 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 419 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 420 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 421 422 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 423 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 424 DEBUG_PROBE); 425 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 426 ATADEBUG_PRINT((", sidetim=0x%x", 427 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 428 DEBUG_PROBE); 429 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 430 ATADEBUG_PRINT((", udamreg 0x%x", 431 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 432 DEBUG_PROBE); 433 } 434 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 435 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 436 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 437 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 438 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 439 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 440 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 441 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 442 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 443 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 444 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 445 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 446 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 447 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 448 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 449 DEBUG_PROBE); 450 } 451 452 } 453 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 454 455 wdc_allocate_regs(&sc->sc_wdcdev); 456 457 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 458 channel++) { 459 cp = &sc->pciide_channels[channel]; 460 if (pciide_chansetup(sc, channel, interface) == 0) 461 continue; 462 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 463 if ((PIIX_IDETIM_READ(idetim, channel) & 464 PIIX_IDETIM_IDE) == 0) { 465 #if 1 466 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 467 "%s channel ignored (disabled)\n", cp->name); 468 cp->ata_channel.ch_flags |= ATACH_DISABLED; 469 continue; 470 #else 471 pcireg_t interface; 472 473 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 474 channel); 475 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 476 idetim); 477 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 478 sc->sc_tag, PCI_CLASS_REG)); 479 aprint_normal("channel %d idetim=%08x interface=%02x\n", 480 channel, idetim, interface); 481 #endif 482 } 483 pciide_mapchan(pa, cp, interface, 484 &cmdsize, &ctlsize, pciide_pci_intr); 485 } 486 487 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 488 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 489 DEBUG_PROBE); 490 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 491 ATADEBUG_PRINT((", sidetim=0x%x", 492 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 493 DEBUG_PROBE); 494 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 495 ATADEBUG_PRINT((", udamreg 0x%x", 496 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 497 DEBUG_PROBE); 498 } 499 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 500 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 501 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 502 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 503 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 504 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 505 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 506 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 507 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 508 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 509 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 510 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 511 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 512 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 513 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 514 DEBUG_PROBE); 515 } 516 } 517 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 518 } 519 520 static void 521 piix_setup_channel(struct ata_channel *chp) 522 { 523 u_int8_t mode[2], drive; 524 u_int32_t oidetim, idetim, idedma_ctl; 525 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 526 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 527 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 528 529 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 530 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 531 idedma_ctl = 0; 532 533 /* set up new idetim: Enable IDE registers decode */ 534 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 535 chp->ch_channel); 536 537 /* setup DMA */ 538 pciide_channel_dma_setup(cp); 539 540 /* 541 * Here we have to mess up with drives mode: PIIX can't have 542 * different timings for master and slave drives. 543 * We need to find the best combination. 544 */ 545 546 /* If both drives supports DMA, take the lower mode */ 547 if ((drvp[0].drive_flags & DRIVE_DMA) && 548 (drvp[1].drive_flags & DRIVE_DMA)) { 549 mode[0] = mode[1] = 550 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 551 drvp[0].DMA_mode = mode[0]; 552 drvp[1].DMA_mode = mode[1]; 553 goto ok; 554 } 555 /* 556 * If only one drive supports DMA, use its mode, and 557 * put the other one in PIO mode 0 if mode not compatible 558 */ 559 if (drvp[0].drive_flags & DRIVE_DMA) { 560 mode[0] = drvp[0].DMA_mode; 561 mode[1] = drvp[1].PIO_mode; 562 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 563 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 564 mode[1] = drvp[1].PIO_mode = 0; 565 goto ok; 566 } 567 if (drvp[1].drive_flags & DRIVE_DMA) { 568 mode[1] = drvp[1].DMA_mode; 569 mode[0] = drvp[0].PIO_mode; 570 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 571 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 572 mode[0] = drvp[0].PIO_mode = 0; 573 goto ok; 574 } 575 /* 576 * If both drives are not DMA, takes the lower mode, unless 577 * one of them is PIO mode < 2 578 */ 579 if (drvp[0].PIO_mode < 2) { 580 mode[0] = drvp[0].PIO_mode = 0; 581 mode[1] = drvp[1].PIO_mode; 582 } else if (drvp[1].PIO_mode < 2) { 583 mode[1] = drvp[1].PIO_mode = 0; 584 mode[0] = drvp[0].PIO_mode; 585 } else { 586 mode[0] = mode[1] = 587 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 588 drvp[0].PIO_mode = mode[0]; 589 drvp[1].PIO_mode = mode[1]; 590 } 591 ok: /* The modes are setup */ 592 for (drive = 0; drive < 2; drive++) { 593 if (drvp[drive].drive_flags & DRIVE_DMA) { 594 idetim |= piix_setup_idetim_timings( 595 mode[drive], 1, chp->ch_channel); 596 goto end; 597 } 598 } 599 /* If we are there, none of the drives are DMA */ 600 if (mode[0] >= 2) 601 idetim |= piix_setup_idetim_timings( 602 mode[0], 0, chp->ch_channel); 603 else 604 idetim |= piix_setup_idetim_timings( 605 mode[1], 0, chp->ch_channel); 606 end: /* 607 * timing mode is now set up in the controller. Enable 608 * it per-drive 609 */ 610 for (drive = 0; drive < 2; drive++) { 611 /* If no drive, skip */ 612 if ((drvp[drive].drive_flags & DRIVE) == 0) 613 continue; 614 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 615 if (drvp[drive].drive_flags & DRIVE_DMA) 616 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 617 } 618 if (idedma_ctl != 0) { 619 /* Add software bits in status register */ 620 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 621 idedma_ctl); 622 } 623 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 624 } 625 626 static void 627 piix3_4_setup_channel(struct ata_channel *chp) 628 { 629 struct ata_drive_datas *drvp; 630 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 631 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 632 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 633 struct wdc_softc *wdc = &sc->sc_wdcdev; 634 int drive, s; 635 int channel = chp->ch_channel; 636 637 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 638 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 639 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 640 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 641 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 642 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 643 PIIX_SIDETIM_RTC_MASK(channel)); 644 idedma_ctl = 0; 645 646 /* set up new idetim: Enable IDE registers decode */ 647 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 648 649 /* setup DMA if needed */ 650 pciide_channel_dma_setup(cp); 651 652 for (drive = 0; drive < 2; drive++) { 653 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 654 PIIX_UDMATIM_SET(0x3, channel, drive)); 655 drvp = &chp->ch_drive[drive]; 656 /* If no drive, skip */ 657 if ((drvp->drive_flags & DRIVE) == 0) 658 continue; 659 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 660 (drvp->drive_flags & DRIVE_UDMA) == 0)) 661 goto pio; 662 663 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 664 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 665 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 666 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 667 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 668 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 669 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 670 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 671 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 672 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 673 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 674 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 675 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 676 ideconf |= PIIX_CONFIG_PINGPONG; 677 } 678 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 679 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 680 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 681 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 682 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 683 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 684 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 685 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 686 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 687 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 688 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 689 /* setup Ultra/100 */ 690 if (drvp->UDMA_mode > 2 && 691 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 692 drvp->UDMA_mode = 2; 693 if (drvp->UDMA_mode > 4) { 694 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 695 } else { 696 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 697 if (drvp->UDMA_mode > 2) { 698 ideconf |= PIIX_CONFIG_UDMA66(channel, 699 drive); 700 } else { 701 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 702 drive); 703 } 704 } 705 } 706 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 707 /* setup Ultra/66 */ 708 if (drvp->UDMA_mode > 2 && 709 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 710 drvp->UDMA_mode = 2; 711 if (drvp->UDMA_mode > 2) 712 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 713 else 714 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 715 } 716 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 717 (drvp->drive_flags & DRIVE_UDMA)) { 718 /* use Ultra/DMA */ 719 s = splbio(); 720 drvp->drive_flags &= ~DRIVE_DMA; 721 splx(s); 722 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 723 udmareg |= PIIX_UDMATIM_SET( 724 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 725 } else { 726 /* use Multiword DMA */ 727 s = splbio(); 728 drvp->drive_flags &= ~DRIVE_UDMA; 729 splx(s); 730 if (drive == 0) { 731 idetim |= piix_setup_idetim_timings( 732 drvp->DMA_mode, 1, channel); 733 } else { 734 sidetim |= piix_setup_sidetim_timings( 735 drvp->DMA_mode, 1, channel); 736 idetim =PIIX_IDETIM_SET(idetim, 737 PIIX_IDETIM_SITRE, channel); 738 } 739 } 740 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 741 742 pio: /* use PIO mode */ 743 idetim |= piix_setup_idetim_drvs(drvp); 744 if (drive == 0) { 745 idetim |= piix_setup_idetim_timings( 746 drvp->PIO_mode, 0, channel); 747 } else { 748 sidetim |= piix_setup_sidetim_timings( 749 drvp->PIO_mode, 0, channel); 750 idetim =PIIX_IDETIM_SET(idetim, 751 PIIX_IDETIM_SITRE, channel); 752 } 753 } 754 if (idedma_ctl != 0) { 755 /* Add software bits in status register */ 756 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 757 idedma_ctl); 758 } 759 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 760 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 761 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 762 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 763 } 764 765 766 /* setup ISP and RTC fields, based on mode */ 767 static u_int32_t 768 piix_setup_idetim_timings(mode, dma, channel) 769 u_int8_t mode; 770 u_int8_t dma; 771 u_int8_t channel; 772 { 773 774 if (dma) 775 return PIIX_IDETIM_SET(0, 776 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 777 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 778 channel); 779 else 780 return PIIX_IDETIM_SET(0, 781 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 782 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 783 channel); 784 } 785 786 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 787 static u_int32_t 788 piix_setup_idetim_drvs(drvp) 789 struct ata_drive_datas *drvp; 790 { 791 u_int32_t ret = 0; 792 struct ata_channel *chp = drvp->chnl_softc; 793 u_int8_t channel = chp->ch_channel; 794 u_int8_t drive = drvp->drive; 795 796 /* 797 * If drive is using UDMA, timings setups are independent 798 * So just check DMA and PIO here. 799 */ 800 if (drvp->drive_flags & DRIVE_DMA) { 801 /* if mode = DMA mode 0, use compatible timings */ 802 if ((drvp->drive_flags & DRIVE_DMA) && 803 drvp->DMA_mode == 0) { 804 drvp->PIO_mode = 0; 805 return ret; 806 } 807 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 808 /* 809 * PIO and DMA timings are the same, use fast timings for PIO 810 * too, else use compat timings. 811 */ 812 if ((piix_isp_pio[drvp->PIO_mode] != 813 piix_isp_dma[drvp->DMA_mode]) || 814 (piix_rtc_pio[drvp->PIO_mode] != 815 piix_rtc_dma[drvp->DMA_mode])) 816 drvp->PIO_mode = 0; 817 /* if PIO mode <= 2, use compat timings for PIO */ 818 if (drvp->PIO_mode <= 2) { 819 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 820 channel); 821 return ret; 822 } 823 } 824 825 /* 826 * Now setup PIO modes. If mode < 2, use compat timings. 827 * Else enable fast timings. Enable IORDY and prefetch/post 828 * if PIO mode >= 3. 829 */ 830 831 if (drvp->PIO_mode < 2) 832 return ret; 833 834 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 835 if (drvp->PIO_mode >= 3) { 836 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 837 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 838 } 839 return ret; 840 } 841 842 /* setup values in SIDETIM registers, based on mode */ 843 static u_int32_t 844 piix_setup_sidetim_timings(mode, dma, channel) 845 u_int8_t mode; 846 u_int8_t dma; 847 u_int8_t channel; 848 { 849 if (dma) 850 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 851 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 852 else 853 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 854 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 855 } 856 857 static void 858 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 859 { 860 struct pciide_channel *cp; 861 bus_size_t cmdsize, ctlsize; 862 pcireg_t interface, cmdsts; 863 int channel; 864 865 if (pciide_chipen(sc, pa) == 0) 866 return; 867 868 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 869 "bus-master DMA support present"); 870 pciide_mapreg_dma(sc, pa); 871 aprint_verbose("\n"); 872 873 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 874 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 875 if (sc->sc_dma_ok) { 876 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 877 sc->sc_wdcdev.irqack = pciide_irqack; 878 /* Do all revisions require DMA alignment workaround? */ 879 sc->sc_wdcdev.dma_init = piix_dma_init; 880 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 881 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 882 } 883 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 884 885 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 886 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 887 888 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 889 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 890 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 891 892 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 893 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 894 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 895 896 interface = PCI_INTERFACE(pa->pa_class); 897 898 wdc_allocate_regs(&sc->sc_wdcdev); 899 900 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 901 channel++) { 902 cp = &sc->pciide_channels[channel]; 903 if (pciide_chansetup(sc, channel, interface) == 0) 904 continue; 905 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 906 pciide_pci_intr); 907 } 908 } 909 910 static int 911 piix_dma_init(void *v, int channel, int drive, void *databuf, 912 size_t datalen, int flags) 913 { 914 915 /* use PIO for unaligned transfer */ 916 if (((uintptr_t)databuf) & 0x1) 917 return EINVAL; 918 919 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 920 } 921
Indexes created Mon Oct 20 11:09:49 GMT 2025