piixide.c revision 1.47.4.1
1 /* $NetBSD: piixide.c,v 1.47.4.1 2009/12/18 05:48:07 snj Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.47.4.1 2009/12/18 05:48:07 snj Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static bool piixide_resume(device_t PMF_FN_PROTO); 54 static bool piixide_suspend(device_t PMF_FN_PROTO); 55 static int piixide_match(device_t, cfdata_t, void *); 56 static void piixide_attach(device_t, device_t, void *); 57 58 static const struct pciide_product_desc pciide_intel_products[] = { 59 { PCI_PRODUCT_INTEL_82092AA, 60 0, 61 "Intel 82092AA IDE controller", 62 default_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371FB_IDE, 65 0, 66 "Intel 82371FB IDE controller (PIIX)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371SB_IDE, 70 0, 71 "Intel 82371SB IDE Interface (PIIX3)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82371AB_IDE, 75 0, 76 "Intel 82371AB IDE controller (PIIX4)", 77 piix_chip_map, 78 }, 79 { PCI_PRODUCT_INTEL_82440MX_IDE, 80 0, 81 "Intel 82440MX IDE controller", 82 piix_chip_map 83 }, 84 { PCI_PRODUCT_INTEL_82801AA_IDE, 85 0, 86 "Intel 82801AA IDE Controller (ICH)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801AB_IDE, 90 0, 91 "Intel 82801AB IDE Controller (ICH0)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BA_IDE, 95 0, 96 "Intel 82801BA IDE Controller (ICH2)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801BAM_IDE, 100 0, 101 "Intel 82801BAM IDE Controller (ICH2-M)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 110 0, 111 "Intel 82801CA IDE Controller (ICH3)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DB_IDE, 115 0, 116 "Intel 82801DB IDE Controller (ICH4)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801DBM_IDE, 120 0, 121 "Intel 82801DBM IDE Controller (ICH4-M)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_IDE, 125 0, 126 "Intel 82801EB IDE Controller (ICH5)", 127 piix_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801EB_SATA, 130 0, 131 "Intel 82801EB Serial ATA Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_82801ER_SATA, 135 0, 136 "Intel 82801ER Serial ATA/Raid Controller", 137 piixsata_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_IDE, 140 0, 141 "Intel 6300ESB IDE Controller (ICH5)", 142 piix_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_6300ESB_SATA, 145 0, 146 "Intel 6300ESB Serial ATA Controller", 147 piixsata_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_6300ESB_RAID, 150 0, 151 "Intel 6300ESB Serial ATA/RAID Controller", 152 piixsata_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FB_IDE, 155 0, 156 "Intel 82801FB IDE Controller (ICH6)", 157 piix_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FB_SATA, 160 0, 161 "Intel 82801FB Serial ATA/Raid Controller", 162 piixsata_chip_map, 163 }, 164 { PCI_PRODUCT_INTEL_82801FR_SATA, 165 0, 166 "Intel 82801FR Serial ATA/Raid Controller", 167 piixsata_chip_map, 168 }, 169 { PCI_PRODUCT_INTEL_82801FBM_SATA, 170 0, 171 "Intel 82801FBM Serial ATA Controller (ICH6)", 172 piixsata_chip_map, 173 }, 174 { PCI_PRODUCT_INTEL_82801G_IDE, 175 0, 176 "Intel 82801GB/GR IDE Controller (ICH7)", 177 piix_chip_map, 178 }, 179 { PCI_PRODUCT_INTEL_82801G_SATA, 180 0, 181 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 182 piixsata_chip_map, 183 }, 184 { PCI_PRODUCT_INTEL_82801GBM_SATA, 185 0, 186 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 187 piixsata_chip_map, 188 }, 189 { PCI_PRODUCT_INTEL_82801H_SATA_1, 190 0, 191 "Intel 82801H Serial ATA Controller (ICH8)", 192 piixsata_chip_map, 193 }, 194 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 195 0, 196 "Intel 82801H Serial ATA RAID Controller (ICH8)", 197 piixsata_chip_map, 198 }, 199 { PCI_PRODUCT_INTEL_82801H_SATA_2, 200 0, 201 "Intel 82801H Serial ATA Controller (ICH8)", 202 piixsata_chip_map, 203 }, 204 { PCI_PRODUCT_INTEL_82801HBM_IDE, 205 0, 206 "Intel 82801HBM IDE Controller (ICH8M)", 207 piix_chip_map, 208 }, 209 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 210 0, 211 "Intel 82801HBM Serial ATA Controller (ICH8M)", 212 piixsata_chip_map, 213 }, 214 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 215 0, 216 "Intel 82801HBM Serial ATA Controller (ICH8M)", 217 piixsata_chip_map, 218 }, 219 { PCI_PRODUCT_INTEL_82801HEM_SATA, 220 0, 221 "Intel 82801HEM Serial ATA Controller (ICH8M)", 222 piixsata_chip_map, 223 }, 224 { PCI_PRODUCT_INTEL_63XXESB_IDE, 225 0, 226 "Intel 631xESB/632xESB IDE Controller", 227 piix_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82801I_SATA_1, 230 0, 231 "Intel 82801I Serial ATA Controller (ICH9)", 232 piixsata_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82801I_SATA_2, 235 0, 236 "Intel 82801I Serial ATA Controller (ICH9)", 237 piixsata_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82801I_SATA_3, 240 0, 241 "Intel 82801I Serial ATA Controller (ICH9)", 242 piixsata_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_63XXESB_SATA, 245 0, 246 "Intel 631xESB/632xESB Serial ATA Controller", 247 piixsata_chip_map, 248 }, 249 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x1, 250 0, 251 "Intel ICH10 Serial ATA 2 Controller 2x1", 252 piixsata_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x2, 255 0, 256 "Intel ICH10 Serial ATA 2 Controller 2x2", 257 piixsata_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x1, 260 0, 261 "Intel ICH10 Serial ATA 2 Controller 4x1", 262 piixsata_chip_map, 263 }, 264 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x2, 265 0, 266 "Intel ICH10 Serial ATA 2 Controller 4x2", 267 piixsata_chip_map, 268 }, 269 { 270 PCI_PRODUCT_INTEL_3400_SATA_1, 271 0, 272 "Intel 3400 Serial ATA Controller", 273 piixsata_chip_map, 274 }, 275 { 276 PCI_PRODUCT_INTEL_3400_SATA_1, 277 0, 278 "Intel 3400 Serial ATA Controller", 279 piixsata_chip_map, 280 }, 281 { 282 PCI_PRODUCT_INTEL_3400_SATA_2, 283 0, 284 "Intel 3400 Serial ATA Controller", 285 piixsata_chip_map, 286 }, 287 { 288 PCI_PRODUCT_INTEL_3400_SATA_3, 289 0, 290 "Intel 3400 Serial ATA Controller", 291 piixsata_chip_map, 292 }, 293 { 294 PCI_PRODUCT_INTEL_3400_SATA_4, 295 0, 296 "Intel 3400 Serial ATA Controller", 297 piixsata_chip_map, 298 }, 299 { 300 PCI_PRODUCT_INTEL_3400_SATA_5, 301 0, 302 "Intel 3400 Serial ATA Controller", 303 piixsata_chip_map, 304 }, 305 { 306 PCI_PRODUCT_INTEL_3400_SATA_6, 307 0, 308 "Intel 3400 Serial ATA Controller", 309 piixsata_chip_map, 310 }, 311 { 0, 312 0, 313 NULL, 314 NULL 315 } 316 }; 317 318 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), 319 piixide_match, piixide_attach, NULL, NULL); 320 321 static int 322 piixide_match(device_t parent, cfdata_t match, void *aux) 323 { 324 struct pci_attach_args *pa = aux; 325 326 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 327 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 328 return (2); 329 } 330 return (0); 331 } 332 333 static void 334 piixide_attach(device_t parent, device_t self, void *aux) 335 { 336 struct pci_attach_args *pa = aux; 337 struct pciide_softc *sc = device_private(self); 338 339 sc->sc_wdcdev.sc_atac.atac_dev = self; 340 341 pciide_common_attach(sc, pa, 342 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 343 344 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 345 aprint_error_dev(self, "couldn't establish power handler\n"); 346 } 347 348 static bool 349 piixide_resume(device_t dv PMF_FN_ARGS) 350 { 351 struct pciide_softc *sc = device_private(dv); 352 353 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 354 sc->sc_pm_reg[0]); 355 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 356 sc->sc_pm_reg[1]); 357 358 return true; 359 } 360 361 static bool 362 piixide_suspend(device_t dv PMF_FN_ARGS) 363 { 364 struct pciide_softc *sc = device_private(dv); 365 366 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 367 PIIX_IDETIM); 368 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 369 PIIX_UDMAREG); 370 371 return true; 372 } 373 374 static void 375 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 376 { 377 struct pciide_channel *cp; 378 int channel; 379 u_int32_t idetim; 380 bus_size_t cmdsize, ctlsize; 381 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 382 383 if (pciide_chipen(sc, pa) == 0) 384 return; 385 386 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 387 "bus-master DMA support present"); 388 pciide_mapreg_dma(sc, pa); 389 aprint_verbose("\n"); 390 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 391 if (sc->sc_dma_ok) { 392 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 393 sc->sc_wdcdev.irqack = pciide_irqack; 394 /* Do all revisions require DMA alignment workaround? */ 395 sc->sc_wdcdev.dma_init = piix_dma_init; 396 switch(sc->sc_pp->ide_product) { 397 case PCI_PRODUCT_INTEL_82371AB_IDE: 398 case PCI_PRODUCT_INTEL_82440MX_IDE: 399 case PCI_PRODUCT_INTEL_82801AA_IDE: 400 case PCI_PRODUCT_INTEL_82801AB_IDE: 401 case PCI_PRODUCT_INTEL_82801BA_IDE: 402 case PCI_PRODUCT_INTEL_82801BAM_IDE: 403 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 404 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 405 case PCI_PRODUCT_INTEL_82801DB_IDE: 406 case PCI_PRODUCT_INTEL_82801DBM_IDE: 407 case PCI_PRODUCT_INTEL_82801EB_IDE: 408 case PCI_PRODUCT_INTEL_6300ESB_IDE: 409 case PCI_PRODUCT_INTEL_82801FB_IDE: 410 case PCI_PRODUCT_INTEL_82801G_IDE: 411 case PCI_PRODUCT_INTEL_82801HBM_IDE: 412 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 413 } 414 } 415 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 416 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 417 switch(sc->sc_pp->ide_product) { 418 case PCI_PRODUCT_INTEL_82801AA_IDE: 419 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 420 break; 421 case PCI_PRODUCT_INTEL_82801BA_IDE: 422 case PCI_PRODUCT_INTEL_82801BAM_IDE: 423 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 424 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 425 case PCI_PRODUCT_INTEL_82801DB_IDE: 426 case PCI_PRODUCT_INTEL_82801DBM_IDE: 427 case PCI_PRODUCT_INTEL_82801EB_IDE: 428 case PCI_PRODUCT_INTEL_6300ESB_IDE: 429 case PCI_PRODUCT_INTEL_82801FB_IDE: 430 case PCI_PRODUCT_INTEL_82801G_IDE: 431 case PCI_PRODUCT_INTEL_82801HBM_IDE: 432 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 433 break; 434 default: 435 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 436 } 437 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 438 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 439 else 440 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 441 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 442 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 443 444 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 445 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 446 DEBUG_PROBE); 447 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 448 ATADEBUG_PRINT((", sidetim=0x%x", 449 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 450 DEBUG_PROBE); 451 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 452 ATADEBUG_PRINT((", udamreg 0x%x", 453 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 454 DEBUG_PROBE); 455 } 456 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 457 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 458 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 459 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 460 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 461 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 462 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 464 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 465 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 466 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 469 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 470 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 471 DEBUG_PROBE); 472 } 473 474 } 475 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 476 477 wdc_allocate_regs(&sc->sc_wdcdev); 478 479 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 480 channel++) { 481 cp = &sc->pciide_channels[channel]; 482 if (pciide_chansetup(sc, channel, interface) == 0) 483 continue; 484 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 485 if ((PIIX_IDETIM_READ(idetim, channel) & 486 PIIX_IDETIM_IDE) == 0) { 487 #if 1 488 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 489 "%s channel ignored (disabled)\n", cp->name); 490 cp->ata_channel.ch_flags |= ATACH_DISABLED; 491 continue; 492 #else 493 pcireg_t interface; 494 495 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 496 channel); 497 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 498 idetim); 499 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 500 sc->sc_tag, PCI_CLASS_REG)); 501 aprint_normal("channel %d idetim=%08x interface=%02x\n", 502 channel, idetim, interface); 503 #endif 504 } 505 pciide_mapchan(pa, cp, interface, 506 &cmdsize, &ctlsize, pciide_pci_intr); 507 } 508 509 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 510 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 511 DEBUG_PROBE); 512 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 513 ATADEBUG_PRINT((", sidetim=0x%x", 514 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 515 DEBUG_PROBE); 516 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 517 ATADEBUG_PRINT((", udamreg 0x%x", 518 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 519 DEBUG_PROBE); 520 } 521 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 522 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 523 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 524 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 525 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 526 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 527 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 528 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 529 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 530 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 531 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 532 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 533 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 534 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 535 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 536 DEBUG_PROBE); 537 } 538 } 539 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 540 } 541 542 static void 543 piix_setup_channel(struct ata_channel *chp) 544 { 545 u_int8_t mode[2], drive; 546 u_int32_t oidetim, idetim, idedma_ctl; 547 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 548 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 549 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 550 551 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 552 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 553 idedma_ctl = 0; 554 555 /* set up new idetim: Enable IDE registers decode */ 556 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 557 chp->ch_channel); 558 559 /* setup DMA */ 560 pciide_channel_dma_setup(cp); 561 562 /* 563 * Here we have to mess up with drives mode: PIIX can't have 564 * different timings for master and slave drives. 565 * We need to find the best combination. 566 */ 567 568 /* If both drives supports DMA, take the lower mode */ 569 if ((drvp[0].drive_flags & DRIVE_DMA) && 570 (drvp[1].drive_flags & DRIVE_DMA)) { 571 mode[0] = mode[1] = 572 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 573 drvp[0].DMA_mode = mode[0]; 574 drvp[1].DMA_mode = mode[1]; 575 goto ok; 576 } 577 /* 578 * If only one drive supports DMA, use its mode, and 579 * put the other one in PIO mode 0 if mode not compatible 580 */ 581 if (drvp[0].drive_flags & DRIVE_DMA) { 582 mode[0] = drvp[0].DMA_mode; 583 mode[1] = drvp[1].PIO_mode; 584 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 585 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 586 mode[1] = drvp[1].PIO_mode = 0; 587 goto ok; 588 } 589 if (drvp[1].drive_flags & DRIVE_DMA) { 590 mode[1] = drvp[1].DMA_mode; 591 mode[0] = drvp[0].PIO_mode; 592 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 593 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 594 mode[0] = drvp[0].PIO_mode = 0; 595 goto ok; 596 } 597 /* 598 * If both drives are not DMA, takes the lower mode, unless 599 * one of them is PIO mode < 2 600 */ 601 if (drvp[0].PIO_mode < 2) { 602 mode[0] = drvp[0].PIO_mode = 0; 603 mode[1] = drvp[1].PIO_mode; 604 } else if (drvp[1].PIO_mode < 2) { 605 mode[1] = drvp[1].PIO_mode = 0; 606 mode[0] = drvp[0].PIO_mode; 607 } else { 608 mode[0] = mode[1] = 609 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 610 drvp[0].PIO_mode = mode[0]; 611 drvp[1].PIO_mode = mode[1]; 612 } 613 ok: /* The modes are setup */ 614 for (drive = 0; drive < 2; drive++) { 615 if (drvp[drive].drive_flags & DRIVE_DMA) { 616 idetim |= piix_setup_idetim_timings( 617 mode[drive], 1, chp->ch_channel); 618 goto end; 619 } 620 } 621 /* If we are there, none of the drives are DMA */ 622 if (mode[0] >= 2) 623 idetim |= piix_setup_idetim_timings( 624 mode[0], 0, chp->ch_channel); 625 else 626 idetim |= piix_setup_idetim_timings( 627 mode[1], 0, chp->ch_channel); 628 end: /* 629 * timing mode is now set up in the controller. Enable 630 * it per-drive 631 */ 632 for (drive = 0; drive < 2; drive++) { 633 /* If no drive, skip */ 634 if ((drvp[drive].drive_flags & DRIVE) == 0) 635 continue; 636 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 637 if (drvp[drive].drive_flags & DRIVE_DMA) 638 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 639 } 640 if (idedma_ctl != 0) { 641 /* Add software bits in status register */ 642 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 643 idedma_ctl); 644 } 645 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 646 } 647 648 static void 649 piix3_4_setup_channel(struct ata_channel *chp) 650 { 651 struct ata_drive_datas *drvp; 652 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 653 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 654 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 655 struct wdc_softc *wdc = &sc->sc_wdcdev; 656 int drive, s; 657 int channel = chp->ch_channel; 658 659 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 660 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 661 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 662 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 663 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 664 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 665 PIIX_SIDETIM_RTC_MASK(channel)); 666 idedma_ctl = 0; 667 668 /* set up new idetim: Enable IDE registers decode */ 669 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 670 671 /* setup DMA if needed */ 672 pciide_channel_dma_setup(cp); 673 674 for (drive = 0; drive < 2; drive++) { 675 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 676 PIIX_UDMATIM_SET(0x3, channel, drive)); 677 drvp = &chp->ch_drive[drive]; 678 /* If no drive, skip */ 679 if ((drvp->drive_flags & DRIVE) == 0) 680 continue; 681 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 682 (drvp->drive_flags & DRIVE_UDMA) == 0)) 683 goto pio; 684 685 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 686 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 687 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 688 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 689 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 690 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 691 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 692 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 693 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 694 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 695 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 696 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 697 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 698 ideconf |= PIIX_CONFIG_PINGPONG; 699 } 700 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 701 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 702 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 703 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 704 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 705 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 706 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 707 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 708 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 709 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 710 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 711 /* setup Ultra/100 */ 712 if (drvp->UDMA_mode > 2 && 713 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 714 drvp->UDMA_mode = 2; 715 if (drvp->UDMA_mode > 4) { 716 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 717 } else { 718 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 719 if (drvp->UDMA_mode > 2) { 720 ideconf |= PIIX_CONFIG_UDMA66(channel, 721 drive); 722 } else { 723 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 724 drive); 725 } 726 } 727 } 728 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 729 /* setup Ultra/66 */ 730 if (drvp->UDMA_mode > 2 && 731 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 732 drvp->UDMA_mode = 2; 733 if (drvp->UDMA_mode > 2) 734 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 735 else 736 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 737 } 738 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 739 (drvp->drive_flags & DRIVE_UDMA)) { 740 /* use Ultra/DMA */ 741 s = splbio(); 742 drvp->drive_flags &= ~DRIVE_DMA; 743 splx(s); 744 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 745 udmareg |= PIIX_UDMATIM_SET( 746 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 747 } else { 748 /* use Multiword DMA */ 749 s = splbio(); 750 drvp->drive_flags &= ~DRIVE_UDMA; 751 splx(s); 752 if (drive == 0) { 753 idetim |= piix_setup_idetim_timings( 754 drvp->DMA_mode, 1, channel); 755 } else { 756 sidetim |= piix_setup_sidetim_timings( 757 drvp->DMA_mode, 1, channel); 758 idetim =PIIX_IDETIM_SET(idetim, 759 PIIX_IDETIM_SITRE, channel); 760 } 761 } 762 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 763 764 pio: /* use PIO mode */ 765 idetim |= piix_setup_idetim_drvs(drvp); 766 if (drive == 0) { 767 idetim |= piix_setup_idetim_timings( 768 drvp->PIO_mode, 0, channel); 769 } else { 770 sidetim |= piix_setup_sidetim_timings( 771 drvp->PIO_mode, 0, channel); 772 idetim =PIIX_IDETIM_SET(idetim, 773 PIIX_IDETIM_SITRE, channel); 774 } 775 } 776 if (idedma_ctl != 0) { 777 /* Add software bits in status register */ 778 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 779 idedma_ctl); 780 } 781 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 782 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 783 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 784 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 785 } 786 787 788 /* setup ISP and RTC fields, based on mode */ 789 static u_int32_t 790 piix_setup_idetim_timings(mode, dma, channel) 791 u_int8_t mode; 792 u_int8_t dma; 793 u_int8_t channel; 794 { 795 796 if (dma) 797 return PIIX_IDETIM_SET(0, 798 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 799 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 800 channel); 801 else 802 return PIIX_IDETIM_SET(0, 803 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 804 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 805 channel); 806 } 807 808 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 809 static u_int32_t 810 piix_setup_idetim_drvs(drvp) 811 struct ata_drive_datas *drvp; 812 { 813 u_int32_t ret = 0; 814 struct ata_channel *chp = drvp->chnl_softc; 815 u_int8_t channel = chp->ch_channel; 816 u_int8_t drive = drvp->drive; 817 818 /* 819 * If drive is using UDMA, timings setups are independent 820 * So just check DMA and PIO here. 821 */ 822 if (drvp->drive_flags & DRIVE_DMA) { 823 /* if mode = DMA mode 0, use compatible timings */ 824 if ((drvp->drive_flags & DRIVE_DMA) && 825 drvp->DMA_mode == 0) { 826 drvp->PIO_mode = 0; 827 return ret; 828 } 829 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 830 /* 831 * PIO and DMA timings are the same, use fast timings for PIO 832 * too, else use compat timings. 833 */ 834 if ((piix_isp_pio[drvp->PIO_mode] != 835 piix_isp_dma[drvp->DMA_mode]) || 836 (piix_rtc_pio[drvp->PIO_mode] != 837 piix_rtc_dma[drvp->DMA_mode])) 838 drvp->PIO_mode = 0; 839 /* if PIO mode <= 2, use compat timings for PIO */ 840 if (drvp->PIO_mode <= 2) { 841 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 842 channel); 843 return ret; 844 } 845 } 846 847 /* 848 * Now setup PIO modes. If mode < 2, use compat timings. 849 * Else enable fast timings. Enable IORDY and prefetch/post 850 * if PIO mode >= 3. 851 */ 852 853 if (drvp->PIO_mode < 2) 854 return ret; 855 856 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 857 if (drvp->PIO_mode >= 3) { 858 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 859 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 860 } 861 return ret; 862 } 863 864 /* setup values in SIDETIM registers, based on mode */ 865 static u_int32_t 866 piix_setup_sidetim_timings(mode, dma, channel) 867 u_int8_t mode; 868 u_int8_t dma; 869 u_int8_t channel; 870 { 871 if (dma) 872 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 873 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 874 else 875 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 876 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 877 } 878 879 static void 880 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 881 { 882 struct pciide_channel *cp; 883 bus_size_t cmdsize, ctlsize; 884 pcireg_t interface, cmdsts; 885 int channel; 886 887 if (pciide_chipen(sc, pa) == 0) 888 return; 889 890 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 891 "bus-master DMA support present"); 892 pciide_mapreg_dma(sc, pa); 893 aprint_verbose("\n"); 894 895 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 896 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 897 if (sc->sc_dma_ok) { 898 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 899 sc->sc_wdcdev.irqack = pciide_irqack; 900 /* Do all revisions require DMA alignment workaround? */ 901 sc->sc_wdcdev.dma_init = piix_dma_init; 902 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 903 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 904 } 905 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 906 907 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 908 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 909 910 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 911 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 912 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 913 914 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 915 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 916 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 917 918 interface = PCI_INTERFACE(pa->pa_class); 919 920 wdc_allocate_regs(&sc->sc_wdcdev); 921 922 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 923 channel++) { 924 cp = &sc->pciide_channels[channel]; 925 if (pciide_chansetup(sc, channel, interface) == 0) 926 continue; 927 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 928 pciide_pci_intr); 929 } 930 } 931 932 static int 933 piix_dma_init(void *v, int channel, int drive, void *databuf, 934 size_t datalen, int flags) 935 { 936 937 /* use PIO for unaligned transfer */ 938 if (((uintptr_t)databuf) & 0x1) 939 return EINVAL; 940 941 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 942 } 943
Indexes created Fri Oct 17 00:09:41 GMT 2025