piixide.c revision 1.49
1 /* $NetBSD: piixide.c,v 1.49 2009/03/09 13:13:25 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.49 2009/03/09 13:13:25 christos Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_piix_reg.h> 43 44 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 45 static void piix_setup_channel(struct ata_channel *); 46 static void piix3_4_setup_channel(struct ata_channel *); 47 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 48 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 49 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 50 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 51 static int piix_dma_init(void *, int, int, void *, size_t, int); 52 53 static bool piixide_resume(device_t PMF_FN_PROTO); 54 static bool piixide_suspend(device_t PMF_FN_PROTO); 55 static int piixide_match(device_t, cfdata_t, void *); 56 static void piixide_attach(device_t, device_t, void *); 57 58 static const struct pciide_product_desc pciide_intel_products[] = { 59 { PCI_PRODUCT_INTEL_82092AA, 60 0, 61 "Intel 82092AA IDE controller", 62 default_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371FB_IDE, 65 0, 66 "Intel 82371FB IDE controller (PIIX)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371SB_IDE, 70 0, 71 "Intel 82371SB IDE Interface (PIIX3)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82371AB_IDE, 75 0, 76 "Intel 82371AB IDE controller (PIIX4)", 77 piix_chip_map, 78 }, 79 { PCI_PRODUCT_INTEL_82440MX_IDE, 80 0, 81 "Intel 82440MX IDE controller", 82 piix_chip_map 83 }, 84 { PCI_PRODUCT_INTEL_82801AA_IDE, 85 0, 86 "Intel 82801AA IDE Controller (ICH)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801AB_IDE, 90 0, 91 "Intel 82801AB IDE Controller (ICH0)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BA_IDE, 95 0, 96 "Intel 82801BA IDE Controller (ICH2)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801BAM_IDE, 100 0, 101 "Intel 82801BAM IDE Controller (ICH2-M)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 110 0, 111 "Intel 82801CA IDE Controller (ICH3)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DB_IDE, 115 0, 116 "Intel 82801DB IDE Controller (ICH4)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801DBM_IDE, 120 0, 121 "Intel 82801DBM IDE Controller (ICH4-M)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_IDE, 125 0, 126 "Intel 82801EB IDE Controller (ICH5)", 127 piix_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801EB_SATA, 130 0, 131 "Intel 82801EB Serial ATA Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_82801ER_SATA, 135 0, 136 "Intel 82801ER Serial ATA/Raid Controller", 137 piixsata_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_IDE, 140 0, 141 "Intel 6300ESB IDE Controller (ICH5)", 142 piix_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_6300ESB_SATA, 145 0, 146 "Intel 6300ESB Serial ATA Controller", 147 piixsata_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_6300ESB_RAID, 150 0, 151 "Intel 6300ESB Serial ATA/RAID Controller", 152 piixsata_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FB_IDE, 155 0, 156 "Intel 82801FB IDE Controller (ICH6)", 157 piix_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FB_SATA, 160 0, 161 "Intel 82801FB Serial ATA/Raid Controller", 162 piixsata_chip_map, 163 }, 164 { PCI_PRODUCT_INTEL_82801FR_SATA, 165 0, 166 "Intel 82801FR Serial ATA/Raid Controller", 167 piixsata_chip_map, 168 }, 169 { PCI_PRODUCT_INTEL_82801FBM_SATA, 170 0, 171 "Intel 82801FBM Serial ATA Controller (ICH6)", 172 piixsata_chip_map, 173 }, 174 { PCI_PRODUCT_INTEL_82801G_IDE, 175 0, 176 "Intel 82801GB/GR IDE Controller (ICH7)", 177 piix_chip_map, 178 }, 179 { PCI_PRODUCT_INTEL_82801G_SATA, 180 0, 181 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 182 piixsata_chip_map, 183 }, 184 { PCI_PRODUCT_INTEL_82801GBM_SATA, 185 0, 186 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 187 piixsata_chip_map, 188 }, 189 { PCI_PRODUCT_INTEL_82801H_SATA_1, 190 0, 191 "Intel 82801H Serial ATA Controller (ICH8)", 192 piixsata_chip_map, 193 }, 194 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 195 0, 196 "Intel 82801H Serial ATA RAID Controller (ICH8)", 197 piixsata_chip_map, 198 }, 199 { PCI_PRODUCT_INTEL_82801H_SATA_2, 200 0, 201 "Intel 82801H Serial ATA Controller (ICH8)", 202 piixsata_chip_map, 203 }, 204 { PCI_PRODUCT_INTEL_82801HBM_IDE, 205 0, 206 "Intel 82801HBM IDE Controller (ICH8M)", 207 piix_chip_map, 208 }, 209 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 210 0, 211 "Intel 82801HBM Serial ATA Controller (ICH8M)", 212 piixsata_chip_map, 213 }, 214 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 215 0, 216 "Intel 82801HBM Serial ATA Controller (ICH8M)", 217 piixsata_chip_map, 218 }, 219 { PCI_PRODUCT_INTEL_82801HEM_SATA, 220 0, 221 "Intel 82801HEM Serial ATA Controller (ICH8M)", 222 piixsata_chip_map, 223 }, 224 { PCI_PRODUCT_INTEL_63XXESB_IDE, 225 0, 226 "Intel 631xESB/632xESB IDE Controller", 227 piix_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82801I_SATA_1, 230 0, 231 "Intel 82801I Serial ATA Controller (ICH9)", 232 piixsata_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82801I_SATA_2, 235 0, 236 "Intel 82801I Serial ATA Controller (ICH9)", 237 piixsata_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82801I_SATA_3, 240 0, 241 "Intel 82801I Serial ATA Controller (ICH9)", 242 piixsata_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_82801I_SATA_4, 245 0, 246 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 247 piixsata_chip_map, 248 }, 249 { PCI_PRODUCT_INTEL_82801I_SATA_5, 250 0, 251 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 252 piixsata_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82801I_SATA_6, 255 0, 256 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 257 piixsata_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_82801I_SATA_7, 260 0, 261 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 262 piixsata_chip_map, 263 }, 264 { PCI_PRODUCT_INTEL_63XXESB_SATA, 265 0, 266 "Intel 631xESB/632xESB Serial ATA Controller", 267 piixsata_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x1, 270 0, 271 "Intel ICH10 Serial ATA 2 Controller 2x1", 272 piixsata_chip_map, 273 }, 274 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x2, 275 0, 276 "Intel ICH10 Serial ATA 2 Controller 2x2", 277 piixsata_chip_map, 278 }, 279 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x1, 280 0, 281 "Intel ICH10 Serial ATA 2 Controller 4x1", 282 piixsata_chip_map, 283 }, 284 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x2, 285 0, 286 "Intel ICH10 Serial ATA 2 Controller 4x2", 287 piixsata_chip_map, 288 }, 289 { 290 PCI_PRODUCT_INTEL_82965PM_IDE, 291 0, 292 "Intel 82965PM IDE controller", 293 piixsata_chip_map, 294 }, 295 { 0, 296 0, 297 NULL, 298 NULL 299 } 300 }; 301 302 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), 303 piixide_match, piixide_attach, NULL, NULL); 304 305 static int 306 piixide_match(device_t parent, cfdata_t match, void *aux) 307 { 308 struct pci_attach_args *pa = aux; 309 310 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 311 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 312 return (2); 313 } 314 return (0); 315 } 316 317 static void 318 piixide_attach(device_t parent, device_t self, void *aux) 319 { 320 struct pci_attach_args *pa = aux; 321 struct pciide_softc *sc = device_private(self); 322 323 sc->sc_wdcdev.sc_atac.atac_dev = self; 324 325 pciide_common_attach(sc, pa, 326 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 327 328 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 329 aprint_error_dev(self, "couldn't establish power handler\n"); 330 } 331 332 static bool 333 piixide_resume(device_t dv PMF_FN_ARGS) 334 { 335 struct pciide_softc *sc = device_private(dv); 336 337 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 338 sc->sc_pm_reg[0]); 339 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 340 sc->sc_pm_reg[1]); 341 342 return true; 343 } 344 345 static bool 346 piixide_suspend(device_t dv PMF_FN_ARGS) 347 { 348 struct pciide_softc *sc = device_private(dv); 349 350 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 351 PIIX_IDETIM); 352 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 353 PIIX_UDMAREG); 354 355 return true; 356 } 357 358 static void 359 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 360 { 361 struct pciide_channel *cp; 362 int channel; 363 u_int32_t idetim; 364 bus_size_t cmdsize, ctlsize; 365 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 366 367 if (pciide_chipen(sc, pa) == 0) 368 return; 369 370 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 371 "bus-master DMA support present"); 372 pciide_mapreg_dma(sc, pa); 373 aprint_verbose("\n"); 374 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 375 if (sc->sc_dma_ok) { 376 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 377 sc->sc_wdcdev.irqack = pciide_irqack; 378 /* Do all revisions require DMA alignment workaround? */ 379 sc->sc_wdcdev.dma_init = piix_dma_init; 380 switch(sc->sc_pp->ide_product) { 381 case PCI_PRODUCT_INTEL_82371AB_IDE: 382 case PCI_PRODUCT_INTEL_82440MX_IDE: 383 case PCI_PRODUCT_INTEL_82801AA_IDE: 384 case PCI_PRODUCT_INTEL_82801AB_IDE: 385 case PCI_PRODUCT_INTEL_82801BA_IDE: 386 case PCI_PRODUCT_INTEL_82801BAM_IDE: 387 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 388 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 389 case PCI_PRODUCT_INTEL_82801DB_IDE: 390 case PCI_PRODUCT_INTEL_82801DBM_IDE: 391 case PCI_PRODUCT_INTEL_82801EB_IDE: 392 case PCI_PRODUCT_INTEL_6300ESB_IDE: 393 case PCI_PRODUCT_INTEL_82801FB_IDE: 394 case PCI_PRODUCT_INTEL_82801G_IDE: 395 case PCI_PRODUCT_INTEL_82801HBM_IDE: 396 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 397 } 398 } 399 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 400 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 401 switch(sc->sc_pp->ide_product) { 402 case PCI_PRODUCT_INTEL_82801AA_IDE: 403 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 404 break; 405 case PCI_PRODUCT_INTEL_82801BA_IDE: 406 case PCI_PRODUCT_INTEL_82801BAM_IDE: 407 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 408 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 409 case PCI_PRODUCT_INTEL_82801DB_IDE: 410 case PCI_PRODUCT_INTEL_82801DBM_IDE: 411 case PCI_PRODUCT_INTEL_82801EB_IDE: 412 case PCI_PRODUCT_INTEL_6300ESB_IDE: 413 case PCI_PRODUCT_INTEL_82801FB_IDE: 414 case PCI_PRODUCT_INTEL_82801G_IDE: 415 case PCI_PRODUCT_INTEL_82801HBM_IDE: 416 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 417 break; 418 default: 419 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 420 } 421 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 422 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 423 else 424 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 425 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 426 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 427 428 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 429 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 430 DEBUG_PROBE); 431 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 432 ATADEBUG_PRINT((", sidetim=0x%x", 433 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 434 DEBUG_PROBE); 435 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 436 ATADEBUG_PRINT((", udamreg 0x%x", 437 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 438 DEBUG_PROBE); 439 } 440 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 441 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 442 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 443 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 444 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 445 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 446 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 447 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 448 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 449 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 450 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 451 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 452 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 453 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 454 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 455 DEBUG_PROBE); 456 } 457 458 } 459 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 460 461 wdc_allocate_regs(&sc->sc_wdcdev); 462 463 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 464 channel++) { 465 cp = &sc->pciide_channels[channel]; 466 if (pciide_chansetup(sc, channel, interface) == 0) 467 continue; 468 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 469 if ((PIIX_IDETIM_READ(idetim, channel) & 470 PIIX_IDETIM_IDE) == 0) { 471 #if 1 472 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 473 "%s channel ignored (disabled)\n", cp->name); 474 cp->ata_channel.ch_flags |= ATACH_DISABLED; 475 continue; 476 #else 477 pcireg_t interface; 478 479 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 480 channel); 481 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 482 idetim); 483 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 484 sc->sc_tag, PCI_CLASS_REG)); 485 aprint_normal("channel %d idetim=%08x interface=%02x\n", 486 channel, idetim, interface); 487 #endif 488 } 489 pciide_mapchan(pa, cp, interface, 490 &cmdsize, &ctlsize, pciide_pci_intr); 491 } 492 493 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 494 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 495 DEBUG_PROBE); 496 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 497 ATADEBUG_PRINT((", sidetim=0x%x", 498 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 499 DEBUG_PROBE); 500 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 501 ATADEBUG_PRINT((", udamreg 0x%x", 502 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 503 DEBUG_PROBE); 504 } 505 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 506 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 507 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 508 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 509 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 510 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 511 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 512 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 513 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 514 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 515 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 516 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 517 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 518 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 519 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 520 DEBUG_PROBE); 521 } 522 } 523 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 524 } 525 526 static void 527 piix_setup_channel(struct ata_channel *chp) 528 { 529 u_int8_t mode[2], drive; 530 u_int32_t oidetim, idetim, idedma_ctl; 531 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 532 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 533 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 534 535 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 536 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 537 idedma_ctl = 0; 538 539 /* set up new idetim: Enable IDE registers decode */ 540 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 541 chp->ch_channel); 542 543 /* setup DMA */ 544 pciide_channel_dma_setup(cp); 545 546 /* 547 * Here we have to mess up with drives mode: PIIX can't have 548 * different timings for master and slave drives. 549 * We need to find the best combination. 550 */ 551 552 /* If both drives supports DMA, take the lower mode */ 553 if ((drvp[0].drive_flags & DRIVE_DMA) && 554 (drvp[1].drive_flags & DRIVE_DMA)) { 555 mode[0] = mode[1] = 556 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 557 drvp[0].DMA_mode = mode[0]; 558 drvp[1].DMA_mode = mode[1]; 559 goto ok; 560 } 561 /* 562 * If only one drive supports DMA, use its mode, and 563 * put the other one in PIO mode 0 if mode not compatible 564 */ 565 if (drvp[0].drive_flags & DRIVE_DMA) { 566 mode[0] = drvp[0].DMA_mode; 567 mode[1] = drvp[1].PIO_mode; 568 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 569 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 570 mode[1] = drvp[1].PIO_mode = 0; 571 goto ok; 572 } 573 if (drvp[1].drive_flags & DRIVE_DMA) { 574 mode[1] = drvp[1].DMA_mode; 575 mode[0] = drvp[0].PIO_mode; 576 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 577 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 578 mode[0] = drvp[0].PIO_mode = 0; 579 goto ok; 580 } 581 /* 582 * If both drives are not DMA, takes the lower mode, unless 583 * one of them is PIO mode < 2 584 */ 585 if (drvp[0].PIO_mode < 2) { 586 mode[0] = drvp[0].PIO_mode = 0; 587 mode[1] = drvp[1].PIO_mode; 588 } else if (drvp[1].PIO_mode < 2) { 589 mode[1] = drvp[1].PIO_mode = 0; 590 mode[0] = drvp[0].PIO_mode; 591 } else { 592 mode[0] = mode[1] = 593 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 594 drvp[0].PIO_mode = mode[0]; 595 drvp[1].PIO_mode = mode[1]; 596 } 597 ok: /* The modes are setup */ 598 for (drive = 0; drive < 2; drive++) { 599 if (drvp[drive].drive_flags & DRIVE_DMA) { 600 idetim |= piix_setup_idetim_timings( 601 mode[drive], 1, chp->ch_channel); 602 goto end; 603 } 604 } 605 /* If we are there, none of the drives are DMA */ 606 if (mode[0] >= 2) 607 idetim |= piix_setup_idetim_timings( 608 mode[0], 0, chp->ch_channel); 609 else 610 idetim |= piix_setup_idetim_timings( 611 mode[1], 0, chp->ch_channel); 612 end: /* 613 * timing mode is now set up in the controller. Enable 614 * it per-drive 615 */ 616 for (drive = 0; drive < 2; drive++) { 617 /* If no drive, skip */ 618 if ((drvp[drive].drive_flags & DRIVE) == 0) 619 continue; 620 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 621 if (drvp[drive].drive_flags & DRIVE_DMA) 622 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 623 } 624 if (idedma_ctl != 0) { 625 /* Add software bits in status register */ 626 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 627 idedma_ctl); 628 } 629 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 630 } 631 632 static void 633 piix3_4_setup_channel(struct ata_channel *chp) 634 { 635 struct ata_drive_datas *drvp; 636 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 637 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 638 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 639 struct wdc_softc *wdc = &sc->sc_wdcdev; 640 int drive, s; 641 int channel = chp->ch_channel; 642 643 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 644 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 645 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 646 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 647 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 648 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 649 PIIX_SIDETIM_RTC_MASK(channel)); 650 idedma_ctl = 0; 651 652 /* set up new idetim: Enable IDE registers decode */ 653 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 654 655 /* setup DMA if needed */ 656 pciide_channel_dma_setup(cp); 657 658 for (drive = 0; drive < 2; drive++) { 659 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 660 PIIX_UDMATIM_SET(0x3, channel, drive)); 661 drvp = &chp->ch_drive[drive]; 662 /* If no drive, skip */ 663 if ((drvp->drive_flags & DRIVE) == 0) 664 continue; 665 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 666 (drvp->drive_flags & DRIVE_UDMA) == 0)) 667 goto pio; 668 669 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 670 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 671 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 672 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 673 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 674 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 675 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 676 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 677 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 678 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 679 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 680 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 681 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 682 ideconf |= PIIX_CONFIG_PINGPONG; 683 } 684 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 685 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 686 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 687 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 688 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 689 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 690 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 691 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 692 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 693 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 694 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 695 /* setup Ultra/100 */ 696 if (drvp->UDMA_mode > 2 && 697 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 698 drvp->UDMA_mode = 2; 699 if (drvp->UDMA_mode > 4) { 700 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 701 } else { 702 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 703 if (drvp->UDMA_mode > 2) { 704 ideconf |= PIIX_CONFIG_UDMA66(channel, 705 drive); 706 } else { 707 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 708 drive); 709 } 710 } 711 } 712 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 713 /* setup Ultra/66 */ 714 if (drvp->UDMA_mode > 2 && 715 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 716 drvp->UDMA_mode = 2; 717 if (drvp->UDMA_mode > 2) 718 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 719 else 720 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 721 } 722 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 723 (drvp->drive_flags & DRIVE_UDMA)) { 724 /* use Ultra/DMA */ 725 s = splbio(); 726 drvp->drive_flags &= ~DRIVE_DMA; 727 splx(s); 728 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 729 udmareg |= PIIX_UDMATIM_SET( 730 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 731 } else { 732 /* use Multiword DMA */ 733 s = splbio(); 734 drvp->drive_flags &= ~DRIVE_UDMA; 735 splx(s); 736 if (drive == 0) { 737 idetim |= piix_setup_idetim_timings( 738 drvp->DMA_mode, 1, channel); 739 } else { 740 sidetim |= piix_setup_sidetim_timings( 741 drvp->DMA_mode, 1, channel); 742 idetim =PIIX_IDETIM_SET(idetim, 743 PIIX_IDETIM_SITRE, channel); 744 } 745 } 746 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 747 748 pio: /* use PIO mode */ 749 idetim |= piix_setup_idetim_drvs(drvp); 750 if (drive == 0) { 751 idetim |= piix_setup_idetim_timings( 752 drvp->PIO_mode, 0, channel); 753 } else { 754 sidetim |= piix_setup_sidetim_timings( 755 drvp->PIO_mode, 0, channel); 756 idetim =PIIX_IDETIM_SET(idetim, 757 PIIX_IDETIM_SITRE, channel); 758 } 759 } 760 if (idedma_ctl != 0) { 761 /* Add software bits in status register */ 762 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 763 idedma_ctl); 764 } 765 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 766 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 767 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 768 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 769 } 770 771 772 /* setup ISP and RTC fields, based on mode */ 773 static u_int32_t 774 piix_setup_idetim_timings(mode, dma, channel) 775 u_int8_t mode; 776 u_int8_t dma; 777 u_int8_t channel; 778 { 779 780 if (dma) 781 return PIIX_IDETIM_SET(0, 782 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 783 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 784 channel); 785 else 786 return PIIX_IDETIM_SET(0, 787 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 788 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 789 channel); 790 } 791 792 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 793 static u_int32_t 794 piix_setup_idetim_drvs(drvp) 795 struct ata_drive_datas *drvp; 796 { 797 u_int32_t ret = 0; 798 struct ata_channel *chp = drvp->chnl_softc; 799 u_int8_t channel = chp->ch_channel; 800 u_int8_t drive = drvp->drive; 801 802 /* 803 * If drive is using UDMA, timings setups are independent 804 * So just check DMA and PIO here. 805 */ 806 if (drvp->drive_flags & DRIVE_DMA) { 807 /* if mode = DMA mode 0, use compatible timings */ 808 if ((drvp->drive_flags & DRIVE_DMA) && 809 drvp->DMA_mode == 0) { 810 drvp->PIO_mode = 0; 811 return ret; 812 } 813 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 814 /* 815 * PIO and DMA timings are the same, use fast timings for PIO 816 * too, else use compat timings. 817 */ 818 if ((piix_isp_pio[drvp->PIO_mode] != 819 piix_isp_dma[drvp->DMA_mode]) || 820 (piix_rtc_pio[drvp->PIO_mode] != 821 piix_rtc_dma[drvp->DMA_mode])) 822 drvp->PIO_mode = 0; 823 /* if PIO mode <= 2, use compat timings for PIO */ 824 if (drvp->PIO_mode <= 2) { 825 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 826 channel); 827 return ret; 828 } 829 } 830 831 /* 832 * Now setup PIO modes. If mode < 2, use compat timings. 833 * Else enable fast timings. Enable IORDY and prefetch/post 834 * if PIO mode >= 3. 835 */ 836 837 if (drvp->PIO_mode < 2) 838 return ret; 839 840 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 841 if (drvp->PIO_mode >= 3) { 842 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 843 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 844 } 845 return ret; 846 } 847 848 /* setup values in SIDETIM registers, based on mode */ 849 static u_int32_t 850 piix_setup_sidetim_timings(mode, dma, channel) 851 u_int8_t mode; 852 u_int8_t dma; 853 u_int8_t channel; 854 { 855 if (dma) 856 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 857 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 858 else 859 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 860 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 861 } 862 863 static void 864 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 865 { 866 struct pciide_channel *cp; 867 bus_size_t cmdsize, ctlsize; 868 pcireg_t interface, cmdsts; 869 int channel; 870 871 if (pciide_chipen(sc, pa) == 0) 872 return; 873 874 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 875 "bus-master DMA support present"); 876 pciide_mapreg_dma(sc, pa); 877 aprint_verbose("\n"); 878 879 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 880 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 881 if (sc->sc_dma_ok) { 882 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 883 sc->sc_wdcdev.irqack = pciide_irqack; 884 /* Do all revisions require DMA alignment workaround? */ 885 sc->sc_wdcdev.dma_init = piix_dma_init; 886 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 887 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 888 } 889 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 890 891 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 892 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 893 894 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 895 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 896 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 897 898 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 899 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 900 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 901 902 interface = PCI_INTERFACE(pa->pa_class); 903 904 wdc_allocate_regs(&sc->sc_wdcdev); 905 906 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 907 channel++) { 908 cp = &sc->pciide_channels[channel]; 909 if (pciide_chansetup(sc, channel, interface) == 0) 910 continue; 911 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 912 pciide_pci_intr); 913 } 914 } 915 916 static int 917 piix_dma_init(void *v, int channel, int drive, void *databuf, 918 size_t datalen, int flags) 919 { 920 921 /* use PIO for unaligned transfer */ 922 if (((uintptr_t)databuf) & 0x1) 923 return EINVAL; 924 925 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 926 } 927
Indexes created Fri Sep 26 20:09:58 GMT 2025