piixide.c revision 1.51
1 /* $NetBSD: piixide.c,v 1.51 2009/10/19 18:41:16 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.51 2009/10/19 18:41:16 bouyer Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_piix_reg.h> 38 39 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 40 static void piix_setup_channel(struct ata_channel *); 41 static void piix3_4_setup_channel(struct ata_channel *); 42 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 43 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 44 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 46 static int piix_dma_init(void *, int, int, void *, size_t, int); 47 48 static bool piixide_resume(device_t PMF_FN_PROTO); 49 static bool piixide_suspend(device_t PMF_FN_PROTO); 50 static int piixide_match(device_t, cfdata_t, void *); 51 static void piixide_attach(device_t, device_t, void *); 52 53 static const struct pciide_product_desc pciide_intel_products[] = { 54 { PCI_PRODUCT_INTEL_82092AA, 55 0, 56 "Intel 82092AA IDE controller", 57 default_chip_map, 58 }, 59 { PCI_PRODUCT_INTEL_82371FB_IDE, 60 0, 61 "Intel 82371FB IDE controller (PIIX)", 62 piix_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371SB_IDE, 65 0, 66 "Intel 82371SB IDE Interface (PIIX3)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371AB_IDE, 70 0, 71 "Intel 82371AB IDE controller (PIIX4)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82440MX_IDE, 75 0, 76 "Intel 82440MX IDE controller", 77 piix_chip_map 78 }, 79 { PCI_PRODUCT_INTEL_82801AA_IDE, 80 0, 81 "Intel 82801AA IDE Controller (ICH)", 82 piix_chip_map, 83 }, 84 { PCI_PRODUCT_INTEL_82801AB_IDE, 85 0, 86 "Intel 82801AB IDE Controller (ICH0)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801BA_IDE, 90 0, 91 "Intel 82801BA IDE Controller (ICH2)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BAM_IDE, 95 0, 96 "Intel 82801BAM IDE Controller (ICH2-M)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 100 0, 101 "Intel 82801CA IDE Controller (ICH3)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801DB_IDE, 110 0, 111 "Intel 82801DB IDE Controller (ICH4)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DBM_IDE, 115 0, 116 "Intel 82801DBM IDE Controller (ICH4-M)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801EB_IDE, 120 0, 121 "Intel 82801EB IDE Controller (ICH5)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_SATA, 125 0, 126 "Intel 82801EB Serial ATA Controller", 127 piixsata_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801ER_SATA, 130 0, 131 "Intel 82801ER Serial ATA/Raid Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_6300ESB_IDE, 135 0, 136 "Intel 6300ESB IDE Controller (ICH5)", 137 piix_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_SATA, 140 0, 141 "Intel 6300ESB Serial ATA Controller", 142 piixsata_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_6300ESB_RAID, 145 0, 146 "Intel 6300ESB Serial ATA/RAID Controller", 147 piixsata_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_82801FB_IDE, 150 0, 151 "Intel 82801FB IDE Controller (ICH6)", 152 piix_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FB_SATA, 155 0, 156 "Intel 82801FB Serial ATA/Raid Controller", 157 piixsata_chip_map, 158 }, 159 { PCI_PRODUCT_INTEL_82801FR_SATA, 160 0, 161 "Intel 82801FR Serial ATA/Raid Controller", 162 piixsata_chip_map, 163 }, 164 { PCI_PRODUCT_INTEL_82801FBM_SATA, 165 0, 166 "Intel 82801FBM Serial ATA Controller (ICH6)", 167 piixsata_chip_map, 168 }, 169 { PCI_PRODUCT_INTEL_82801G_IDE, 170 0, 171 "Intel 82801GB/GR IDE Controller (ICH7)", 172 piix_chip_map, 173 }, 174 { PCI_PRODUCT_INTEL_82801G_SATA, 175 0, 176 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 177 piixsata_chip_map, 178 }, 179 { PCI_PRODUCT_INTEL_82801GBM_SATA, 180 0, 181 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 182 piixsata_chip_map, 183 }, 184 { PCI_PRODUCT_INTEL_82801H_SATA_1, 185 0, 186 "Intel 82801H Serial ATA Controller (ICH8)", 187 piixsata_chip_map, 188 }, 189 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 190 0, 191 "Intel 82801H Serial ATA RAID Controller (ICH8)", 192 piixsata_chip_map, 193 }, 194 { PCI_PRODUCT_INTEL_82801H_SATA_2, 195 0, 196 "Intel 82801H Serial ATA Controller (ICH8)", 197 piixsata_chip_map, 198 }, 199 { PCI_PRODUCT_INTEL_82801HBM_IDE, 200 0, 201 "Intel 82801HBM IDE Controller (ICH8M)", 202 piix_chip_map, 203 }, 204 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 205 0, 206 "Intel 82801HBM Serial ATA Controller (ICH8M)", 207 piixsata_chip_map, 208 }, 209 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 210 0, 211 "Intel 82801HBM Serial ATA Controller (ICH8M)", 212 piixsata_chip_map, 213 }, 214 { PCI_PRODUCT_INTEL_82801HEM_SATA, 215 0, 216 "Intel 82801HEM Serial ATA Controller (ICH8M)", 217 piixsata_chip_map, 218 }, 219 { PCI_PRODUCT_INTEL_63XXESB_IDE, 220 0, 221 "Intel 631xESB/632xESB IDE Controller", 222 piix_chip_map, 223 }, 224 { PCI_PRODUCT_INTEL_82801I_SATA_1, 225 0, 226 "Intel 82801I Serial ATA Controller (ICH9)", 227 piixsata_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82801I_SATA_2, 230 0, 231 "Intel 82801I Serial ATA Controller (ICH9)", 232 piixsata_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82801I_SATA_3, 235 0, 236 "Intel 82801I Serial ATA Controller (ICH9)", 237 piixsata_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82801I_SATA_4, 240 0, 241 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 242 piixsata_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_82801I_SATA_5, 245 0, 246 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 247 piixsata_chip_map, 248 }, 249 { PCI_PRODUCT_INTEL_82801I_SATA_6, 250 0, 251 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 252 piixsata_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82801I_SATA_7, 255 0, 256 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 257 piixsata_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_63XXESB_SATA, 260 0, 261 "Intel 631xESB/632xESB Serial ATA Controller", 262 piixsata_chip_map, 263 }, 264 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x1, 265 0, 266 "Intel ICH10 Serial ATA 2 Controller 2x1", 267 piixsata_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_ICH10_SATA2_2x2, 270 0, 271 "Intel ICH10 Serial ATA 2 Controller 2x2", 272 piixsata_chip_map, 273 }, 274 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x1, 275 0, 276 "Intel ICH10 Serial ATA 2 Controller 4x1", 277 piixsata_chip_map, 278 }, 279 { PCI_PRODUCT_INTEL_ICH10_SATA2_4x2, 280 0, 281 "Intel ICH10 Serial ATA 2 Controller 4x2", 282 piixsata_chip_map, 283 }, 284 { 285 PCI_PRODUCT_INTEL_82965PM_IDE, 286 0, 287 "Intel 82965PM IDE controller", 288 piixsata_chip_map, 289 }, 290 { 0, 291 0, 292 NULL, 293 NULL 294 } 295 }; 296 297 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), 298 piixide_match, piixide_attach, NULL, NULL); 299 300 static int 301 piixide_match(device_t parent, cfdata_t match, void *aux) 302 { 303 struct pci_attach_args *pa = aux; 304 305 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 306 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 307 return (2); 308 } 309 return (0); 310 } 311 312 static void 313 piixide_attach(device_t parent, device_t self, void *aux) 314 { 315 struct pci_attach_args *pa = aux; 316 struct pciide_softc *sc = device_private(self); 317 318 sc->sc_wdcdev.sc_atac.atac_dev = self; 319 320 pciide_common_attach(sc, pa, 321 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 322 323 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 324 aprint_error_dev(self, "couldn't establish power handler\n"); 325 } 326 327 static bool 328 piixide_resume(device_t dv PMF_FN_ARGS) 329 { 330 struct pciide_softc *sc = device_private(dv); 331 332 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 333 sc->sc_pm_reg[0]); 334 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 335 sc->sc_pm_reg[1]); 336 337 return true; 338 } 339 340 static bool 341 piixide_suspend(device_t dv PMF_FN_ARGS) 342 { 343 struct pciide_softc *sc = device_private(dv); 344 345 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 346 PIIX_IDETIM); 347 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 348 PIIX_UDMAREG); 349 350 return true; 351 } 352 353 static void 354 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 355 { 356 struct pciide_channel *cp; 357 int channel; 358 u_int32_t idetim; 359 bus_size_t cmdsize, ctlsize; 360 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 361 362 if (pciide_chipen(sc, pa) == 0) 363 return; 364 365 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 366 "bus-master DMA support present"); 367 pciide_mapreg_dma(sc, pa); 368 aprint_verbose("\n"); 369 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 370 if (sc->sc_dma_ok) { 371 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 372 sc->sc_wdcdev.irqack = pciide_irqack; 373 /* Do all revisions require DMA alignment workaround? */ 374 sc->sc_wdcdev.dma_init = piix_dma_init; 375 switch(sc->sc_pp->ide_product) { 376 case PCI_PRODUCT_INTEL_82371AB_IDE: 377 case PCI_PRODUCT_INTEL_82440MX_IDE: 378 case PCI_PRODUCT_INTEL_82801AA_IDE: 379 case PCI_PRODUCT_INTEL_82801AB_IDE: 380 case PCI_PRODUCT_INTEL_82801BA_IDE: 381 case PCI_PRODUCT_INTEL_82801BAM_IDE: 382 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 383 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 384 case PCI_PRODUCT_INTEL_82801DB_IDE: 385 case PCI_PRODUCT_INTEL_82801DBM_IDE: 386 case PCI_PRODUCT_INTEL_82801EB_IDE: 387 case PCI_PRODUCT_INTEL_6300ESB_IDE: 388 case PCI_PRODUCT_INTEL_82801FB_IDE: 389 case PCI_PRODUCT_INTEL_82801G_IDE: 390 case PCI_PRODUCT_INTEL_82801HBM_IDE: 391 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 392 } 393 } 394 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 395 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 396 switch(sc->sc_pp->ide_product) { 397 case PCI_PRODUCT_INTEL_82801AA_IDE: 398 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 399 break; 400 case PCI_PRODUCT_INTEL_82801BA_IDE: 401 case PCI_PRODUCT_INTEL_82801BAM_IDE: 402 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 403 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 404 case PCI_PRODUCT_INTEL_82801DB_IDE: 405 case PCI_PRODUCT_INTEL_82801DBM_IDE: 406 case PCI_PRODUCT_INTEL_82801EB_IDE: 407 case PCI_PRODUCT_INTEL_6300ESB_IDE: 408 case PCI_PRODUCT_INTEL_82801FB_IDE: 409 case PCI_PRODUCT_INTEL_82801G_IDE: 410 case PCI_PRODUCT_INTEL_82801HBM_IDE: 411 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 412 break; 413 default: 414 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 415 } 416 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 417 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 418 else 419 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 420 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 421 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 422 423 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 424 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 425 DEBUG_PROBE); 426 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 427 ATADEBUG_PRINT((", sidetim=0x%x", 428 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 429 DEBUG_PROBE); 430 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 431 ATADEBUG_PRINT((", udamreg 0x%x", 432 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 433 DEBUG_PROBE); 434 } 435 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 436 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 437 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 438 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 439 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 440 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 441 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 442 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 443 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 444 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 445 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 446 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 447 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 448 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 449 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 450 DEBUG_PROBE); 451 } 452 453 } 454 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 455 456 wdc_allocate_regs(&sc->sc_wdcdev); 457 458 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 459 channel++) { 460 cp = &sc->pciide_channels[channel]; 461 if (pciide_chansetup(sc, channel, interface) == 0) 462 continue; 463 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 464 if ((PIIX_IDETIM_READ(idetim, channel) & 465 PIIX_IDETIM_IDE) == 0) { 466 #if 1 467 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 468 "%s channel ignored (disabled)\n", cp->name); 469 cp->ata_channel.ch_flags |= ATACH_DISABLED; 470 continue; 471 #else 472 pcireg_t interface; 473 474 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 475 channel); 476 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 477 idetim); 478 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 479 sc->sc_tag, PCI_CLASS_REG)); 480 aprint_normal("channel %d idetim=%08x interface=%02x\n", 481 channel, idetim, interface); 482 #endif 483 } 484 pciide_mapchan(pa, cp, interface, 485 &cmdsize, &ctlsize, pciide_pci_intr); 486 } 487 488 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 489 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 490 DEBUG_PROBE); 491 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 492 ATADEBUG_PRINT((", sidetim=0x%x", 493 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 494 DEBUG_PROBE); 495 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 496 ATADEBUG_PRINT((", udamreg 0x%x", 497 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 498 DEBUG_PROBE); 499 } 500 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 501 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 502 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 503 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 504 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 505 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 506 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 507 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 508 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 509 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 510 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 511 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 512 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 513 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 514 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 515 DEBUG_PROBE); 516 } 517 } 518 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 519 } 520 521 static void 522 piix_setup_channel(struct ata_channel *chp) 523 { 524 u_int8_t mode[2], drive; 525 u_int32_t oidetim, idetim, idedma_ctl; 526 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 527 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 528 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 529 530 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 531 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 532 idedma_ctl = 0; 533 534 /* set up new idetim: Enable IDE registers decode */ 535 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 536 chp->ch_channel); 537 538 /* setup DMA */ 539 pciide_channel_dma_setup(cp); 540 541 /* 542 * Here we have to mess up with drives mode: PIIX can't have 543 * different timings for master and slave drives. 544 * We need to find the best combination. 545 */ 546 547 /* If both drives supports DMA, take the lower mode */ 548 if ((drvp[0].drive_flags & DRIVE_DMA) && 549 (drvp[1].drive_flags & DRIVE_DMA)) { 550 mode[0] = mode[1] = 551 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 552 drvp[0].DMA_mode = mode[0]; 553 drvp[1].DMA_mode = mode[1]; 554 goto ok; 555 } 556 /* 557 * If only one drive supports DMA, use its mode, and 558 * put the other one in PIO mode 0 if mode not compatible 559 */ 560 if (drvp[0].drive_flags & DRIVE_DMA) { 561 mode[0] = drvp[0].DMA_mode; 562 mode[1] = drvp[1].PIO_mode; 563 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 564 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 565 mode[1] = drvp[1].PIO_mode = 0; 566 goto ok; 567 } 568 if (drvp[1].drive_flags & DRIVE_DMA) { 569 mode[1] = drvp[1].DMA_mode; 570 mode[0] = drvp[0].PIO_mode; 571 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 572 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 573 mode[0] = drvp[0].PIO_mode = 0; 574 goto ok; 575 } 576 /* 577 * If both drives are not DMA, takes the lower mode, unless 578 * one of them is PIO mode < 2 579 */ 580 if (drvp[0].PIO_mode < 2) { 581 mode[0] = drvp[0].PIO_mode = 0; 582 mode[1] = drvp[1].PIO_mode; 583 } else if (drvp[1].PIO_mode < 2) { 584 mode[1] = drvp[1].PIO_mode = 0; 585 mode[0] = drvp[0].PIO_mode; 586 } else { 587 mode[0] = mode[1] = 588 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 589 drvp[0].PIO_mode = mode[0]; 590 drvp[1].PIO_mode = mode[1]; 591 } 592 ok: /* The modes are setup */ 593 for (drive = 0; drive < 2; drive++) { 594 if (drvp[drive].drive_flags & DRIVE_DMA) { 595 idetim |= piix_setup_idetim_timings( 596 mode[drive], 1, chp->ch_channel); 597 goto end; 598 } 599 } 600 /* If we are there, none of the drives are DMA */ 601 if (mode[0] >= 2) 602 idetim |= piix_setup_idetim_timings( 603 mode[0], 0, chp->ch_channel); 604 else 605 idetim |= piix_setup_idetim_timings( 606 mode[1], 0, chp->ch_channel); 607 end: /* 608 * timing mode is now set up in the controller. Enable 609 * it per-drive 610 */ 611 for (drive = 0; drive < 2; drive++) { 612 /* If no drive, skip */ 613 if ((drvp[drive].drive_flags & DRIVE) == 0) 614 continue; 615 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 616 if (drvp[drive].drive_flags & DRIVE_DMA) 617 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 618 } 619 if (idedma_ctl != 0) { 620 /* Add software bits in status register */ 621 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 622 idedma_ctl); 623 } 624 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 625 } 626 627 static void 628 piix3_4_setup_channel(struct ata_channel *chp) 629 { 630 struct ata_drive_datas *drvp; 631 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 632 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 633 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 634 struct wdc_softc *wdc = &sc->sc_wdcdev; 635 int drive, s; 636 int channel = chp->ch_channel; 637 638 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 639 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 640 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 641 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 642 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 643 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 644 PIIX_SIDETIM_RTC_MASK(channel)); 645 idedma_ctl = 0; 646 647 /* set up new idetim: Enable IDE registers decode */ 648 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 649 650 /* setup DMA if needed */ 651 pciide_channel_dma_setup(cp); 652 653 for (drive = 0; drive < 2; drive++) { 654 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 655 PIIX_UDMATIM_SET(0x3, channel, drive)); 656 drvp = &chp->ch_drive[drive]; 657 /* If no drive, skip */ 658 if ((drvp->drive_flags & DRIVE) == 0) 659 continue; 660 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 661 (drvp->drive_flags & DRIVE_UDMA) == 0)) 662 goto pio; 663 664 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 665 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 666 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 667 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 668 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 669 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 670 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 671 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 672 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 673 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 674 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 675 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 676 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 677 ideconf |= PIIX_CONFIG_PINGPONG; 678 } 679 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 680 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 681 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 682 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 683 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 684 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 685 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 686 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 687 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 688 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 689 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 690 /* setup Ultra/100 */ 691 if (drvp->UDMA_mode > 2 && 692 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 693 drvp->UDMA_mode = 2; 694 if (drvp->UDMA_mode > 4) { 695 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 696 } else { 697 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 698 if (drvp->UDMA_mode > 2) { 699 ideconf |= PIIX_CONFIG_UDMA66(channel, 700 drive); 701 } else { 702 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 703 drive); 704 } 705 } 706 } 707 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 708 /* setup Ultra/66 */ 709 if (drvp->UDMA_mode > 2 && 710 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 711 drvp->UDMA_mode = 2; 712 if (drvp->UDMA_mode > 2) 713 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 714 else 715 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 716 } 717 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 718 (drvp->drive_flags & DRIVE_UDMA)) { 719 /* use Ultra/DMA */ 720 s = splbio(); 721 drvp->drive_flags &= ~DRIVE_DMA; 722 splx(s); 723 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 724 udmareg |= PIIX_UDMATIM_SET( 725 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 726 } else { 727 /* use Multiword DMA */ 728 s = splbio(); 729 drvp->drive_flags &= ~DRIVE_UDMA; 730 splx(s); 731 if (drive == 0) { 732 idetim |= piix_setup_idetim_timings( 733 drvp->DMA_mode, 1, channel); 734 } else { 735 sidetim |= piix_setup_sidetim_timings( 736 drvp->DMA_mode, 1, channel); 737 idetim =PIIX_IDETIM_SET(idetim, 738 PIIX_IDETIM_SITRE, channel); 739 } 740 } 741 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 742 743 pio: /* use PIO mode */ 744 idetim |= piix_setup_idetim_drvs(drvp); 745 if (drive == 0) { 746 idetim |= piix_setup_idetim_timings( 747 drvp->PIO_mode, 0, channel); 748 } else { 749 sidetim |= piix_setup_sidetim_timings( 750 drvp->PIO_mode, 0, channel); 751 idetim =PIIX_IDETIM_SET(idetim, 752 PIIX_IDETIM_SITRE, channel); 753 } 754 } 755 if (idedma_ctl != 0) { 756 /* Add software bits in status register */ 757 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 758 idedma_ctl); 759 } 760 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 761 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 762 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 763 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 764 } 765 766 767 /* setup ISP and RTC fields, based on mode */ 768 static u_int32_t 769 piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 770 { 771 772 if (dma) 773 return PIIX_IDETIM_SET(0, 774 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 775 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 776 channel); 777 else 778 return PIIX_IDETIM_SET(0, 779 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 780 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 781 channel); 782 } 783 784 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 785 static u_int32_t 786 piix_setup_idetim_drvs(struct ata_drive_datas *drvp) 787 { 788 u_int32_t ret = 0; 789 struct ata_channel *chp = drvp->chnl_softc; 790 u_int8_t channel = chp->ch_channel; 791 u_int8_t drive = drvp->drive; 792 793 /* 794 * If drive is using UDMA, timings setups are independent 795 * So just check DMA and PIO here. 796 */ 797 if (drvp->drive_flags & DRIVE_DMA) { 798 /* if mode = DMA mode 0, use compatible timings */ 799 if ((drvp->drive_flags & DRIVE_DMA) && 800 drvp->DMA_mode == 0) { 801 drvp->PIO_mode = 0; 802 return ret; 803 } 804 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 805 /* 806 * PIO and DMA timings are the same, use fast timings for PIO 807 * too, else use compat timings. 808 */ 809 if ((piix_isp_pio[drvp->PIO_mode] != 810 piix_isp_dma[drvp->DMA_mode]) || 811 (piix_rtc_pio[drvp->PIO_mode] != 812 piix_rtc_dma[drvp->DMA_mode])) 813 drvp->PIO_mode = 0; 814 /* if PIO mode <= 2, use compat timings for PIO */ 815 if (drvp->PIO_mode <= 2) { 816 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 817 channel); 818 return ret; 819 } 820 } 821 822 /* 823 * Now setup PIO modes. If mode < 2, use compat timings. 824 * Else enable fast timings. Enable IORDY and prefetch/post 825 * if PIO mode >= 3. 826 */ 827 828 if (drvp->PIO_mode < 2) 829 return ret; 830 831 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 832 if (drvp->PIO_mode >= 3) { 833 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 834 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 835 } 836 return ret; 837 } 838 839 /* setup values in SIDETIM registers, based on mode */ 840 static u_int32_t 841 piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 842 { 843 if (dma) 844 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 845 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 846 else 847 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 848 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 849 } 850 851 static void 852 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 853 { 854 struct pciide_channel *cp; 855 bus_size_t cmdsize, ctlsize; 856 pcireg_t interface, cmdsts; 857 int channel; 858 859 if (pciide_chipen(sc, pa) == 0) 860 return; 861 862 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 863 "bus-master DMA support present"); 864 pciide_mapreg_dma(sc, pa); 865 aprint_verbose("\n"); 866 867 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 868 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 869 if (sc->sc_dma_ok) { 870 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 871 sc->sc_wdcdev.irqack = pciide_irqack; 872 /* Do all revisions require DMA alignment workaround? */ 873 sc->sc_wdcdev.dma_init = piix_dma_init; 874 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 875 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 876 } 877 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 878 879 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 880 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 881 882 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 883 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 884 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 885 886 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 887 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 888 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 889 890 interface = PCI_INTERFACE(pa->pa_class); 891 892 wdc_allocate_regs(&sc->sc_wdcdev); 893 894 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 895 channel++) { 896 cp = &sc->pciide_channels[channel]; 897 if (pciide_chansetup(sc, channel, interface) == 0) 898 continue; 899 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 900 pciide_pci_intr); 901 } 902 } 903 904 static int 905 piix_dma_init(void *v, int channel, int drive, void *databuf, 906 size_t datalen, int flags) 907 { 908 909 /* use PIO for unaligned transfer */ 910 if (((uintptr_t)databuf) & 0x1) 911 return EINVAL; 912 913 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 914 } 915
Indexes created Fri Oct 17 09:09:57 GMT 2025