piixide.c revision 1.56.2.1
1 /* $NetBSD: piixide.c,v 1.56.2.1 2011/06/06 09:08:25 jruoho Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.56.2.1 2011/06/06 09:08:25 jruoho Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_piix_reg.h> 38 39 static void piix_chip_map(struct pciide_softc*, 40 const struct pci_attach_args *); 41 static void piix_setup_channel(struct ata_channel *); 42 static void piix3_4_setup_channel(struct ata_channel *); 43 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 44 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 45 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 46 static void piixsata_chip_map(struct pciide_softc*, 47 const struct pci_attach_args *); 48 static int piix_dma_init(void *, int, int, void *, size_t, int); 49 50 static bool piixide_resume(device_t, const pmf_qual_t *); 51 static bool piixide_suspend(device_t, const pmf_qual_t *); 52 static int piixide_match(device_t, cfdata_t, void *); 53 static void piixide_attach(device_t, device_t, void *); 54 55 static const struct pciide_product_desc pciide_intel_products[] = { 56 { PCI_PRODUCT_INTEL_82092AA, 57 0, 58 "Intel 82092AA IDE controller", 59 default_chip_map, 60 }, 61 { PCI_PRODUCT_INTEL_82371FB_IDE, 62 0, 63 "Intel 82371FB IDE controller (PIIX)", 64 piix_chip_map, 65 }, 66 { PCI_PRODUCT_INTEL_82371SB_IDE, 67 0, 68 "Intel 82371SB IDE Interface (PIIX3)", 69 piix_chip_map, 70 }, 71 { PCI_PRODUCT_INTEL_82371AB_IDE, 72 0, 73 "Intel 82371AB IDE controller (PIIX4)", 74 piix_chip_map, 75 }, 76 { PCI_PRODUCT_INTEL_82440MX_IDE, 77 0, 78 "Intel 82440MX IDE controller", 79 piix_chip_map 80 }, 81 { PCI_PRODUCT_INTEL_82801AA_IDE, 82 0, 83 "Intel 82801AA IDE Controller (ICH)", 84 piix_chip_map, 85 }, 86 { PCI_PRODUCT_INTEL_82801AB_IDE, 87 0, 88 "Intel 82801AB IDE Controller (ICH0)", 89 piix_chip_map, 90 }, 91 { PCI_PRODUCT_INTEL_82801BA_IDE, 92 0, 93 "Intel 82801BA IDE Controller (ICH2)", 94 piix_chip_map, 95 }, 96 { PCI_PRODUCT_INTEL_82801BAM_IDE, 97 0, 98 "Intel 82801BAM IDE Controller (ICH2-M)", 99 piix_chip_map, 100 }, 101 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 102 0, 103 "Intel 82801CA IDE Controller (ICH3)", 104 piix_chip_map, 105 }, 106 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 107 0, 108 "Intel 82801CA IDE Controller (ICH3)", 109 piix_chip_map, 110 }, 111 { PCI_PRODUCT_INTEL_82801DB_IDE, 112 0, 113 "Intel 82801DB IDE Controller (ICH4)", 114 piix_chip_map, 115 }, 116 { PCI_PRODUCT_INTEL_82801DBM_IDE, 117 0, 118 "Intel 82801DBM IDE Controller (ICH4-M)", 119 piix_chip_map, 120 }, 121 { PCI_PRODUCT_INTEL_82801EB_IDE, 122 0, 123 "Intel 82801EB IDE Controller (ICH5)", 124 piix_chip_map, 125 }, 126 { PCI_PRODUCT_INTEL_82801EB_SATA, 127 0, 128 "Intel 82801EB Serial ATA Controller", 129 piixsata_chip_map, 130 }, 131 { PCI_PRODUCT_INTEL_82801ER_SATA, 132 0, 133 "Intel 82801ER Serial ATA/Raid Controller", 134 piixsata_chip_map, 135 }, 136 { PCI_PRODUCT_INTEL_6300ESB_IDE, 137 0, 138 "Intel 6300ESB IDE Controller (ICH5)", 139 piix_chip_map, 140 }, 141 { PCI_PRODUCT_INTEL_6300ESB_SATA, 142 0, 143 "Intel 6300ESB Serial ATA Controller", 144 piixsata_chip_map, 145 }, 146 { PCI_PRODUCT_INTEL_6300ESB_RAID, 147 0, 148 "Intel 6300ESB Serial ATA/RAID Controller", 149 piixsata_chip_map, 150 }, 151 { PCI_PRODUCT_INTEL_82801FB_IDE, 152 0, 153 "Intel 82801FB IDE Controller (ICH6)", 154 piix_chip_map, 155 }, 156 { PCI_PRODUCT_INTEL_82801FB_SATA, 157 0, 158 "Intel 82801FB Serial ATA/Raid Controller", 159 piixsata_chip_map, 160 }, 161 { PCI_PRODUCT_INTEL_82801FR_SATA, 162 0, 163 "Intel 82801FR Serial ATA/Raid Controller", 164 piixsata_chip_map, 165 }, 166 { PCI_PRODUCT_INTEL_82801FBM_SATA, 167 0, 168 "Intel 82801FBM Serial ATA Controller (ICH6)", 169 piixsata_chip_map, 170 }, 171 { PCI_PRODUCT_INTEL_82801G_IDE, 172 0, 173 "Intel 82801GB/GR IDE Controller (ICH7)", 174 piix_chip_map, 175 }, 176 { PCI_PRODUCT_INTEL_82801G_SATA, 177 0, 178 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 179 piixsata_chip_map, 180 }, 181 { PCI_PRODUCT_INTEL_82801GBM_SATA, 182 0, 183 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 184 piixsata_chip_map, 185 }, 186 { PCI_PRODUCT_INTEL_82801H_SATA_1, 187 0, 188 "Intel 82801H Serial ATA Controller (ICH8)", 189 piixsata_chip_map, 190 }, 191 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 192 0, 193 "Intel 82801H Serial ATA RAID Controller (ICH8)", 194 piixsata_chip_map, 195 }, 196 { PCI_PRODUCT_INTEL_82801H_SATA_2, 197 0, 198 "Intel 82801H Serial ATA Controller (ICH8)", 199 piixsata_chip_map, 200 }, 201 { PCI_PRODUCT_INTEL_82801HBM_IDE, 202 0, 203 "Intel 82801HBM IDE Controller (ICH8M)", 204 piix_chip_map, 205 }, 206 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 207 0, 208 "Intel 82801HBM Serial ATA Controller (ICH8M)", 209 piixsata_chip_map, 210 }, 211 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 212 0, 213 "Intel 82801HBM Serial ATA Controller (ICH8M)", 214 piixsata_chip_map, 215 }, 216 { PCI_PRODUCT_INTEL_82801HEM_SATA, 217 0, 218 "Intel 82801HEM Serial ATA Controller (ICH8M)", 219 piixsata_chip_map, 220 }, 221 { PCI_PRODUCT_INTEL_63XXESB_IDE, 222 0, 223 "Intel 631xESB/632xESB IDE Controller", 224 piix_chip_map, 225 }, 226 { PCI_PRODUCT_INTEL_82801I_SATA_1, 227 0, 228 "Intel 82801I Serial ATA Controller (ICH9)", 229 piixsata_chip_map, 230 }, 231 { PCI_PRODUCT_INTEL_82801I_SATA_2, 232 0, 233 "Intel 82801I Serial ATA Controller (ICH9)", 234 piixsata_chip_map, 235 }, 236 { PCI_PRODUCT_INTEL_82801I_SATA_3, 237 0, 238 "Intel 82801I Serial ATA Controller (ICH9)", 239 piixsata_chip_map, 240 }, 241 { PCI_PRODUCT_INTEL_82801I_SATA_4, 242 0, 243 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 244 piixsata_chip_map, 245 }, 246 { PCI_PRODUCT_INTEL_82801I_SATA_5, 247 0, 248 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 249 piixsata_chip_map, 250 }, 251 { PCI_PRODUCT_INTEL_82801I_SATA_6, 252 0, 253 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 254 piixsata_chip_map, 255 }, 256 { PCI_PRODUCT_INTEL_82801I_SATA_7, 257 0, 258 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 259 piixsata_chip_map, 260 }, 261 { PCI_PRODUCT_INTEL_63XXESB_SATA, 262 0, 263 "Intel 631xESB/632xESB Serial ATA Controller", 264 piixsata_chip_map, 265 }, 266 { PCI_PRODUCT_INTEL_82801JD_SATA_IDE2, 267 0, 268 "Intel 82801JD Serial ATA Controller (ICH10)", 269 piixsata_chip_map, 270 }, 271 { PCI_PRODUCT_INTEL_82801JI_SATA_IDE2, 272 0, 273 "Intel 82801JI Serial ATA Controller (ICH10)", 274 piixsata_chip_map, 275 }, 276 { PCI_PRODUCT_INTEL_82801JD_SATA_IDE, 277 0, 278 "Intel 82801JD Serial ATA Controller (ICH10)", 279 piixsata_chip_map, 280 }, 281 { PCI_PRODUCT_INTEL_82801JI_SATA_IDE, 282 0, 283 "Intel 82801JI Serial ATA Controller (ICH10)", 284 piixsata_chip_map, 285 }, 286 { 287 PCI_PRODUCT_INTEL_82965PM_IDE, 288 0, 289 "Intel 82965PM IDE controller", 290 piixsata_chip_map, 291 }, 292 { 293 PCI_PRODUCT_INTEL_3400_SATA_1, 294 0, 295 "Intel 3400 Serial ATA Controller", 296 piixsata_chip_map, 297 }, 298 { 299 PCI_PRODUCT_INTEL_3400_SATA_1, 300 0, 301 "Intel 3400 Serial ATA Controller", 302 piixsata_chip_map, 303 }, 304 { 305 PCI_PRODUCT_INTEL_3400_SATA_2, 306 0, 307 "Intel 3400 Serial ATA Controller", 308 piixsata_chip_map, 309 }, 310 { 311 PCI_PRODUCT_INTEL_3400_SATA_3, 312 0, 313 "Intel 3400 Serial ATA Controller", 314 piixsata_chip_map, 315 }, 316 { 317 PCI_PRODUCT_INTEL_3400_SATA_4, 318 0, 319 "Intel 3400 Serial ATA Controller", 320 piixsata_chip_map, 321 }, 322 { 323 PCI_PRODUCT_INTEL_3400_SATA_5, 324 0, 325 "Intel 3400 Serial ATA Controller", 326 piixsata_chip_map, 327 }, 328 { 329 PCI_PRODUCT_INTEL_3400_SATA_6, 330 0, 331 "Intel 3400 Serial ATA Controller", 332 piixsata_chip_map, 333 }, 334 { 0, 335 0, 336 NULL, 337 NULL 338 } 339 }; 340 341 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), 342 piixide_match, piixide_attach, NULL, NULL); 343 344 static int 345 piixide_match(device_t parent, cfdata_t match, void *aux) 346 { 347 struct pci_attach_args *pa = aux; 348 349 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 350 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 351 return (2); 352 } 353 return (0); 354 } 355 356 static void 357 piixide_attach(device_t parent, device_t self, void *aux) 358 { 359 struct pci_attach_args *pa = aux; 360 struct pciide_softc *sc = device_private(self); 361 362 sc->sc_wdcdev.sc_atac.atac_dev = self; 363 364 pciide_common_attach(sc, pa, 365 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 366 367 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 368 aprint_error_dev(self, "couldn't establish power handler\n"); 369 } 370 371 static bool 372 piixide_resume(device_t dv, const pmf_qual_t *qual) 373 { 374 struct pciide_softc *sc = device_private(dv); 375 376 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 377 sc->sc_pm_reg[0]); 378 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 379 sc->sc_pm_reg[1]); 380 381 return true; 382 } 383 384 static bool 385 piixide_suspend(device_t dv, const pmf_qual_t *qual) 386 { 387 struct pciide_softc *sc = device_private(dv); 388 389 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 390 PIIX_IDETIM); 391 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 392 PIIX_UDMAREG); 393 394 return true; 395 } 396 397 static void 398 piix_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 399 { 400 struct pciide_channel *cp; 401 int channel; 402 u_int32_t idetim; 403 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 404 405 if (pciide_chipen(sc, pa) == 0) 406 return; 407 408 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 409 "bus-master DMA support present"); 410 pciide_mapreg_dma(sc, pa); 411 aprint_verbose("\n"); 412 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 413 if (sc->sc_dma_ok) { 414 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 415 sc->sc_wdcdev.irqack = pciide_irqack; 416 /* Do all revisions require DMA alignment workaround? */ 417 sc->sc_wdcdev.dma_init = piix_dma_init; 418 switch(sc->sc_pp->ide_product) { 419 case PCI_PRODUCT_INTEL_82371AB_IDE: 420 case PCI_PRODUCT_INTEL_82440MX_IDE: 421 case PCI_PRODUCT_INTEL_82801AA_IDE: 422 case PCI_PRODUCT_INTEL_82801AB_IDE: 423 case PCI_PRODUCT_INTEL_82801BA_IDE: 424 case PCI_PRODUCT_INTEL_82801BAM_IDE: 425 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 426 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 427 case PCI_PRODUCT_INTEL_82801DB_IDE: 428 case PCI_PRODUCT_INTEL_82801DBM_IDE: 429 case PCI_PRODUCT_INTEL_82801EB_IDE: 430 case PCI_PRODUCT_INTEL_6300ESB_IDE: 431 case PCI_PRODUCT_INTEL_82801FB_IDE: 432 case PCI_PRODUCT_INTEL_82801G_IDE: 433 case PCI_PRODUCT_INTEL_82801HBM_IDE: 434 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 435 } 436 } 437 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 438 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 439 switch(sc->sc_pp->ide_product) { 440 case PCI_PRODUCT_INTEL_82801AA_IDE: 441 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 442 break; 443 case PCI_PRODUCT_INTEL_82801BA_IDE: 444 case PCI_PRODUCT_INTEL_82801BAM_IDE: 445 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 446 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 447 case PCI_PRODUCT_INTEL_82801DB_IDE: 448 case PCI_PRODUCT_INTEL_82801DBM_IDE: 449 case PCI_PRODUCT_INTEL_82801EB_IDE: 450 case PCI_PRODUCT_INTEL_6300ESB_IDE: 451 case PCI_PRODUCT_INTEL_82801FB_IDE: 452 case PCI_PRODUCT_INTEL_82801G_IDE: 453 case PCI_PRODUCT_INTEL_82801HBM_IDE: 454 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 455 break; 456 default: 457 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 458 } 459 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 460 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 461 else 462 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 463 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 464 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 465 466 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 467 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 468 DEBUG_PROBE); 469 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 470 ATADEBUG_PRINT((", sidetim=0x%x", 471 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 472 DEBUG_PROBE); 473 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 474 ATADEBUG_PRINT((", udamreg 0x%x", 475 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 476 DEBUG_PROBE); 477 } 478 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 479 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 480 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 481 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 482 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 483 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 484 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 485 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 486 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 487 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 488 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 489 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 490 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 491 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 492 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 493 DEBUG_PROBE); 494 } 495 496 } 497 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 498 499 wdc_allocate_regs(&sc->sc_wdcdev); 500 501 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 502 channel++) { 503 cp = &sc->pciide_channels[channel]; 504 if (pciide_chansetup(sc, channel, interface) == 0) 505 continue; 506 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 507 if ((PIIX_IDETIM_READ(idetim, channel) & 508 PIIX_IDETIM_IDE) == 0) { 509 #if 1 510 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 511 "%s channel ignored (disabled)\n", cp->name); 512 cp->ata_channel.ch_flags |= ATACH_DISABLED; 513 continue; 514 #else 515 pcireg_t interface; 516 517 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 518 channel); 519 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 520 idetim); 521 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 522 sc->sc_tag, PCI_CLASS_REG)); 523 aprint_normal("channel %d idetim=%08x interface=%02x\n", 524 channel, idetim, interface); 525 #endif 526 } 527 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 528 } 529 530 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 531 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 532 DEBUG_PROBE); 533 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 534 ATADEBUG_PRINT((", sidetim=0x%x", 535 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 536 DEBUG_PROBE); 537 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 538 ATADEBUG_PRINT((", udamreg 0x%x", 539 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 540 DEBUG_PROBE); 541 } 542 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 543 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 544 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 545 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 546 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 547 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 548 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 549 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 550 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 551 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 552 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 553 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 554 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 555 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 556 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 557 DEBUG_PROBE); 558 } 559 } 560 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 561 } 562 563 static void 564 piix_setup_channel(struct ata_channel *chp) 565 { 566 u_int8_t mode[2], drive; 567 u_int32_t oidetim, idetim, idedma_ctl; 568 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 569 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 570 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 571 572 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 573 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 574 idedma_ctl = 0; 575 576 /* set up new idetim: Enable IDE registers decode */ 577 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 578 chp->ch_channel); 579 580 /* setup DMA */ 581 pciide_channel_dma_setup(cp); 582 583 /* 584 * Here we have to mess up with drives mode: PIIX can't have 585 * different timings for master and slave drives. 586 * We need to find the best combination. 587 */ 588 589 /* If both drives supports DMA, take the lower mode */ 590 if ((drvp[0].drive_flags & DRIVE_DMA) && 591 (drvp[1].drive_flags & DRIVE_DMA)) { 592 mode[0] = mode[1] = 593 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 594 drvp[0].DMA_mode = mode[0]; 595 drvp[1].DMA_mode = mode[1]; 596 goto ok; 597 } 598 /* 599 * If only one drive supports DMA, use its mode, and 600 * put the other one in PIO mode 0 if mode not compatible 601 */ 602 if (drvp[0].drive_flags & DRIVE_DMA) { 603 mode[0] = drvp[0].DMA_mode; 604 mode[1] = drvp[1].PIO_mode; 605 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 606 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 607 mode[1] = drvp[1].PIO_mode = 0; 608 goto ok; 609 } 610 if (drvp[1].drive_flags & DRIVE_DMA) { 611 mode[1] = drvp[1].DMA_mode; 612 mode[0] = drvp[0].PIO_mode; 613 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 614 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 615 mode[0] = drvp[0].PIO_mode = 0; 616 goto ok; 617 } 618 /* 619 * If both drives are not DMA, takes the lower mode, unless 620 * one of them is PIO mode < 2 621 */ 622 if (drvp[0].PIO_mode < 2) { 623 mode[0] = drvp[0].PIO_mode = 0; 624 mode[1] = drvp[1].PIO_mode; 625 } else if (drvp[1].PIO_mode < 2) { 626 mode[1] = drvp[1].PIO_mode = 0; 627 mode[0] = drvp[0].PIO_mode; 628 } else { 629 mode[0] = mode[1] = 630 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 631 drvp[0].PIO_mode = mode[0]; 632 drvp[1].PIO_mode = mode[1]; 633 } 634 ok: /* The modes are setup */ 635 for (drive = 0; drive < 2; drive++) { 636 if (drvp[drive].drive_flags & DRIVE_DMA) { 637 idetim |= piix_setup_idetim_timings( 638 mode[drive], 1, chp->ch_channel); 639 goto end; 640 } 641 } 642 /* If we are there, none of the drives are DMA */ 643 if (mode[0] >= 2) 644 idetim |= piix_setup_idetim_timings( 645 mode[0], 0, chp->ch_channel); 646 else 647 idetim |= piix_setup_idetim_timings( 648 mode[1], 0, chp->ch_channel); 649 end: /* 650 * timing mode is now set up in the controller. Enable 651 * it per-drive 652 */ 653 for (drive = 0; drive < 2; drive++) { 654 /* If no drive, skip */ 655 if ((drvp[drive].drive_flags & DRIVE) == 0) 656 continue; 657 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 658 if (drvp[drive].drive_flags & DRIVE_DMA) 659 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 660 } 661 if (idedma_ctl != 0) { 662 /* Add software bits in status register */ 663 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 664 idedma_ctl); 665 } 666 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 667 } 668 669 static void 670 piix3_4_setup_channel(struct ata_channel *chp) 671 { 672 struct ata_drive_datas *drvp; 673 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 674 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 675 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 676 struct wdc_softc *wdc = &sc->sc_wdcdev; 677 int drive, s; 678 int channel = chp->ch_channel; 679 680 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 681 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 682 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 683 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 684 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 685 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 686 PIIX_SIDETIM_RTC_MASK(channel)); 687 idedma_ctl = 0; 688 689 /* set up new idetim: Enable IDE registers decode */ 690 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 691 692 /* setup DMA if needed */ 693 pciide_channel_dma_setup(cp); 694 695 for (drive = 0; drive < 2; drive++) { 696 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 697 PIIX_UDMATIM_SET(0x3, channel, drive)); 698 drvp = &chp->ch_drive[drive]; 699 /* If no drive, skip */ 700 if ((drvp->drive_flags & DRIVE) == 0) 701 continue; 702 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 703 (drvp->drive_flags & DRIVE_UDMA) == 0)) 704 goto pio; 705 706 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 707 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 708 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 709 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 710 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 711 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 712 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 713 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 714 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 715 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 716 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 717 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 718 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 719 ideconf |= PIIX_CONFIG_PINGPONG; 720 } 721 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 722 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 723 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 724 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 725 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 726 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 727 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 728 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 729 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 730 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 731 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 732 /* setup Ultra/100 */ 733 if (drvp->UDMA_mode > 2 && 734 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 735 drvp->UDMA_mode = 2; 736 if (drvp->UDMA_mode > 4) { 737 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 738 } else { 739 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 740 if (drvp->UDMA_mode > 2) { 741 ideconf |= PIIX_CONFIG_UDMA66(channel, 742 drive); 743 } else { 744 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 745 drive); 746 } 747 } 748 } 749 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 750 /* setup Ultra/66 */ 751 if (drvp->UDMA_mode > 2 && 752 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 753 drvp->UDMA_mode = 2; 754 if (drvp->UDMA_mode > 2) 755 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 756 else 757 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 758 } 759 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 760 (drvp->drive_flags & DRIVE_UDMA)) { 761 /* use Ultra/DMA */ 762 s = splbio(); 763 drvp->drive_flags &= ~DRIVE_DMA; 764 splx(s); 765 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 766 udmareg |= PIIX_UDMATIM_SET( 767 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 768 } else { 769 /* use Multiword DMA */ 770 s = splbio(); 771 drvp->drive_flags &= ~DRIVE_UDMA; 772 splx(s); 773 if (drive == 0) { 774 idetim |= piix_setup_idetim_timings( 775 drvp->DMA_mode, 1, channel); 776 } else { 777 sidetim |= piix_setup_sidetim_timings( 778 drvp->DMA_mode, 1, channel); 779 idetim =PIIX_IDETIM_SET(idetim, 780 PIIX_IDETIM_SITRE, channel); 781 } 782 } 783 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 784 785 pio: /* use PIO mode */ 786 idetim |= piix_setup_idetim_drvs(drvp); 787 if (drive == 0) { 788 idetim |= piix_setup_idetim_timings( 789 drvp->PIO_mode, 0, channel); 790 } else { 791 sidetim |= piix_setup_sidetim_timings( 792 drvp->PIO_mode, 0, channel); 793 idetim =PIIX_IDETIM_SET(idetim, 794 PIIX_IDETIM_SITRE, channel); 795 } 796 } 797 if (idedma_ctl != 0) { 798 /* Add software bits in status register */ 799 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 800 idedma_ctl); 801 } 802 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 803 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 804 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 805 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 806 } 807 808 809 /* setup ISP and RTC fields, based on mode */ 810 static u_int32_t 811 piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 812 { 813 814 if (dma) 815 return PIIX_IDETIM_SET(0, 816 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 817 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 818 channel); 819 else 820 return PIIX_IDETIM_SET(0, 821 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 822 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 823 channel); 824 } 825 826 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 827 static u_int32_t 828 piix_setup_idetim_drvs(struct ata_drive_datas *drvp) 829 { 830 u_int32_t ret = 0; 831 struct ata_channel *chp = drvp->chnl_softc; 832 u_int8_t channel = chp->ch_channel; 833 u_int8_t drive = drvp->drive; 834 835 /* 836 * If drive is using UDMA, timings setups are independent 837 * So just check DMA and PIO here. 838 */ 839 if (drvp->drive_flags & DRIVE_DMA) { 840 /* if mode = DMA mode 0, use compatible timings */ 841 if ((drvp->drive_flags & DRIVE_DMA) && 842 drvp->DMA_mode == 0) { 843 drvp->PIO_mode = 0; 844 return ret; 845 } 846 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 847 /* 848 * PIO and DMA timings are the same, use fast timings for PIO 849 * too, else use compat timings. 850 */ 851 if ((piix_isp_pio[drvp->PIO_mode] != 852 piix_isp_dma[drvp->DMA_mode]) || 853 (piix_rtc_pio[drvp->PIO_mode] != 854 piix_rtc_dma[drvp->DMA_mode])) 855 drvp->PIO_mode = 0; 856 /* if PIO mode <= 2, use compat timings for PIO */ 857 if (drvp->PIO_mode <= 2) { 858 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 859 channel); 860 return ret; 861 } 862 } 863 864 /* 865 * Now setup PIO modes. If mode < 2, use compat timings. 866 * Else enable fast timings. Enable IORDY and prefetch/post 867 * if PIO mode >= 3. 868 */ 869 870 if (drvp->PIO_mode < 2) 871 return ret; 872 873 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 874 if (drvp->PIO_mode >= 3) { 875 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 876 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 877 } 878 return ret; 879 } 880 881 /* setup values in SIDETIM registers, based on mode */ 882 static u_int32_t 883 piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 884 { 885 if (dma) 886 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 887 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 888 else 889 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 890 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 891 } 892 893 static void 894 piixsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 895 { 896 struct pciide_channel *cp; 897 pcireg_t interface, cmdsts; 898 int channel; 899 900 if (pciide_chipen(sc, pa) == 0) 901 return; 902 903 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 904 "bus-master DMA support present"); 905 pciide_mapreg_dma(sc, pa); 906 aprint_verbose("\n"); 907 908 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 909 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 910 if (sc->sc_dma_ok) { 911 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 912 sc->sc_wdcdev.irqack = pciide_irqack; 913 /* Do all revisions require DMA alignment workaround? */ 914 sc->sc_wdcdev.dma_init = piix_dma_init; 915 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 916 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 917 } 918 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 919 920 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 921 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 922 923 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 924 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 925 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 926 927 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 928 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 929 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 930 931 interface = PCI_INTERFACE(pa->pa_class); 932 933 wdc_allocate_regs(&sc->sc_wdcdev); 934 935 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 936 channel++) { 937 cp = &sc->pciide_channels[channel]; 938 if (pciide_chansetup(sc, channel, interface) == 0) 939 continue; 940 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 941 } 942 } 943 944 static int 945 piix_dma_init(void *v, int channel, int drive, void *databuf, 946 size_t datalen, int flags) 947 { 948 949 /* use PIO for unaligned transfer */ 950 if (((uintptr_t)databuf) & 0x1) 951 return EINVAL; 952 953 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 954 } 955
Indexes created Wed Oct 15 16:09:53 GMT 2025