piixide.c revision 1.63.2.2
1 /* $NetBSD: piixide.c,v 1.63.2.2 2012/11/20 03:02:28 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: piixide.c,v 1.63.2.2 2012/11/20 03:02:28 tls Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_piix_reg.h> 38 39 static void piix_chip_map(struct pciide_softc*, 40 const struct pci_attach_args *); 41 static void piix_setup_channel(struct ata_channel *); 42 static void piix3_4_setup_channel(struct ata_channel *); 43 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 44 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 45 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 46 static void piixsata_chip_map(struct pciide_softc*, 47 const struct pci_attach_args *); 48 static int piix_dma_init(void *, int, int, void *, size_t, int); 49 50 static bool piixide_resume(device_t, const pmf_qual_t *); 51 static bool piixide_suspend(device_t, const pmf_qual_t *); 52 static int piixide_match(device_t, cfdata_t, void *); 53 static void piixide_attach(device_t, device_t, void *); 54 55 static const struct pciide_product_desc pciide_intel_products[] = { 56 { PCI_PRODUCT_INTEL_82092AA, 57 0, 58 "Intel 82092AA IDE controller", 59 default_chip_map, 60 }, 61 { PCI_PRODUCT_INTEL_82371FB_IDE, 62 0, 63 "Intel 82371FB IDE controller (PIIX)", 64 piix_chip_map, 65 }, 66 { PCI_PRODUCT_INTEL_82371SB_IDE, 67 0, 68 "Intel 82371SB IDE Interface (PIIX3)", 69 piix_chip_map, 70 }, 71 { PCI_PRODUCT_INTEL_82371AB_IDE, 72 0, 73 "Intel 82371AB IDE controller (PIIX4)", 74 piix_chip_map, 75 }, 76 { PCI_PRODUCT_INTEL_82440MX_IDE, 77 0, 78 "Intel 82440MX IDE controller", 79 piix_chip_map 80 }, 81 { PCI_PRODUCT_INTEL_82801AA_IDE, 82 0, 83 "Intel 82801AA IDE Controller (ICH)", 84 piix_chip_map, 85 }, 86 { PCI_PRODUCT_INTEL_82801AB_IDE, 87 0, 88 "Intel 82801AB IDE Controller (ICH0)", 89 piix_chip_map, 90 }, 91 { PCI_PRODUCT_INTEL_82801BA_IDE, 92 0, 93 "Intel 82801BA IDE Controller (ICH2)", 94 piix_chip_map, 95 }, 96 { PCI_PRODUCT_INTEL_82801BAM_IDE, 97 0, 98 "Intel 82801BAM IDE Controller (ICH2-M)", 99 piix_chip_map, 100 }, 101 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 102 0, 103 "Intel 82801CA IDE Controller (ICH3)", 104 piix_chip_map, 105 }, 106 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 107 0, 108 "Intel 82801CA IDE Controller (ICH3)", 109 piix_chip_map, 110 }, 111 { PCI_PRODUCT_INTEL_82801DB_IDE, 112 0, 113 "Intel 82801DB IDE Controller (ICH4)", 114 piix_chip_map, 115 }, 116 { PCI_PRODUCT_INTEL_82801DBM_IDE, 117 0, 118 "Intel 82801DBM IDE Controller (ICH4-M)", 119 piix_chip_map, 120 }, 121 { PCI_PRODUCT_INTEL_82801EB_IDE, 122 0, 123 "Intel 82801EB IDE Controller (ICH5)", 124 piix_chip_map, 125 }, 126 { PCI_PRODUCT_INTEL_82801EB_SATA, 127 0, 128 "Intel 82801EB Serial ATA Controller", 129 piixsata_chip_map, 130 }, 131 { PCI_PRODUCT_INTEL_82801ER_SATA, 132 0, 133 "Intel 82801ER Serial ATA/Raid Controller", 134 piixsata_chip_map, 135 }, 136 { PCI_PRODUCT_INTEL_6300ESB_IDE, 137 0, 138 "Intel 6300ESB IDE Controller (ICH5)", 139 piix_chip_map, 140 }, 141 { PCI_PRODUCT_INTEL_6300ESB_SATA, 142 0, 143 "Intel 6300ESB Serial ATA Controller", 144 piixsata_chip_map, 145 }, 146 { PCI_PRODUCT_INTEL_6300ESB_RAID, 147 0, 148 "Intel 6300ESB Serial ATA/RAID Controller", 149 piixsata_chip_map, 150 }, 151 { PCI_PRODUCT_INTEL_82801FB_IDE, 152 0, 153 "Intel 82801FB IDE Controller (ICH6)", 154 piix_chip_map, 155 }, 156 { PCI_PRODUCT_INTEL_82801FB_SATA, 157 0, 158 "Intel 82801FB Serial ATA/Raid Controller", 159 piixsata_chip_map, 160 }, 161 { PCI_PRODUCT_INTEL_82801FR_SATA, 162 0, 163 "Intel 82801FR Serial ATA/Raid Controller", 164 piixsata_chip_map, 165 }, 166 { PCI_PRODUCT_INTEL_82801FBM_SATA, 167 0, 168 "Intel 82801FBM Serial ATA Controller (ICH6)", 169 piixsata_chip_map, 170 }, 171 { PCI_PRODUCT_INTEL_82801G_IDE, 172 0, 173 "Intel 82801GB/GR IDE Controller (ICH7)", 174 piix_chip_map, 175 }, 176 { PCI_PRODUCT_INTEL_82801G_SATA, 177 0, 178 "Intel 82801GB/GR Serial ATA/Raid Controller (ICH7)", 179 piixsata_chip_map, 180 }, 181 { PCI_PRODUCT_INTEL_82801GBM_SATA, 182 0, 183 "Intel 82801GBM/GHM Serial ATA Controller (ICH7)", 184 piixsata_chip_map, 185 }, 186 { PCI_PRODUCT_INTEL_82801H_SATA_1, 187 0, 188 "Intel 82801H Serial ATA Controller (ICH8)", 189 piixsata_chip_map, 190 }, 191 { PCI_PRODUCT_INTEL_82801H_SATA_RAID, 192 0, 193 "Intel 82801H Serial ATA RAID Controller (ICH8)", 194 piixsata_chip_map, 195 }, 196 { PCI_PRODUCT_INTEL_82801H_SATA_2, 197 0, 198 "Intel 82801H Serial ATA Controller (ICH8)", 199 piixsata_chip_map, 200 }, 201 { PCI_PRODUCT_INTEL_82801HBM_IDE, 202 0, 203 "Intel 82801HBM IDE Controller (ICH8M)", 204 piix_chip_map, 205 }, 206 { PCI_PRODUCT_INTEL_82801HBM_SATA_1, 207 0, 208 "Intel 82801HBM Serial ATA Controller (ICH8M)", 209 piixsata_chip_map, 210 }, 211 { PCI_PRODUCT_INTEL_82801HBM_SATA_2, 212 0, 213 "Intel 82801HBM Serial ATA Controller (ICH8M)", 214 piixsata_chip_map, 215 }, 216 { PCI_PRODUCT_INTEL_82801HEM_SATA, 217 0, 218 "Intel 82801HEM Serial ATA Controller (ICH8M)", 219 piixsata_chip_map, 220 }, 221 { PCI_PRODUCT_INTEL_63XXESB_IDE, 222 0, 223 "Intel 631xESB/632xESB IDE Controller", 224 piix_chip_map, 225 }, 226 { PCI_PRODUCT_INTEL_82801I_SATA_1, 227 0, 228 "Intel 82801I Serial ATA Controller (ICH9)", 229 piixsata_chip_map, 230 }, 231 { PCI_PRODUCT_INTEL_82801I_SATA_2, 232 0, 233 "Intel 82801I Serial ATA Controller (ICH9)", 234 piixsata_chip_map, 235 }, 236 { PCI_PRODUCT_INTEL_82801I_SATA_3, 237 0, 238 "Intel 82801I Serial ATA Controller (ICH9)", 239 piixsata_chip_map, 240 }, 241 { PCI_PRODUCT_INTEL_82801I_SATA_4, 242 0, 243 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 244 piixsata_chip_map, 245 }, 246 { PCI_PRODUCT_INTEL_82801I_SATA_5, 247 0, 248 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 249 piixsata_chip_map, 250 }, 251 { PCI_PRODUCT_INTEL_82801I_SATA_6, 252 0, 253 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 254 piixsata_chip_map, 255 }, 256 { PCI_PRODUCT_INTEL_82801I_SATA_7, 257 0, 258 "Intel 82801I Mobile Serial ATA Controller (ICH9)", 259 piixsata_chip_map, 260 }, 261 { PCI_PRODUCT_INTEL_63XXESB_SATA, 262 0, 263 "Intel 631xESB/632xESB Serial ATA Controller", 264 piixsata_chip_map, 265 }, 266 { PCI_PRODUCT_INTEL_82801JD_SATA_IDE2, 267 0, 268 "Intel 82801JD Serial ATA Controller (ICH10)", 269 piixsata_chip_map, 270 }, 271 { PCI_PRODUCT_INTEL_82801JI_SATA_IDE2, 272 0, 273 "Intel 82801JI Serial ATA Controller (ICH10)", 274 piixsata_chip_map, 275 }, 276 { PCI_PRODUCT_INTEL_82801JD_SATA_IDE, 277 0, 278 "Intel 82801JD Serial ATA Controller (ICH10)", 279 piixsata_chip_map, 280 }, 281 { PCI_PRODUCT_INTEL_82801JI_SATA_IDE, 282 0, 283 "Intel 82801JI Serial ATA Controller (ICH10)", 284 piixsata_chip_map, 285 }, 286 { 287 PCI_PRODUCT_INTEL_82965PM_IDE, 288 0, 289 "Intel 82965PM IDE controller", 290 piixsata_chip_map, 291 }, 292 { 293 PCI_PRODUCT_INTEL_3400_SATA_1, 294 0, 295 "Intel 3400 Serial ATA Controller", 296 piixsata_chip_map, 297 }, 298 { 299 PCI_PRODUCT_INTEL_3400_SATA_1, 300 0, 301 "Intel 3400 Serial ATA Controller", 302 piixsata_chip_map, 303 }, 304 { 305 PCI_PRODUCT_INTEL_3400_SATA_2, 306 0, 307 "Intel 3400 Serial ATA Controller", 308 piixsata_chip_map, 309 }, 310 { 311 PCI_PRODUCT_INTEL_3400_SATA_3, 312 0, 313 "Intel 3400 Serial ATA Controller", 314 piixsata_chip_map, 315 }, 316 { 317 PCI_PRODUCT_INTEL_3400_SATA_4, 318 0, 319 "Intel 3400 Serial ATA Controller", 320 piixsata_chip_map, 321 }, 322 { 323 PCI_PRODUCT_INTEL_3400_SATA_5, 324 0, 325 "Intel 3400 Serial ATA Controller", 326 piixsata_chip_map, 327 }, 328 { 329 PCI_PRODUCT_INTEL_3400_SATA_6, 330 0, 331 "Intel 3400 Serial ATA Controller", 332 piixsata_chip_map, 333 }, 334 { 335 PCI_PRODUCT_INTEL_6SERIES_SATA_1, 336 0, 337 "Intel 6 Series Serial ATA Controller", 338 piixsata_chip_map, 339 }, 340 { 341 PCI_PRODUCT_INTEL_6SERIES_SATA_2, 342 0, 343 "Intel 6 Series Serial ATA Controller", 344 piixsata_chip_map, 345 }, 346 { 347 PCI_PRODUCT_INTEL_6SERIES_SATA_3, 348 0, 349 "Intel 6 Series Serial ATA Controller", 350 piixsata_chip_map, 351 }, 352 { 353 PCI_PRODUCT_INTEL_6SERIES_SATA_4, 354 0, 355 "Intel 6 Series Serial ATA Controller", 356 piixsata_chip_map, 357 }, 358 { 0, 359 0, 360 NULL, 361 NULL 362 } 363 }; 364 365 CFATTACH_DECL_NEW(piixide, sizeof(struct pciide_softc), 366 piixide_match, piixide_attach, pciide_detach, NULL); 367 368 static int 369 piixide_match(device_t parent, cfdata_t match, void *aux) 370 { 371 struct pci_attach_args *pa = aux; 372 373 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 374 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 375 return (2); 376 } 377 return (0); 378 } 379 380 static void 381 piixide_attach(device_t parent, device_t self, void *aux) 382 { 383 struct pci_attach_args *pa = aux; 384 struct pciide_softc *sc = device_private(self); 385 386 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 387 388 sc->sc_wdcdev.sc_atac.atac_dev = self; 389 390 pciide_common_attach(sc, pa, 391 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 392 393 if (!pmf_device_register(self, piixide_suspend, piixide_resume)) 394 aprint_error_dev(self, "couldn't establish power handler\n"); 395 } 396 397 static bool 398 piixide_resume(device_t dv, const pmf_qual_t *qual) 399 { 400 struct pciide_softc *sc = device_private(dv); 401 402 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 403 sc->sc_pm_reg[0]); 404 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, 405 sc->sc_pm_reg[1]); 406 407 return true; 408 } 409 410 static bool 411 piixide_suspend(device_t dv, const pmf_qual_t *qual) 412 { 413 struct pciide_softc *sc = device_private(dv); 414 415 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 416 PIIX_IDETIM); 417 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 418 PIIX_UDMAREG); 419 420 return true; 421 } 422 423 static void 424 piix_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 425 { 426 struct pciide_channel *cp; 427 int channel; 428 u_int32_t idetim; 429 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 430 431 if (pciide_chipen(sc, pa) == 0) 432 return; 433 434 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 435 "bus-master DMA support present"); 436 pciide_mapreg_dma(sc, pa); 437 aprint_verbose("\n"); 438 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 439 if (sc->sc_dma_ok) { 440 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 441 sc->sc_wdcdev.irqack = pciide_irqack; 442 /* Do all revisions require DMA alignment workaround? */ 443 sc->sc_wdcdev.dma_init = piix_dma_init; 444 switch(sc->sc_pp->ide_product) { 445 case PCI_PRODUCT_INTEL_82371AB_IDE: 446 case PCI_PRODUCT_INTEL_82440MX_IDE: 447 case PCI_PRODUCT_INTEL_82801AA_IDE: 448 case PCI_PRODUCT_INTEL_82801AB_IDE: 449 case PCI_PRODUCT_INTEL_82801BA_IDE: 450 case PCI_PRODUCT_INTEL_82801BAM_IDE: 451 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 452 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 453 case PCI_PRODUCT_INTEL_82801DB_IDE: 454 case PCI_PRODUCT_INTEL_82801DBM_IDE: 455 case PCI_PRODUCT_INTEL_82801EB_IDE: 456 case PCI_PRODUCT_INTEL_6300ESB_IDE: 457 case PCI_PRODUCT_INTEL_82801FB_IDE: 458 case PCI_PRODUCT_INTEL_82801G_IDE: 459 case PCI_PRODUCT_INTEL_82801HBM_IDE: 460 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 461 } 462 } 463 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 464 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 465 switch(sc->sc_pp->ide_product) { 466 case PCI_PRODUCT_INTEL_82801AA_IDE: 467 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 468 break; 469 case PCI_PRODUCT_INTEL_82801BA_IDE: 470 case PCI_PRODUCT_INTEL_82801BAM_IDE: 471 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 472 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 473 case PCI_PRODUCT_INTEL_82801DB_IDE: 474 case PCI_PRODUCT_INTEL_82801DBM_IDE: 475 case PCI_PRODUCT_INTEL_82801EB_IDE: 476 case PCI_PRODUCT_INTEL_6300ESB_IDE: 477 case PCI_PRODUCT_INTEL_82801FB_IDE: 478 case PCI_PRODUCT_INTEL_82801G_IDE: 479 case PCI_PRODUCT_INTEL_82801HBM_IDE: 480 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 481 break; 482 default: 483 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 484 } 485 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 486 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 487 else 488 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 489 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 490 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 491 sc->sc_wdcdev.wdc_maxdrives = 2; 492 493 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 494 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 495 DEBUG_PROBE); 496 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 497 ATADEBUG_PRINT((", sidetim=0x%x", 498 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 499 DEBUG_PROBE); 500 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 501 ATADEBUG_PRINT((", udamreg 0x%x", 502 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 503 DEBUG_PROBE); 504 } 505 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 506 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 507 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 508 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 509 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 510 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 511 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 512 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 513 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 514 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 515 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 516 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 517 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 518 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 519 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 520 DEBUG_PROBE); 521 } 522 523 } 524 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 525 526 wdc_allocate_regs(&sc->sc_wdcdev); 527 528 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 529 channel++) { 530 cp = &sc->pciide_channels[channel]; 531 if (pciide_chansetup(sc, channel, interface) == 0) 532 continue; 533 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 534 if ((PIIX_IDETIM_READ(idetim, channel) & 535 PIIX_IDETIM_IDE) == 0) { 536 #if 1 537 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 538 "%s channel ignored (disabled)\n", cp->name); 539 cp->ata_channel.ch_flags |= ATACH_DISABLED; 540 continue; 541 #else 542 pcireg_t interface; 543 544 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 545 channel); 546 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 547 idetim); 548 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 549 sc->sc_tag, PCI_CLASS_REG)); 550 aprint_normal("channel %d idetim=%08x interface=%02x\n", 551 channel, idetim, interface); 552 #endif 553 } 554 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 555 } 556 557 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 558 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 559 DEBUG_PROBE); 560 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 561 ATADEBUG_PRINT((", sidetim=0x%x", 562 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 563 DEBUG_PROBE); 564 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 565 ATADEBUG_PRINT((", udamreg 0x%x", 566 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 567 DEBUG_PROBE); 568 } 569 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 570 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 571 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 572 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 573 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 574 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 575 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 576 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 577 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 578 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 579 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 580 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 581 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 582 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 583 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 584 DEBUG_PROBE); 585 } 586 } 587 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 588 } 589 590 static void 591 piix_setup_channel(struct ata_channel *chp) 592 { 593 u_int8_t mode[2], drive; 594 u_int32_t oidetim, idetim, idedma_ctl; 595 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 596 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 597 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 598 599 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 600 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 601 idedma_ctl = 0; 602 603 /* set up new idetim: Enable IDE registers decode */ 604 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 605 chp->ch_channel); 606 607 /* setup DMA */ 608 pciide_channel_dma_setup(cp); 609 610 /* 611 * Here we have to mess up with drives mode: PIIX can't have 612 * different timings for master and slave drives. 613 * We need to find the best combination. 614 */ 615 616 /* If both drives supports DMA, take the lower mode */ 617 if ((drvp[0].drive_flags & ATA_DRIVE_DMA) && 618 (drvp[1].drive_flags & ATA_DRIVE_DMA)) { 619 mode[0] = mode[1] = 620 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 621 drvp[0].DMA_mode = mode[0]; 622 drvp[1].DMA_mode = mode[1]; 623 goto ok; 624 } 625 /* 626 * If only one drive supports DMA, use its mode, and 627 * put the other one in PIO mode 0 if mode not compatible 628 */ 629 if (drvp[0].drive_flags & ATA_DRIVE_DMA) { 630 mode[0] = drvp[0].DMA_mode; 631 mode[1] = drvp[1].PIO_mode; 632 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 633 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 634 mode[1] = drvp[1].PIO_mode = 0; 635 goto ok; 636 } 637 if (drvp[1].drive_flags & ATA_DRIVE_DMA) { 638 mode[1] = drvp[1].DMA_mode; 639 mode[0] = drvp[0].PIO_mode; 640 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 641 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 642 mode[0] = drvp[0].PIO_mode = 0; 643 goto ok; 644 } 645 /* 646 * If both drives are not DMA, takes the lower mode, unless 647 * one of them is PIO mode < 2 648 */ 649 if (drvp[0].PIO_mode < 2) { 650 mode[0] = drvp[0].PIO_mode = 0; 651 mode[1] = drvp[1].PIO_mode; 652 } else if (drvp[1].PIO_mode < 2) { 653 mode[1] = drvp[1].PIO_mode = 0; 654 mode[0] = drvp[0].PIO_mode; 655 } else { 656 mode[0] = mode[1] = 657 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 658 drvp[0].PIO_mode = mode[0]; 659 drvp[1].PIO_mode = mode[1]; 660 } 661 ok: /* The modes are setup */ 662 for (drive = 0; drive < 2; drive++) { 663 if (drvp[drive].drive_flags & ATA_DRIVE_DMA) { 664 idetim |= piix_setup_idetim_timings( 665 mode[drive], 1, chp->ch_channel); 666 goto end; 667 } 668 } 669 /* If we are there, none of the drives are DMA */ 670 if (mode[0] >= 2) 671 idetim |= piix_setup_idetim_timings( 672 mode[0], 0, chp->ch_channel); 673 else 674 idetim |= piix_setup_idetim_timings( 675 mode[1], 0, chp->ch_channel); 676 end: /* 677 * timing mode is now set up in the controller. Enable 678 * it per-drive 679 */ 680 for (drive = 0; drive < 2; drive++) { 681 /* If no drive, skip */ 682 if (drvp[drive].drive_type == ATA_DRIVET_NONE) 683 continue; 684 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 685 if (drvp[drive].drive_flags & ATA_DRIVE_DMA) 686 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 687 } 688 if (idedma_ctl != 0) { 689 /* Add software bits in status register */ 690 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 691 idedma_ctl); 692 } 693 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 694 } 695 696 static void 697 piix3_4_setup_channel(struct ata_channel *chp) 698 { 699 struct ata_drive_datas *drvp; 700 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 701 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 702 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 703 struct wdc_softc *wdc = &sc->sc_wdcdev; 704 int drive, s; 705 int channel = chp->ch_channel; 706 707 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 708 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 709 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 710 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 711 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 712 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 713 PIIX_SIDETIM_RTC_MASK(channel)); 714 idedma_ctl = 0; 715 716 /* set up new idetim: Enable IDE registers decode */ 717 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 718 719 /* setup DMA if needed */ 720 pciide_channel_dma_setup(cp); 721 722 for (drive = 0; drive < 2; drive++) { 723 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 724 PIIX_UDMATIM_SET(0x3, channel, drive)); 725 drvp = &chp->ch_drive[drive]; 726 /* If no drive, skip */ 727 if (drvp->drive_type == ATA_DRIVET_NONE) 728 continue; 729 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 730 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0)) 731 goto pio; 732 733 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 734 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 735 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 736 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 737 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 738 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 739 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 740 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 741 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 742 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 743 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 744 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 745 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 746 ideconf |= PIIX_CONFIG_PINGPONG; 747 } 748 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 749 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 750 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 751 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 752 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 753 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 754 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 755 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 756 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE || 757 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801G_IDE || 758 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801HBM_IDE) { 759 /* setup Ultra/100 */ 760 if (drvp->UDMA_mode > 2 && 761 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 762 drvp->UDMA_mode = 2; 763 if (drvp->UDMA_mode > 4) { 764 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 765 } else { 766 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 767 if (drvp->UDMA_mode > 2) { 768 ideconf |= PIIX_CONFIG_UDMA66(channel, 769 drive); 770 } else { 771 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 772 drive); 773 } 774 } 775 } 776 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 777 /* setup Ultra/66 */ 778 if (drvp->UDMA_mode > 2 && 779 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 780 drvp->UDMA_mode = 2; 781 if (drvp->UDMA_mode > 2) 782 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 783 else 784 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 785 } 786 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 787 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 788 /* use Ultra/DMA */ 789 s = splbio(); 790 drvp->drive_flags &= ~ATA_DRIVE_DMA; 791 splx(s); 792 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 793 udmareg |= PIIX_UDMATIM_SET( 794 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 795 } else { 796 /* use Multiword DMA */ 797 s = splbio(); 798 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 799 splx(s); 800 if (drive == 0) { 801 idetim |= piix_setup_idetim_timings( 802 drvp->DMA_mode, 1, channel); 803 } else { 804 sidetim |= piix_setup_sidetim_timings( 805 drvp->DMA_mode, 1, channel); 806 idetim =PIIX_IDETIM_SET(idetim, 807 PIIX_IDETIM_SITRE, channel); 808 } 809 } 810 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 811 812 pio: /* use PIO mode */ 813 idetim |= piix_setup_idetim_drvs(drvp); 814 if (drive == 0) { 815 idetim |= piix_setup_idetim_timings( 816 drvp->PIO_mode, 0, channel); 817 } else { 818 sidetim |= piix_setup_sidetim_timings( 819 drvp->PIO_mode, 0, channel); 820 idetim =PIIX_IDETIM_SET(idetim, 821 PIIX_IDETIM_SITRE, channel); 822 } 823 } 824 if (idedma_ctl != 0) { 825 /* Add software bits in status register */ 826 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 827 idedma_ctl); 828 } 829 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 830 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 831 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 832 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 833 } 834 835 836 /* setup ISP and RTC fields, based on mode */ 837 static u_int32_t 838 piix_setup_idetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 839 { 840 841 if (dma) 842 return PIIX_IDETIM_SET(0, 843 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 844 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 845 channel); 846 else 847 return PIIX_IDETIM_SET(0, 848 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 849 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 850 channel); 851 } 852 853 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 854 static u_int32_t 855 piix_setup_idetim_drvs(struct ata_drive_datas *drvp) 856 { 857 u_int32_t ret = 0; 858 struct ata_channel *chp = drvp->chnl_softc; 859 u_int8_t channel = chp->ch_channel; 860 u_int8_t drive = drvp->drive; 861 862 /* 863 * If drive is using UDMA, timings setups are independent 864 * So just check DMA and PIO here. 865 */ 866 if (drvp->drive_flags & ATA_DRIVE_DMA) { 867 /* if mode = DMA mode 0, use compatible timings */ 868 if ((drvp->drive_flags & ATA_DRIVE_DMA) && 869 drvp->DMA_mode == 0) { 870 drvp->PIO_mode = 0; 871 return ret; 872 } 873 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 874 /* 875 * PIO and DMA timings are the same, use fast timings for PIO 876 * too, else use compat timings. 877 */ 878 if ((piix_isp_pio[drvp->PIO_mode] != 879 piix_isp_dma[drvp->DMA_mode]) || 880 (piix_rtc_pio[drvp->PIO_mode] != 881 piix_rtc_dma[drvp->DMA_mode])) 882 drvp->PIO_mode = 0; 883 /* if PIO mode <= 2, use compat timings for PIO */ 884 if (drvp->PIO_mode <= 2) { 885 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 886 channel); 887 return ret; 888 } 889 } 890 891 /* 892 * Now setup PIO modes. If mode < 2, use compat timings. 893 * Else enable fast timings. Enable IORDY and prefetch/post 894 * if PIO mode >= 3. 895 */ 896 897 if (drvp->PIO_mode < 2) 898 return ret; 899 900 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 901 if (drvp->PIO_mode >= 3) { 902 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 903 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 904 } 905 return ret; 906 } 907 908 /* setup values in SIDETIM registers, based on mode */ 909 static u_int32_t 910 piix_setup_sidetim_timings(u_int8_t mode, u_int8_t dma, u_int8_t channel) 911 { 912 if (dma) 913 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 914 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 915 else 916 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 917 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 918 } 919 920 static void 921 piixsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 922 { 923 struct pciide_channel *cp; 924 pcireg_t interface, cmdsts; 925 int channel; 926 927 if (pciide_chipen(sc, pa) == 0) 928 return; 929 930 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 931 "bus-master DMA support present"); 932 pciide_mapreg_dma(sc, pa); 933 aprint_verbose("\n"); 934 935 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 936 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 937 if (sc->sc_dma_ok) { 938 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 939 sc->sc_wdcdev.irqack = pciide_irqack; 940 /* Do all revisions require DMA alignment workaround? */ 941 sc->sc_wdcdev.dma_init = piix_dma_init; 942 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 943 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 944 } 945 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 946 947 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 948 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 949 sc->sc_wdcdev.wdc_maxdrives = 2; 950 951 cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 952 cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE; 953 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts); 954 955 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 956 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 957 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID; 958 959 interface = PCI_INTERFACE(pa->pa_class); 960 961 wdc_allocate_regs(&sc->sc_wdcdev); 962 963 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 964 channel++) { 965 cp = &sc->pciide_channels[channel]; 966 if (pciide_chansetup(sc, channel, interface) == 0) 967 continue; 968 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 969 } 970 } 971 972 static int 973 piix_dma_init(void *v, int channel, int drive, void *databuf, 974 size_t datalen, int flags) 975 { 976 977 /* use PIO for unaligned transfer */ 978 if (((uintptr_t)databuf) & 0x1) 979 return EINVAL; 980 981 return pciide_dma_init(v, channel, drive, databuf, datalen, flags); 982 } 983
Indexes created Thu Oct 16 14:10:15 GMT 2025