piixide.c revision 1.7
1 /* $NetBSD: piixide.c,v 1.7 2004/01/03 01:50:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct wdc_channel *); 43 static void piix3_4_setup_channel(struct wdc_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static int piixide_match(struct device *, struct cfdata *, void *); 50 static void piixide_attach(struct device *, struct device *, void *); 51 52 static const struct pciide_product_desc pciide_intel_products[] = { 53 { PCI_PRODUCT_INTEL_82092AA, 54 0, 55 "Intel 82092AA IDE controller", 56 default_chip_map, 57 }, 58 { PCI_PRODUCT_INTEL_82371FB_IDE, 59 0, 60 "Intel 82371FB IDE controller (PIIX)", 61 piix_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371SB_IDE, 64 0, 65 "Intel 82371SB IDE Interface (PIIX3)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371AB_IDE, 69 0, 70 "Intel 82371AB IDE controller (PIIX4)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82440MX_IDE, 74 0, 75 "Intel 82440MX IDE controller", 76 piix_chip_map 77 }, 78 { PCI_PRODUCT_INTEL_82801AA_IDE, 79 0, 80 "Intel 82801AA IDE Controller (ICH)", 81 piix_chip_map, 82 }, 83 { PCI_PRODUCT_INTEL_82801AB_IDE, 84 0, 85 "Intel 82801AB IDE Controller (ICH0)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801BA_IDE, 89 0, 90 "Intel 82801BA IDE Controller (ICH2)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 0, 95 "Intel 82801BAM IDE Controller (ICH2-M)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 0, 100 "Intel 82801CA IDE Controller (ICH3)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801DB_IDE, 109 0, 110 "Intel 82801DB IDE Controller (ICH4)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 0, 115 "Intel 82801DBM IDE Controller (ICH4-M)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801EB_IDE, 119 0, 120 "Intel 82801EB IDE Controller (ICH5)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_SATA, 124 0, 125 "Intel 82801EB Serial ATA Controller", 126 piixsata_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801ER_SATA, 129 0, 130 "Intel 82801ER Serial ATA/Raid Controller", 131 piixsata_chip_map, 132 }, 133 { 0, 134 0, 135 NULL, 136 NULL 137 } 138 }; 139 140 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 141 piixide_match, piixide_attach, NULL, NULL); 142 143 static int 144 piixide_match(struct device *parent, struct cfdata *match, void *aux) 145 { 146 struct pci_attach_args *pa = aux; 147 148 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 149 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 150 return (2); 151 } 152 return (0); 153 } 154 155 static void 156 piixide_attach(struct device *parent, struct device *self, void *aux) 157 { 158 struct pci_attach_args *pa = aux; 159 struct pciide_softc *sc = (struct pciide_softc *)self; 160 161 pciide_common_attach(sc, pa, 162 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 163 164 } 165 166 static void 167 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 168 { 169 struct pciide_channel *cp; 170 int channel; 171 u_int32_t idetim; 172 bus_size_t cmdsize, ctlsize; 173 174 if (pciide_chipen(sc, pa) == 0) 175 return; 176 177 aprint_normal("%s: bus-master DMA support present", 178 sc->sc_wdcdev.sc_dev.dv_xname); 179 pciide_mapreg_dma(sc, pa); 180 aprint_normal("\n"); 181 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 182 WDC_CAPABILITY_MODE; 183 if (sc->sc_dma_ok) { 184 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 185 sc->sc_wdcdev.irqack = pciide_irqack; 186 switch(sc->sc_pp->ide_product) { 187 case PCI_PRODUCT_INTEL_82371AB_IDE: 188 case PCI_PRODUCT_INTEL_82440MX_IDE: 189 case PCI_PRODUCT_INTEL_82801AA_IDE: 190 case PCI_PRODUCT_INTEL_82801AB_IDE: 191 case PCI_PRODUCT_INTEL_82801BA_IDE: 192 case PCI_PRODUCT_INTEL_82801BAM_IDE: 193 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 194 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 195 case PCI_PRODUCT_INTEL_82801DB_IDE: 196 case PCI_PRODUCT_INTEL_82801DBM_IDE: 197 case PCI_PRODUCT_INTEL_82801EB_IDE: 198 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 199 } 200 } 201 sc->sc_wdcdev.PIO_cap = 4; 202 sc->sc_wdcdev.DMA_cap = 2; 203 switch(sc->sc_pp->ide_product) { 204 case PCI_PRODUCT_INTEL_82801AA_IDE: 205 sc->sc_wdcdev.UDMA_cap = 4; 206 break; 207 case PCI_PRODUCT_INTEL_82801BA_IDE: 208 case PCI_PRODUCT_INTEL_82801BAM_IDE: 209 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 210 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 211 case PCI_PRODUCT_INTEL_82801DB_IDE: 212 case PCI_PRODUCT_INTEL_82801DBM_IDE: 213 case PCI_PRODUCT_INTEL_82801EB_IDE: 214 sc->sc_wdcdev.UDMA_cap = 5; 215 break; 216 default: 217 sc->sc_wdcdev.UDMA_cap = 2; 218 } 219 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 220 sc->sc_wdcdev.set_modes = piix_setup_channel; 221 else 222 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 223 sc->sc_wdcdev.channels = sc->wdc_chanarray; 224 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 225 226 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 227 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 228 DEBUG_PROBE); 229 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 230 WDCDEBUG_PRINT((", sidetim=0x%x", 231 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 232 DEBUG_PROBE); 233 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 234 WDCDEBUG_PRINT((", udamreg 0x%x", 235 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 236 DEBUG_PROBE); 237 } 238 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 239 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 240 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 241 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 242 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 243 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 244 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 245 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 246 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ) { 247 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 248 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 249 DEBUG_PROBE); 250 } 251 252 } 253 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 254 255 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 256 cp = &sc->pciide_channels[channel]; 257 /* PIIX is compat-only */ 258 if (pciide_chansetup(sc, channel, 0) == 0) 259 continue; 260 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 261 if ((PIIX_IDETIM_READ(idetim, channel) & 262 PIIX_IDETIM_IDE) == 0) { 263 #if 1 264 aprint_normal("%s: %s channel ignored (disabled)\n", 265 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 266 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 267 continue; 268 #else 269 pcireg_t interface; 270 271 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 272 channel); 273 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 274 idetim); 275 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 276 sc->sc_tag, PCI_CLASS_REG)); 277 aprint_normal("channel %d idetim=%08x interface=%02x\n", 278 channel, idetim, interface); 279 #endif 280 } 281 /* PIIX are compat-only pciide devices */ 282 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 283 } 284 285 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 286 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 287 DEBUG_PROBE); 288 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 289 WDCDEBUG_PRINT((", sidetim=0x%x", 290 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 291 DEBUG_PROBE); 292 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 293 WDCDEBUG_PRINT((", udamreg 0x%x", 294 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 295 DEBUG_PROBE); 296 } 297 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 298 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 299 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 300 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 301 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 302 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 303 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 304 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 305 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 306 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 307 DEBUG_PROBE); 308 } 309 } 310 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 311 } 312 313 static void 314 piix_setup_channel(struct wdc_channel *chp) 315 { 316 u_int8_t mode[2], drive; 317 u_int32_t oidetim, idetim, idedma_ctl; 318 struct pciide_channel *cp = (struct pciide_channel*)chp; 319 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 320 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 321 322 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 323 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 324 idedma_ctl = 0; 325 326 /* set up new idetim: Enable IDE registers decode */ 327 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 328 chp->channel); 329 330 /* setup DMA */ 331 pciide_channel_dma_setup(cp); 332 333 /* 334 * Here we have to mess up with drives mode: PIIX can't have 335 * different timings for master and slave drives. 336 * We need to find the best combination. 337 */ 338 339 /* If both drives supports DMA, take the lower mode */ 340 if ((drvp[0].drive_flags & DRIVE_DMA) && 341 (drvp[1].drive_flags & DRIVE_DMA)) { 342 mode[0] = mode[1] = 343 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 344 drvp[0].DMA_mode = mode[0]; 345 drvp[1].DMA_mode = mode[1]; 346 goto ok; 347 } 348 /* 349 * If only one drive supports DMA, use its mode, and 350 * put the other one in PIO mode 0 if mode not compatible 351 */ 352 if (drvp[0].drive_flags & DRIVE_DMA) { 353 mode[0] = drvp[0].DMA_mode; 354 mode[1] = drvp[1].PIO_mode; 355 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 356 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 357 mode[1] = drvp[1].PIO_mode = 0; 358 goto ok; 359 } 360 if (drvp[1].drive_flags & DRIVE_DMA) { 361 mode[1] = drvp[1].DMA_mode; 362 mode[0] = drvp[0].PIO_mode; 363 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 364 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 365 mode[0] = drvp[0].PIO_mode = 0; 366 goto ok; 367 } 368 /* 369 * If both drives are not DMA, takes the lower mode, unless 370 * one of them is PIO mode < 2 371 */ 372 if (drvp[0].PIO_mode < 2) { 373 mode[0] = drvp[0].PIO_mode = 0; 374 mode[1] = drvp[1].PIO_mode; 375 } else if (drvp[1].PIO_mode < 2) { 376 mode[1] = drvp[1].PIO_mode = 0; 377 mode[0] = drvp[0].PIO_mode; 378 } else { 379 mode[0] = mode[1] = 380 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 381 drvp[0].PIO_mode = mode[0]; 382 drvp[1].PIO_mode = mode[1]; 383 } 384 ok: /* The modes are setup */ 385 for (drive = 0; drive < 2; drive++) { 386 if (drvp[drive].drive_flags & DRIVE_DMA) { 387 idetim |= piix_setup_idetim_timings( 388 mode[drive], 1, chp->channel); 389 goto end; 390 } 391 } 392 /* If we are there, none of the drives are DMA */ 393 if (mode[0] >= 2) 394 idetim |= piix_setup_idetim_timings( 395 mode[0], 0, chp->channel); 396 else 397 idetim |= piix_setup_idetim_timings( 398 mode[1], 0, chp->channel); 399 end: /* 400 * timing mode is now set up in the controller. Enable 401 * it per-drive 402 */ 403 for (drive = 0; drive < 2; drive++) { 404 /* If no drive, skip */ 405 if ((drvp[drive].drive_flags & DRIVE) == 0) 406 continue; 407 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 408 if (drvp[drive].drive_flags & DRIVE_DMA) 409 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 410 } 411 if (idedma_ctl != 0) { 412 /* Add software bits in status register */ 413 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 414 idedma_ctl); 415 } 416 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 417 } 418 419 static void 420 piix3_4_setup_channel(struct wdc_channel *chp) 421 { 422 struct ata_drive_datas *drvp; 423 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 424 struct pciide_channel *cp = (struct pciide_channel*)chp; 425 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 426 int drive; 427 int channel = chp->channel; 428 429 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 430 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 431 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 432 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 433 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 434 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 435 PIIX_SIDETIM_RTC_MASK(channel)); 436 idedma_ctl = 0; 437 438 /* set up new idetim: Enable IDE registers decode */ 439 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 440 441 /* setup DMA if needed */ 442 pciide_channel_dma_setup(cp); 443 444 for (drive = 0; drive < 2; drive++) { 445 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 446 PIIX_UDMATIM_SET(0x3, channel, drive)); 447 drvp = &chp->ch_drive[drive]; 448 /* If no drive, skip */ 449 if ((drvp->drive_flags & DRIVE) == 0) 450 continue; 451 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 452 (drvp->drive_flags & DRIVE_UDMA) == 0)) 453 goto pio; 454 455 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 456 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 457 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 458 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 459 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 460 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 461 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 462 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 463 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 464 ideconf |= PIIX_CONFIG_PINGPONG; 465 } 466 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 467 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 468 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 470 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 472 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 473 /* setup Ultra/100 */ 474 if (drvp->UDMA_mode > 2 && 475 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 476 drvp->UDMA_mode = 2; 477 if (drvp->UDMA_mode > 4) { 478 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 479 } else { 480 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 481 if (drvp->UDMA_mode > 2) { 482 ideconf |= PIIX_CONFIG_UDMA66(channel, 483 drive); 484 } else { 485 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 486 drive); 487 } 488 } 489 } 490 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 491 /* setup Ultra/66 */ 492 if (drvp->UDMA_mode > 2 && 493 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 494 drvp->UDMA_mode = 2; 495 if (drvp->UDMA_mode > 2) 496 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 497 else 498 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 499 } 500 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 501 (drvp->drive_flags & DRIVE_UDMA)) { 502 /* use Ultra/DMA */ 503 drvp->drive_flags &= ~DRIVE_DMA; 504 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 505 udmareg |= PIIX_UDMATIM_SET( 506 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 507 } else { 508 /* use Multiword DMA */ 509 drvp->drive_flags &= ~DRIVE_UDMA; 510 if (drive == 0) { 511 idetim |= piix_setup_idetim_timings( 512 drvp->DMA_mode, 1, channel); 513 } else { 514 sidetim |= piix_setup_sidetim_timings( 515 drvp->DMA_mode, 1, channel); 516 idetim =PIIX_IDETIM_SET(idetim, 517 PIIX_IDETIM_SITRE, channel); 518 } 519 } 520 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 521 522 pio: /* use PIO mode */ 523 idetim |= piix_setup_idetim_drvs(drvp); 524 if (drive == 0) { 525 idetim |= piix_setup_idetim_timings( 526 drvp->PIO_mode, 0, channel); 527 } else { 528 sidetim |= piix_setup_sidetim_timings( 529 drvp->PIO_mode, 0, channel); 530 idetim =PIIX_IDETIM_SET(idetim, 531 PIIX_IDETIM_SITRE, channel); 532 } 533 } 534 if (idedma_ctl != 0) { 535 /* Add software bits in status register */ 536 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 537 idedma_ctl); 538 } 539 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 540 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 541 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 542 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 543 } 544 545 546 /* setup ISP and RTC fields, based on mode */ 547 static u_int32_t 548 piix_setup_idetim_timings(mode, dma, channel) 549 u_int8_t mode; 550 u_int8_t dma; 551 u_int8_t channel; 552 { 553 554 if (dma) 555 return PIIX_IDETIM_SET(0, 556 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 557 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 558 channel); 559 else 560 return PIIX_IDETIM_SET(0, 561 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 562 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 563 channel); 564 } 565 566 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 567 static u_int32_t 568 piix_setup_idetim_drvs(drvp) 569 struct ata_drive_datas *drvp; 570 { 571 u_int32_t ret = 0; 572 struct wdc_channel *chp = drvp->chnl_softc; 573 u_int8_t channel = chp->channel; 574 u_int8_t drive = drvp->drive; 575 576 /* 577 * If drive is using UDMA, timings setups are independant 578 * So just check DMA and PIO here. 579 */ 580 if (drvp->drive_flags & DRIVE_DMA) { 581 /* if mode = DMA mode 0, use compatible timings */ 582 if ((drvp->drive_flags & DRIVE_DMA) && 583 drvp->DMA_mode == 0) { 584 drvp->PIO_mode = 0; 585 return ret; 586 } 587 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 588 /* 589 * PIO and DMA timings are the same, use fast timings for PIO 590 * too, else use compat timings. 591 */ 592 if ((piix_isp_pio[drvp->PIO_mode] != 593 piix_isp_dma[drvp->DMA_mode]) || 594 (piix_rtc_pio[drvp->PIO_mode] != 595 piix_rtc_dma[drvp->DMA_mode])) 596 drvp->PIO_mode = 0; 597 /* if PIO mode <= 2, use compat timings for PIO */ 598 if (drvp->PIO_mode <= 2) { 599 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 600 channel); 601 return ret; 602 } 603 } 604 605 /* 606 * Now setup PIO modes. If mode < 2, use compat timings. 607 * Else enable fast timings. Enable IORDY and prefetch/post 608 * if PIO mode >= 3. 609 */ 610 611 if (drvp->PIO_mode < 2) 612 return ret; 613 614 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 615 if (drvp->PIO_mode >= 3) { 616 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 617 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 618 } 619 return ret; 620 } 621 622 /* setup values in SIDETIM registers, based on mode */ 623 static u_int32_t 624 piix_setup_sidetim_timings(mode, dma, channel) 625 u_int8_t mode; 626 u_int8_t dma; 627 u_int8_t channel; 628 { 629 if (dma) 630 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 631 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 632 else 633 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 634 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 635 } 636 637 static void 638 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 639 { 640 struct pciide_channel *cp; 641 bus_size_t cmdsize, ctlsize; 642 pcireg_t interface; 643 int channel; 644 645 if (pciide_chipen(sc, pa) == 0) 646 return; 647 648 aprint_normal("%s: bus-master DMA support present", 649 sc->sc_wdcdev.sc_dev.dv_xname); 650 pciide_mapreg_dma(sc, pa); 651 aprint_normal("\n"); 652 653 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 654 WDC_CAPABILITY_MODE; 655 sc->sc_wdcdev.PIO_cap = 4; 656 if (sc->sc_dma_ok) { 657 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 658 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 659 sc->sc_wdcdev.irqack = pciide_irqack; 660 sc->sc_wdcdev.DMA_cap = 2; 661 sc->sc_wdcdev.UDMA_cap = 6; 662 } 663 sc->sc_wdcdev.set_modes = sata_setup_channel; 664 665 sc->sc_wdcdev.channels = sc->wdc_chanarray; 666 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 667 668 interface = PCI_INTERFACE(pa->pa_class); 669 670 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 671 cp = &sc->pciide_channels[channel]; 672 if (pciide_chansetup(sc, channel, interface) == 0) 673 continue; 674 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 675 pciide_pci_intr); 676 } 677 } 678
Indexes created Mon Oct 20 16:09:52 GMT 2025