piixide.c revision 1.8.2.1.2.2
1 /* $NetBSD: piixide.c,v 1.8.2.1.2.2 2005/05/19 09:56:07 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct wdc_channel *); 43 static void piix3_4_setup_channel(struct wdc_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static int piixide_match(struct device *, struct cfdata *, void *); 50 static void piixide_attach(struct device *, struct device *, void *); 51 52 static const struct pciide_product_desc pciide_intel_products[] = { 53 { PCI_PRODUCT_INTEL_82092AA, 54 0, 55 "Intel 82092AA IDE controller", 56 default_chip_map, 57 }, 58 { PCI_PRODUCT_INTEL_82371FB_IDE, 59 0, 60 "Intel 82371FB IDE controller (PIIX)", 61 piix_chip_map, 62 }, 63 { PCI_PRODUCT_INTEL_82371SB_IDE, 64 0, 65 "Intel 82371SB IDE Interface (PIIX3)", 66 piix_chip_map, 67 }, 68 { PCI_PRODUCT_INTEL_82371AB_IDE, 69 0, 70 "Intel 82371AB IDE controller (PIIX4)", 71 piix_chip_map, 72 }, 73 { PCI_PRODUCT_INTEL_82440MX_IDE, 74 0, 75 "Intel 82440MX IDE controller", 76 piix_chip_map 77 }, 78 { PCI_PRODUCT_INTEL_82801AA_IDE, 79 0, 80 "Intel 82801AA IDE Controller (ICH)", 81 piix_chip_map, 82 }, 83 { PCI_PRODUCT_INTEL_82801AB_IDE, 84 0, 85 "Intel 82801AB IDE Controller (ICH0)", 86 piix_chip_map, 87 }, 88 { PCI_PRODUCT_INTEL_82801BA_IDE, 89 0, 90 "Intel 82801BA IDE Controller (ICH2)", 91 piix_chip_map, 92 }, 93 { PCI_PRODUCT_INTEL_82801BAM_IDE, 94 0, 95 "Intel 82801BAM IDE Controller (ICH2-M)", 96 piix_chip_map, 97 }, 98 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 99 0, 100 "Intel 82801CA IDE Controller (ICH3)", 101 piix_chip_map, 102 }, 103 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 104 0, 105 "Intel 82801CA IDE Controller (ICH3)", 106 piix_chip_map, 107 }, 108 { PCI_PRODUCT_INTEL_82801DB_IDE, 109 0, 110 "Intel 82801DB IDE Controller (ICH4)", 111 piix_chip_map, 112 }, 113 { PCI_PRODUCT_INTEL_82801DBM_IDE, 114 0, 115 "Intel 82801DBM IDE Controller (ICH4-M)", 116 piix_chip_map, 117 }, 118 { PCI_PRODUCT_INTEL_82801EB_IDE, 119 0, 120 "Intel 82801EB IDE Controller (ICH5)", 121 piix_chip_map, 122 }, 123 { PCI_PRODUCT_INTEL_82801EB_SATA, 124 0, 125 "Intel 82801EB Serial ATA Controller", 126 piixsata_chip_map, 127 }, 128 { PCI_PRODUCT_INTEL_82801ER_SATA, 129 0, 130 "Intel 82801ER Serial ATA/Raid Controller", 131 piixsata_chip_map, 132 }, 133 { PCI_PRODUCT_INTEL_6300ESB_IDE, 134 0, 135 "Intel 6300ESB IDE Controller (ICH5)", 136 piix_chip_map, 137 }, 138 { PCI_PRODUCT_INTEL_6300ESB_SATA, 139 0, 140 "Intel 6300ESB Serial ATA Controller", 141 piixsata_chip_map, 142 }, 143 { PCI_PRODUCT_INTEL_82801FB_IDE, 144 0, 145 "Intel 82801FB IDE Controller (ICH6)", 146 piix_chip_map, 147 }, 148 { PCI_PRODUCT_INTEL_82801FB_SATA, 149 0, 150 "Intel 82801FB Serial ATA/Raid Controller", 151 piixsata_chip_map, 152 }, 153 { PCI_PRODUCT_INTEL_82801FR_SATA, 154 0, 155 "Intel 82801FR Serial ATA/Raid Controller", 156 piixsata_chip_map, 157 }, 158 { 0, 159 0, 160 NULL, 161 NULL 162 } 163 }; 164 165 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 166 piixide_match, piixide_attach, NULL, NULL); 167 168 static int 169 piixide_match(struct device *parent, struct cfdata *match, void *aux) 170 { 171 struct pci_attach_args *pa = aux; 172 173 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 174 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 175 return (2); 176 } 177 return (0); 178 } 179 180 static void 181 piixide_attach(struct device *parent, struct device *self, void *aux) 182 { 183 struct pci_attach_args *pa = aux; 184 struct pciide_softc *sc = (struct pciide_softc *)self; 185 186 pciide_common_attach(sc, pa, 187 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 188 189 } 190 191 static void 192 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 193 { 194 struct pciide_channel *cp; 195 int channel; 196 u_int32_t idetim; 197 bus_size_t cmdsize, ctlsize; 198 199 if (pciide_chipen(sc, pa) == 0) 200 return; 201 202 aprint_normal("%s: bus-master DMA support present", 203 sc->sc_wdcdev.sc_dev.dv_xname); 204 pciide_mapreg_dma(sc, pa); 205 aprint_normal("\n"); 206 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 207 WDC_CAPABILITY_MODE; 208 if (sc->sc_dma_ok) { 209 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 210 sc->sc_wdcdev.irqack = pciide_irqack; 211 switch(sc->sc_pp->ide_product) { 212 case PCI_PRODUCT_INTEL_82371AB_IDE: 213 case PCI_PRODUCT_INTEL_82440MX_IDE: 214 case PCI_PRODUCT_INTEL_82801AA_IDE: 215 case PCI_PRODUCT_INTEL_82801AB_IDE: 216 case PCI_PRODUCT_INTEL_82801BA_IDE: 217 case PCI_PRODUCT_INTEL_82801BAM_IDE: 218 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 219 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 220 case PCI_PRODUCT_INTEL_82801DB_IDE: 221 case PCI_PRODUCT_INTEL_82801DBM_IDE: 222 case PCI_PRODUCT_INTEL_82801EB_IDE: 223 case PCI_PRODUCT_INTEL_6300ESB_IDE: 224 case PCI_PRODUCT_INTEL_82801FB_IDE: 225 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 226 } 227 } 228 sc->sc_wdcdev.PIO_cap = 4; 229 sc->sc_wdcdev.DMA_cap = 2; 230 switch(sc->sc_pp->ide_product) { 231 case PCI_PRODUCT_INTEL_82801AA_IDE: 232 sc->sc_wdcdev.UDMA_cap = 4; 233 break; 234 case PCI_PRODUCT_INTEL_82801BA_IDE: 235 case PCI_PRODUCT_INTEL_82801BAM_IDE: 236 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 237 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 238 case PCI_PRODUCT_INTEL_82801DB_IDE: 239 case PCI_PRODUCT_INTEL_82801DBM_IDE: 240 case PCI_PRODUCT_INTEL_82801EB_IDE: 241 case PCI_PRODUCT_INTEL_6300ESB_IDE: 242 case PCI_PRODUCT_INTEL_82801FB_IDE: 243 sc->sc_wdcdev.UDMA_cap = 5; 244 break; 245 default: 246 sc->sc_wdcdev.UDMA_cap = 2; 247 } 248 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 249 sc->sc_wdcdev.set_modes = piix_setup_channel; 250 else 251 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 252 sc->sc_wdcdev.channels = sc->wdc_chanarray; 253 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 254 255 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 256 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 257 DEBUG_PROBE); 258 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 259 WDCDEBUG_PRINT((", sidetim=0x%x", 260 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 261 DEBUG_PROBE); 262 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 263 WDCDEBUG_PRINT((", udamreg 0x%x", 264 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 265 DEBUG_PROBE); 266 } 267 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 268 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 269 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 270 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 271 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 272 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 273 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 274 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 275 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 276 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 277 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 278 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 279 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 280 DEBUG_PROBE); 281 } 282 283 } 284 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 285 286 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 287 cp = &sc->pciide_channels[channel]; 288 /* PIIX is compat-only */ 289 if (pciide_chansetup(sc, channel, 0) == 0) 290 continue; 291 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 292 if ((PIIX_IDETIM_READ(idetim, channel) & 293 PIIX_IDETIM_IDE) == 0) { 294 #if 1 295 aprint_normal("%s: %s channel ignored (disabled)\n", 296 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 297 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 298 continue; 299 #else 300 pcireg_t interface; 301 302 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 303 channel); 304 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 305 idetim); 306 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 307 sc->sc_tag, PCI_CLASS_REG)); 308 aprint_normal("channel %d idetim=%08x interface=%02x\n", 309 channel, idetim, interface); 310 #endif 311 } 312 /* PIIX are compat-only pciide devices */ 313 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 314 } 315 316 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 317 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 318 DEBUG_PROBE); 319 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 320 WDCDEBUG_PRINT((", sidetim=0x%x", 321 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 322 DEBUG_PROBE); 323 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 324 WDCDEBUG_PRINT((", udamreg 0x%x", 325 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 326 DEBUG_PROBE); 327 } 328 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 329 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 330 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 331 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 332 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 333 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 334 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 335 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 336 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 337 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 338 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 339 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 340 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 341 DEBUG_PROBE); 342 } 343 } 344 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 345 } 346 347 static void 348 piix_setup_channel(struct wdc_channel *chp) 349 { 350 u_int8_t mode[2], drive; 351 u_int32_t oidetim, idetim, idedma_ctl; 352 struct pciide_channel *cp = (struct pciide_channel*)chp; 353 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 354 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 355 356 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 357 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 358 idedma_ctl = 0; 359 360 /* set up new idetim: Enable IDE registers decode */ 361 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 362 chp->ch_channel); 363 364 /* setup DMA */ 365 pciide_channel_dma_setup(cp); 366 367 /* 368 * Here we have to mess up with drives mode: PIIX can't have 369 * different timings for master and slave drives. 370 * We need to find the best combination. 371 */ 372 373 /* If both drives supports DMA, take the lower mode */ 374 if ((drvp[0].drive_flags & DRIVE_DMA) && 375 (drvp[1].drive_flags & DRIVE_DMA)) { 376 mode[0] = mode[1] = 377 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 378 drvp[0].DMA_mode = mode[0]; 379 drvp[1].DMA_mode = mode[1]; 380 goto ok; 381 } 382 /* 383 * If only one drive supports DMA, use its mode, and 384 * put the other one in PIO mode 0 if mode not compatible 385 */ 386 if (drvp[0].drive_flags & DRIVE_DMA) { 387 mode[0] = drvp[0].DMA_mode; 388 mode[1] = drvp[1].PIO_mode; 389 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 390 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 391 mode[1] = drvp[1].PIO_mode = 0; 392 goto ok; 393 } 394 if (drvp[1].drive_flags & DRIVE_DMA) { 395 mode[1] = drvp[1].DMA_mode; 396 mode[0] = drvp[0].PIO_mode; 397 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 398 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 399 mode[0] = drvp[0].PIO_mode = 0; 400 goto ok; 401 } 402 /* 403 * If both drives are not DMA, takes the lower mode, unless 404 * one of them is PIO mode < 2 405 */ 406 if (drvp[0].PIO_mode < 2) { 407 mode[0] = drvp[0].PIO_mode = 0; 408 mode[1] = drvp[1].PIO_mode; 409 } else if (drvp[1].PIO_mode < 2) { 410 mode[1] = drvp[1].PIO_mode = 0; 411 mode[0] = drvp[0].PIO_mode; 412 } else { 413 mode[0] = mode[1] = 414 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 415 drvp[0].PIO_mode = mode[0]; 416 drvp[1].PIO_mode = mode[1]; 417 } 418 ok: /* The modes are setup */ 419 for (drive = 0; drive < 2; drive++) { 420 if (drvp[drive].drive_flags & DRIVE_DMA) { 421 idetim |= piix_setup_idetim_timings( 422 mode[drive], 1, chp->ch_channel); 423 goto end; 424 } 425 } 426 /* If we are there, none of the drives are DMA */ 427 if (mode[0] >= 2) 428 idetim |= piix_setup_idetim_timings( 429 mode[0], 0, chp->ch_channel); 430 else 431 idetim |= piix_setup_idetim_timings( 432 mode[1], 0, chp->ch_channel); 433 end: /* 434 * timing mode is now set up in the controller. Enable 435 * it per-drive 436 */ 437 for (drive = 0; drive < 2; drive++) { 438 /* If no drive, skip */ 439 if ((drvp[drive].drive_flags & DRIVE) == 0) 440 continue; 441 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 442 if (drvp[drive].drive_flags & DRIVE_DMA) 443 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 444 } 445 if (idedma_ctl != 0) { 446 /* Add software bits in status register */ 447 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 448 idedma_ctl); 449 } 450 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 451 } 452 453 static void 454 piix3_4_setup_channel(struct wdc_channel *chp) 455 { 456 struct ata_drive_datas *drvp; 457 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 458 struct pciide_channel *cp = (struct pciide_channel*)chp; 459 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 460 struct wdc_softc *wdc = &sc->sc_wdcdev; 461 int drive; 462 int channel = chp->ch_channel; 463 464 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 465 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 466 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 467 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 468 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 469 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 470 PIIX_SIDETIM_RTC_MASK(channel)); 471 idedma_ctl = 0; 472 473 /* set up new idetim: Enable IDE registers decode */ 474 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 475 476 /* setup DMA if needed */ 477 pciide_channel_dma_setup(cp); 478 479 for (drive = 0; drive < 2; drive++) { 480 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 481 PIIX_UDMATIM_SET(0x3, channel, drive)); 482 drvp = &chp->ch_drive[drive]; 483 /* If no drive, skip */ 484 if ((drvp->drive_flags & DRIVE) == 0) 485 continue; 486 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 487 (drvp->drive_flags & DRIVE_UDMA) == 0)) 488 goto pio; 489 490 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 491 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 492 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 493 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 494 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 495 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 496 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 497 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 498 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 499 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 500 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 501 ideconf |= PIIX_CONFIG_PINGPONG; 502 } 503 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 504 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 505 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 506 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 507 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 508 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 509 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 510 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 511 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 512 /* setup Ultra/100 */ 513 if (drvp->UDMA_mode > 2 && 514 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 515 drvp->UDMA_mode = 2; 516 if (drvp->UDMA_mode > 4) { 517 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 518 } else { 519 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 520 if (drvp->UDMA_mode > 2) { 521 ideconf |= PIIX_CONFIG_UDMA66(channel, 522 drive); 523 } else { 524 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 525 drive); 526 } 527 } 528 } 529 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 530 /* setup Ultra/66 */ 531 if (drvp->UDMA_mode > 2 && 532 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 533 drvp->UDMA_mode = 2; 534 if (drvp->UDMA_mode > 2) 535 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 536 else 537 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 538 } 539 if ((wdc->cap & WDC_CAPABILITY_UDMA) && 540 (drvp->drive_flags & DRIVE_UDMA)) { 541 /* use Ultra/DMA */ 542 drvp->drive_flags &= ~DRIVE_DMA; 543 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 544 udmareg |= PIIX_UDMATIM_SET( 545 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 546 } else { 547 /* use Multiword DMA */ 548 drvp->drive_flags &= ~DRIVE_UDMA; 549 if (drive == 0) { 550 idetim |= piix_setup_idetim_timings( 551 drvp->DMA_mode, 1, channel); 552 } else { 553 sidetim |= piix_setup_sidetim_timings( 554 drvp->DMA_mode, 1, channel); 555 idetim =PIIX_IDETIM_SET(idetim, 556 PIIX_IDETIM_SITRE, channel); 557 } 558 } 559 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 560 561 pio: /* use PIO mode */ 562 idetim |= piix_setup_idetim_drvs(drvp); 563 if (drive == 0) { 564 idetim |= piix_setup_idetim_timings( 565 drvp->PIO_mode, 0, channel); 566 } else { 567 sidetim |= piix_setup_sidetim_timings( 568 drvp->PIO_mode, 0, channel); 569 idetim =PIIX_IDETIM_SET(idetim, 570 PIIX_IDETIM_SITRE, channel); 571 } 572 } 573 if (idedma_ctl != 0) { 574 /* Add software bits in status register */ 575 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 576 idedma_ctl); 577 } 578 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 579 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 580 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 581 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 582 } 583 584 585 /* setup ISP and RTC fields, based on mode */ 586 static u_int32_t 587 piix_setup_idetim_timings(mode, dma, channel) 588 u_int8_t mode; 589 u_int8_t dma; 590 u_int8_t channel; 591 { 592 593 if (dma) 594 return PIIX_IDETIM_SET(0, 595 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 596 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 597 channel); 598 else 599 return PIIX_IDETIM_SET(0, 600 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 601 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 602 channel); 603 } 604 605 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 606 static u_int32_t 607 piix_setup_idetim_drvs(drvp) 608 struct ata_drive_datas *drvp; 609 { 610 u_int32_t ret = 0; 611 struct wdc_channel *chp = drvp->chnl_softc; 612 u_int8_t channel = chp->ch_channel; 613 u_int8_t drive = drvp->drive; 614 615 /* 616 * If drive is using UDMA, timings setups are independant 617 * So just check DMA and PIO here. 618 */ 619 if (drvp->drive_flags & DRIVE_DMA) { 620 /* if mode = DMA mode 0, use compatible timings */ 621 if ((drvp->drive_flags & DRIVE_DMA) && 622 drvp->DMA_mode == 0) { 623 drvp->PIO_mode = 0; 624 return ret; 625 } 626 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 627 /* 628 * PIO and DMA timings are the same, use fast timings for PIO 629 * too, else use compat timings. 630 */ 631 if ((piix_isp_pio[drvp->PIO_mode] != 632 piix_isp_dma[drvp->DMA_mode]) || 633 (piix_rtc_pio[drvp->PIO_mode] != 634 piix_rtc_dma[drvp->DMA_mode])) 635 drvp->PIO_mode = 0; 636 /* if PIO mode <= 2, use compat timings for PIO */ 637 if (drvp->PIO_mode <= 2) { 638 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 639 channel); 640 return ret; 641 } 642 } 643 644 /* 645 * Now setup PIO modes. If mode < 2, use compat timings. 646 * Else enable fast timings. Enable IORDY and prefetch/post 647 * if PIO mode >= 3. 648 */ 649 650 if (drvp->PIO_mode < 2) 651 return ret; 652 653 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 654 if (drvp->PIO_mode >= 3) { 655 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 656 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 657 } 658 return ret; 659 } 660 661 /* setup values in SIDETIM registers, based on mode */ 662 static u_int32_t 663 piix_setup_sidetim_timings(mode, dma, channel) 664 u_int8_t mode; 665 u_int8_t dma; 666 u_int8_t channel; 667 { 668 if (dma) 669 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 670 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 671 else 672 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 673 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 674 } 675 676 static void 677 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 678 { 679 struct pciide_channel *cp; 680 bus_size_t cmdsize, ctlsize; 681 pcireg_t interface; 682 int channel; 683 684 if (pciide_chipen(sc, pa) == 0) 685 return; 686 687 aprint_normal("%s: bus-master DMA support present", 688 sc->sc_wdcdev.sc_dev.dv_xname); 689 pciide_mapreg_dma(sc, pa); 690 aprint_normal("\n"); 691 692 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 693 WDC_CAPABILITY_MODE; 694 sc->sc_wdcdev.PIO_cap = 4; 695 if (sc->sc_dma_ok) { 696 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 697 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 698 sc->sc_wdcdev.irqack = pciide_irqack; 699 sc->sc_wdcdev.DMA_cap = 2; 700 sc->sc_wdcdev.UDMA_cap = 6; 701 } 702 sc->sc_wdcdev.set_modes = sata_setup_channel; 703 704 sc->sc_wdcdev.channels = sc->wdc_chanarray; 705 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 706 707 interface = PCI_INTERFACE(pa->pa_class); 708 709 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 710 cp = &sc->pciide_channels[channel]; 711 if (pciide_chansetup(sc, channel, interface) == 0) 712 continue; 713 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 714 pciide_pci_intr); 715 } 716 } 717
Indexes created Wed Oct 15 16:09:53 GMT 2025