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piixide.c revision 1.8.2.1.2.4
      1 /*	$NetBSD: piixide.c,v 1.8.2.1.2.4 2005/08/22 21:55:01 riz Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Manuel Bouyer.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/param.h>
     33 #include <sys/systm.h>
     34 
     35 #include <dev/pci/pcivar.h>
     36 #include <dev/pci/pcidevs.h>
     37 #include <dev/pci/pciidereg.h>
     38 #include <dev/pci/pciidevar.h>
     39 #include <dev/pci/pciide_piix_reg.h>
     40 
     41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *);
     42 static void piix_setup_channel(struct wdc_channel *);
     43 static void piix3_4_setup_channel(struct wdc_channel *);
     44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t);
     45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *);
     46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t);
     47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *);
     48 
     49 static int  piixide_match(struct device *, struct cfdata *, void *);
     50 static void piixide_attach(struct device *, struct device *, void *);
     51 
     52 static const struct pciide_product_desc pciide_intel_products[] =  {
     53 	{ PCI_PRODUCT_INTEL_82092AA,
     54 	  0,
     55 	  "Intel 82092AA IDE controller",
     56 	  default_chip_map,
     57 	},
     58 	{ PCI_PRODUCT_INTEL_82371FB_IDE,
     59 	  0,
     60 	  "Intel 82371FB IDE controller (PIIX)",
     61 	  piix_chip_map,
     62 	},
     63 	{ PCI_PRODUCT_INTEL_82371SB_IDE,
     64 	  0,
     65 	  "Intel 82371SB IDE Interface (PIIX3)",
     66 	  piix_chip_map,
     67 	},
     68 	{ PCI_PRODUCT_INTEL_82371AB_IDE,
     69 	  0,
     70 	  "Intel 82371AB IDE controller (PIIX4)",
     71 	  piix_chip_map,
     72 	},
     73 	{ PCI_PRODUCT_INTEL_82440MX_IDE,
     74 	  0,
     75 	  "Intel 82440MX IDE controller",
     76 	  piix_chip_map
     77 	},
     78 	{ PCI_PRODUCT_INTEL_82801AA_IDE,
     79 	  0,
     80 	  "Intel 82801AA IDE Controller (ICH)",
     81 	  piix_chip_map,
     82 	},
     83 	{ PCI_PRODUCT_INTEL_82801AB_IDE,
     84 	  0,
     85 	  "Intel 82801AB IDE Controller (ICH0)",
     86 	  piix_chip_map,
     87 	},
     88 	{ PCI_PRODUCT_INTEL_82801BA_IDE,
     89 	  0,
     90 	  "Intel 82801BA IDE Controller (ICH2)",
     91 	  piix_chip_map,
     92 	},
     93 	{ PCI_PRODUCT_INTEL_82801BAM_IDE,
     94 	  0,
     95 	  "Intel 82801BAM IDE Controller (ICH2-M)",
     96 	  piix_chip_map,
     97 	},
     98 	{ PCI_PRODUCT_INTEL_82801CA_IDE_1,
     99 	  0,
    100 	  "Intel 82801CA IDE Controller (ICH3)",
    101 	  piix_chip_map,
    102 	},
    103 	{ PCI_PRODUCT_INTEL_82801CA_IDE_2,
    104 	  0,
    105 	  "Intel 82801CA IDE Controller (ICH3)",
    106 	  piix_chip_map,
    107 	},
    108 	{ PCI_PRODUCT_INTEL_82801DB_IDE,
    109 	  0,
    110 	  "Intel 82801DB IDE Controller (ICH4)",
    111 	  piix_chip_map,
    112 	},
    113 	{ PCI_PRODUCT_INTEL_82801DBM_IDE,
    114 	  0,
    115 	  "Intel 82801DBM IDE Controller (ICH4-M)",
    116 	  piix_chip_map,
    117 	},
    118 	{ PCI_PRODUCT_INTEL_82801EB_IDE,
    119 	  0,
    120 	  "Intel 82801EB IDE Controller (ICH5)",
    121 	  piix_chip_map,
    122 	},
    123 	{ PCI_PRODUCT_INTEL_82801EB_SATA,
    124 	  0,
    125 	  "Intel 82801EB Serial ATA Controller",
    126 	  piixsata_chip_map,
    127 	},
    128 	{ PCI_PRODUCT_INTEL_82801ER_SATA,
    129 	  0,
    130 	  "Intel 82801ER Serial ATA/Raid Controller",
    131 	  piixsata_chip_map,
    132 	},
    133 	{ PCI_PRODUCT_INTEL_6300ESB_IDE,
    134 	  0,
    135 	  "Intel 6300ESB IDE Controller (ICH5)",
    136 	  piix_chip_map,
    137 	},
    138 	{ PCI_PRODUCT_INTEL_6300ESB_SATA,
    139 	  0,
    140 	  "Intel 6300ESB Serial ATA Controller",
    141 	  piixsata_chip_map,
    142 	},
    143 	{ PCI_PRODUCT_INTEL_82801FB_IDE,
    144 	  0,
    145 	  "Intel 82801FB IDE Controller (ICH6)",
    146 	  piix_chip_map,
    147 	},
    148 	{ PCI_PRODUCT_INTEL_82801FB_SATA,
    149 	  0,
    150 	  "Intel 82801FB Serial ATA/Raid Controller",
    151 	  piixsata_chip_map,
    152 	},
    153 	{ PCI_PRODUCT_INTEL_82801FR_SATA,
    154 	  0,
    155 	  "Intel 82801FR Serial ATA/Raid Controller",
    156 	  piixsata_chip_map,
    157 	},
    158 	{ PCI_PRODUCT_INTEL_82801FBM_SATA,
    159 	  0,
    160 	  "Intel 82801FBM Serial ATA Controller (ICH6)",
    161 	  piixsata_chip_map,
    162 	},
    163 	{ 0,
    164 	  0,
    165 	  NULL,
    166 	  NULL
    167 	}
    168 };
    169 
    170 CFATTACH_DECL(piixide, sizeof(struct pciide_softc),
    171     piixide_match, piixide_attach, NULL, NULL);
    172 
    173 static int
    174 piixide_match(struct device *parent, struct cfdata *match, void *aux)
    175 {
    176 	struct pci_attach_args *pa = aux;
    177 
    178 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
    179 		if (pciide_lookup_product(pa->pa_id, pciide_intel_products))
    180 			return (2);
    181 	}
    182 	return (0);
    183 }
    184 
    185 static void
    186 piixide_attach(struct device *parent, struct device *self, void *aux)
    187 {
    188 	struct pci_attach_args *pa = aux;
    189 	struct pciide_softc *sc = (struct pciide_softc *)self;
    190 
    191 	pciide_common_attach(sc, pa,
    192 	    pciide_lookup_product(pa->pa_id, pciide_intel_products));
    193 
    194 }
    195 
    196 static void
    197 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
    198 {
    199 	struct pciide_channel *cp;
    200 	int channel;
    201 	u_int32_t idetim;
    202 	bus_size_t cmdsize, ctlsize;
    203 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
    204 
    205 	if (pciide_chipen(sc, pa) == 0)
    206 		return;
    207 
    208 	aprint_normal("%s: bus-master DMA support present",
    209 	    sc->sc_wdcdev.sc_dev.dv_xname);
    210 	pciide_mapreg_dma(sc, pa);
    211 	aprint_normal("\n");
    212 	sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
    213 	    WDC_CAPABILITY_MODE;
    214 	if (sc->sc_dma_ok) {
    215 		sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
    216 		sc->sc_wdcdev.irqack = pciide_irqack;
    217 		switch(sc->sc_pp->ide_product) {
    218 		case PCI_PRODUCT_INTEL_82371AB_IDE:
    219 		case PCI_PRODUCT_INTEL_82440MX_IDE:
    220 		case PCI_PRODUCT_INTEL_82801AA_IDE:
    221 		case PCI_PRODUCT_INTEL_82801AB_IDE:
    222 		case PCI_PRODUCT_INTEL_82801BA_IDE:
    223 		case PCI_PRODUCT_INTEL_82801BAM_IDE:
    224 		case PCI_PRODUCT_INTEL_82801CA_IDE_1:
    225 		case PCI_PRODUCT_INTEL_82801CA_IDE_2:
    226 		case PCI_PRODUCT_INTEL_82801DB_IDE:
    227 		case PCI_PRODUCT_INTEL_82801DBM_IDE:
    228 		case PCI_PRODUCT_INTEL_82801EB_IDE:
    229 		case PCI_PRODUCT_INTEL_6300ESB_IDE:
    230 		case PCI_PRODUCT_INTEL_82801FB_IDE:
    231 			sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
    232 		}
    233 	}
    234 	sc->sc_wdcdev.PIO_cap = 4;
    235 	sc->sc_wdcdev.DMA_cap = 2;
    236 	switch(sc->sc_pp->ide_product) {
    237 	case PCI_PRODUCT_INTEL_82801AA_IDE:
    238 		sc->sc_wdcdev.UDMA_cap = 4;
    239 		break;
    240 	case PCI_PRODUCT_INTEL_82801BA_IDE:
    241 	case PCI_PRODUCT_INTEL_82801BAM_IDE:
    242 	case PCI_PRODUCT_INTEL_82801CA_IDE_1:
    243 	case PCI_PRODUCT_INTEL_82801CA_IDE_2:
    244 	case PCI_PRODUCT_INTEL_82801DB_IDE:
    245 	case PCI_PRODUCT_INTEL_82801DBM_IDE:
    246 	case PCI_PRODUCT_INTEL_82801EB_IDE:
    247 	case PCI_PRODUCT_INTEL_6300ESB_IDE:
    248 	case PCI_PRODUCT_INTEL_82801FB_IDE:
    249 		sc->sc_wdcdev.UDMA_cap = 5;
    250 		break;
    251 	default:
    252 		sc->sc_wdcdev.UDMA_cap = 2;
    253 	}
    254 	if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE)
    255 		sc->sc_wdcdev.set_modes = piix_setup_channel;
    256 	else
    257 		sc->sc_wdcdev.set_modes = piix3_4_setup_channel;
    258 	sc->sc_wdcdev.channels = sc->wdc_chanarray;
    259 	sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
    260 
    261 	WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x",
    262 	    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
    263 	    DEBUG_PROBE);
    264 	if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
    265 		WDCDEBUG_PRINT((", sidetim=0x%x",
    266 		    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
    267 		    DEBUG_PROBE);
    268 		if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
    269 			WDCDEBUG_PRINT((", udamreg 0x%x",
    270 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
    271 			    DEBUG_PROBE);
    272 		}
    273 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
    274 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
    275 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
    276 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
    277 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
    278 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
    279 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
    280 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
    281 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
    282 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
    283 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
    284 			WDCDEBUG_PRINT((", IDE_CONTROL 0x%x",
    285 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
    286 			    DEBUG_PROBE);
    287 		}
    288 
    289 	}
    290 	WDCDEBUG_PRINT(("\n"), DEBUG_PROBE);
    291 
    292 	for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
    293 		cp = &sc->pciide_channels[channel];
    294 		if (pciide_chansetup(sc, channel, interface) == 0)
    295 			continue;
    296 		idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
    297 		if ((PIIX_IDETIM_READ(idetim, channel) &
    298 		    PIIX_IDETIM_IDE) == 0) {
    299 #if 1
    300 			aprint_normal("%s: %s channel ignored (disabled)\n",
    301 			    sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
    302 			cp->wdc_channel.ch_flags |= WDCF_DISABLED;
    303 			continue;
    304 #else
    305 			pcireg_t interface;
    306 
    307 			idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
    308 			    channel);
    309 			pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM,
    310 			    idetim);
    311 			interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc,
    312 			    sc->sc_tag, PCI_CLASS_REG));
    313 			aprint_normal("channel %d idetim=%08x interface=%02x\n",
    314 			    channel, idetim, interface);
    315 #endif
    316 		}
    317 		pciide_mapchan(pa, cp, interface,
    318 		    &cmdsize, &ctlsize, pciide_pci_intr);
    319 	}
    320 
    321 	WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x",
    322 	    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)),
    323 	    DEBUG_PROBE);
    324 	if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) {
    325 		WDCDEBUG_PRINT((", sidetim=0x%x",
    326 		    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)),
    327 		    DEBUG_PROBE);
    328 		if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
    329 			WDCDEBUG_PRINT((", udamreg 0x%x",
    330 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)),
    331 			    DEBUG_PROBE);
    332 		}
    333 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
    334 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
    335 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
    336 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
    337 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
    338 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
    339 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
    340 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
    341 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
    342 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
    343 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
    344 			WDCDEBUG_PRINT((", IDE_CONTROL 0x%x",
    345 			    pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)),
    346 			    DEBUG_PROBE);
    347 		}
    348 	}
    349 	WDCDEBUG_PRINT(("\n"), DEBUG_PROBE);
    350 }
    351 
    352 static void
    353 piix_setup_channel(struct wdc_channel *chp)
    354 {
    355 	u_int8_t mode[2], drive;
    356 	u_int32_t oidetim, idetim, idedma_ctl;
    357 	struct pciide_channel *cp = (struct pciide_channel*)chp;
    358 	struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc;
    359 	struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive;
    360 
    361 	oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
    362 	idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel);
    363 	idedma_ctl = 0;
    364 
    365 	/* set up new idetim: Enable IDE registers decode */
    366 	idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE,
    367 	    chp->ch_channel);
    368 
    369 	/* setup DMA */
    370 	pciide_channel_dma_setup(cp);
    371 
    372 	/*
    373 	 * Here we have to mess up with drives mode: PIIX can't have
    374 	 * different timings for master and slave drives.
    375 	 * We need to find the best combination.
    376 	 */
    377 
    378 	/* If both drives supports DMA, take the lower mode */
    379 	if ((drvp[0].drive_flags & DRIVE_DMA) &&
    380 	    (drvp[1].drive_flags & DRIVE_DMA)) {
    381 		mode[0] = mode[1] =
    382 		    min(drvp[0].DMA_mode, drvp[1].DMA_mode);
    383 		    drvp[0].DMA_mode = mode[0];
    384 		    drvp[1].DMA_mode = mode[1];
    385 		goto ok;
    386 	}
    387 	/*
    388 	 * If only one drive supports DMA, use its mode, and
    389 	 * put the other one in PIO mode 0 if mode not compatible
    390 	 */
    391 	if (drvp[0].drive_flags & DRIVE_DMA) {
    392 		mode[0] = drvp[0].DMA_mode;
    393 		mode[1] = drvp[1].PIO_mode;
    394 		if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] ||
    395 		    piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]])
    396 			mode[1] = drvp[1].PIO_mode = 0;
    397 		goto ok;
    398 	}
    399 	if (drvp[1].drive_flags & DRIVE_DMA) {
    400 		mode[1] = drvp[1].DMA_mode;
    401 		mode[0] = drvp[0].PIO_mode;
    402 		if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] ||
    403 		    piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]])
    404 			mode[0] = drvp[0].PIO_mode = 0;
    405 		goto ok;
    406 	}
    407 	/*
    408 	 * If both drives are not DMA, takes the lower mode, unless
    409 	 * one of them is PIO mode < 2
    410 	 */
    411 	if (drvp[0].PIO_mode < 2) {
    412 		mode[0] = drvp[0].PIO_mode = 0;
    413 		mode[1] = drvp[1].PIO_mode;
    414 	} else if (drvp[1].PIO_mode < 2) {
    415 		mode[1] = drvp[1].PIO_mode = 0;
    416 		mode[0] = drvp[0].PIO_mode;
    417 	} else {
    418 		mode[0] = mode[1] =
    419 		    min(drvp[1].PIO_mode, drvp[0].PIO_mode);
    420 		drvp[0].PIO_mode = mode[0];
    421 		drvp[1].PIO_mode = mode[1];
    422 	}
    423 ok:	/* The modes are setup */
    424 	for (drive = 0; drive < 2; drive++) {
    425 		if (drvp[drive].drive_flags & DRIVE_DMA) {
    426 			idetim |= piix_setup_idetim_timings(
    427 			    mode[drive], 1, chp->ch_channel);
    428 			goto end;
    429 		}
    430 	}
    431 	/* If we are there, none of the drives are DMA */
    432 	if (mode[0] >= 2)
    433 		idetim |= piix_setup_idetim_timings(
    434 		    mode[0], 0, chp->ch_channel);
    435 	else
    436 		idetim |= piix_setup_idetim_timings(
    437 		    mode[1], 0, chp->ch_channel);
    438 end:	/*
    439 	 * timing mode is now set up in the controller. Enable
    440 	 * it per-drive
    441 	 */
    442 	for (drive = 0; drive < 2; drive++) {
    443 		/* If no drive, skip */
    444 		if ((drvp[drive].drive_flags & DRIVE) == 0)
    445 			continue;
    446 		idetim |= piix_setup_idetim_drvs(&drvp[drive]);
    447 		if (drvp[drive].drive_flags & DRIVE_DMA)
    448 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    449 	}
    450 	if (idedma_ctl != 0) {
    451 		/* Add software bits in status register */
    452 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    453 		    idedma_ctl);
    454 	}
    455 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
    456 }
    457 
    458 static void
    459 piix3_4_setup_channel(struct wdc_channel *chp)
    460 {
    461 	struct ata_drive_datas *drvp;
    462 	u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl;
    463 	struct pciide_channel *cp = (struct pciide_channel*)chp;
    464 	struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc;
    465 	struct wdc_softc *wdc = &sc->sc_wdcdev;
    466 	int drive;
    467 	int channel = chp->ch_channel;
    468 
    469 	oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM);
    470 	sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM);
    471 	udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG);
    472 	ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG);
    473 	idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel);
    474 	sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) |
    475 	    PIIX_SIDETIM_RTC_MASK(channel));
    476 	idedma_ctl = 0;
    477 
    478 	/* set up new idetim: Enable IDE registers decode */
    479 	idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel);
    480 
    481 	/* setup DMA if needed */
    482 	pciide_channel_dma_setup(cp);
    483 
    484 	for (drive = 0; drive < 2; drive++) {
    485 		udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) |
    486 		    PIIX_UDMATIM_SET(0x3, channel, drive));
    487 		drvp = &chp->ch_drive[drive];
    488 		/* If no drive, skip */
    489 		if ((drvp->drive_flags & DRIVE) == 0)
    490 			continue;
    491 		if (((drvp->drive_flags & DRIVE_DMA) == 0 &&
    492 		    (drvp->drive_flags & DRIVE_UDMA) == 0))
    493 			goto pio;
    494 
    495 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE ||
    496 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE ||
    497 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
    498 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
    499 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
    500 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
    501 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
    502 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
    503 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
    504 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
    505 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
    506 			ideconf |= PIIX_CONFIG_PINGPONG;
    507 		}
    508 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE ||
    509 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE ||
    510 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 ||
    511 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 ||
    512 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE ||
    513 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE ||
    514 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ||
    515 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE ||
    516 		    sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) {
    517 			/* setup Ultra/100 */
    518 			if (drvp->UDMA_mode > 2 &&
    519 			    (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
    520 				drvp->UDMA_mode = 2;
    521 			if (drvp->UDMA_mode > 4) {
    522 				ideconf |= PIIX_CONFIG_UDMA100(channel, drive);
    523 			} else {
    524 				ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive);
    525 				if (drvp->UDMA_mode > 2) {
    526 					ideconf |= PIIX_CONFIG_UDMA66(channel,
    527 					    drive);
    528 				} else {
    529 					ideconf &= ~PIIX_CONFIG_UDMA66(channel,
    530 					    drive);
    531 				}
    532 			}
    533 		}
    534 		if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) {
    535 			/* setup Ultra/66 */
    536 			if (drvp->UDMA_mode > 2 &&
    537 			    (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0)
    538 				drvp->UDMA_mode = 2;
    539 			if (drvp->UDMA_mode > 2)
    540 				ideconf |= PIIX_CONFIG_UDMA66(channel, drive);
    541 			else
    542 				ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive);
    543 		}
    544 		if ((wdc->cap & WDC_CAPABILITY_UDMA) &&
    545 		    (drvp->drive_flags & DRIVE_UDMA)) {
    546 			/* use Ultra/DMA */
    547 			drvp->drive_flags &= ~DRIVE_DMA;
    548 			udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive);
    549 			udmareg |= PIIX_UDMATIM_SET(
    550 			    piix4_sct_udma[drvp->UDMA_mode], channel, drive);
    551 		} else {
    552 			/* use Multiword DMA */
    553 			drvp->drive_flags &= ~DRIVE_UDMA;
    554 			if (drive == 0) {
    555 				idetim |= piix_setup_idetim_timings(
    556 				    drvp->DMA_mode, 1, channel);
    557 			} else {
    558 				sidetim |= piix_setup_sidetim_timings(
    559 					drvp->DMA_mode, 1, channel);
    560 				idetim =PIIX_IDETIM_SET(idetim,
    561 				    PIIX_IDETIM_SITRE, channel);
    562 			}
    563 		}
    564 		idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    565 
    566 pio:		/* use PIO mode */
    567 		idetim |= piix_setup_idetim_drvs(drvp);
    568 		if (drive == 0) {
    569 			idetim |= piix_setup_idetim_timings(
    570 			    drvp->PIO_mode, 0, channel);
    571 		} else {
    572 			sidetim |= piix_setup_sidetim_timings(
    573 				drvp->PIO_mode, 0, channel);
    574 			idetim =PIIX_IDETIM_SET(idetim,
    575 			    PIIX_IDETIM_SITRE, channel);
    576 		}
    577 	}
    578 	if (idedma_ctl != 0) {
    579 		/* Add software bits in status register */
    580 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    581 		    idedma_ctl);
    582 	}
    583 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim);
    584 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim);
    585 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg);
    586 	pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf);
    587 }
    588 
    589 
    590 /* setup ISP and RTC fields, based on mode */
    591 static u_int32_t
    592 piix_setup_idetim_timings(mode, dma, channel)
    593 	u_int8_t mode;
    594 	u_int8_t dma;
    595 	u_int8_t channel;
    596 {
    597 
    598 	if (dma)
    599 		return PIIX_IDETIM_SET(0,
    600 		    PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) |
    601 		    PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]),
    602 		    channel);
    603 	else
    604 		return PIIX_IDETIM_SET(0,
    605 		    PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) |
    606 		    PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]),
    607 		    channel);
    608 }
    609 
    610 /* setup DTE, PPE, IE and TIME field based on PIO mode */
    611 static u_int32_t
    612 piix_setup_idetim_drvs(drvp)
    613 	struct ata_drive_datas *drvp;
    614 {
    615 	u_int32_t ret = 0;
    616 	struct wdc_channel *chp = drvp->chnl_softc;
    617 	u_int8_t channel = chp->ch_channel;
    618 	u_int8_t drive = drvp->drive;
    619 
    620 	/*
    621 	 * If drive is using UDMA, timings setups are independant
    622 	 * So just check DMA and PIO here.
    623 	 */
    624 	if (drvp->drive_flags & DRIVE_DMA) {
    625 		/* if mode = DMA mode 0, use compatible timings */
    626 		if ((drvp->drive_flags & DRIVE_DMA) &&
    627 		    drvp->DMA_mode == 0) {
    628 			drvp->PIO_mode = 0;
    629 			return ret;
    630 		}
    631 		ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
    632 		/*
    633 		 * PIO and DMA timings are the same, use fast timings for PIO
    634 		 * too, else use compat timings.
    635 		 */
    636 		if ((piix_isp_pio[drvp->PIO_mode] !=
    637 		    piix_isp_dma[drvp->DMA_mode]) ||
    638 		    (piix_rtc_pio[drvp->PIO_mode] !=
    639 		    piix_rtc_dma[drvp->DMA_mode]))
    640 			drvp->PIO_mode = 0;
    641 		/* if PIO mode <= 2, use compat timings for PIO */
    642 		if (drvp->PIO_mode <= 2) {
    643 			ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive),
    644 			    channel);
    645 			return ret;
    646 		}
    647 	}
    648 
    649 	/*
    650 	 * Now setup PIO modes. If mode < 2, use compat timings.
    651 	 * Else enable fast timings. Enable IORDY and prefetch/post
    652 	 * if PIO mode >= 3.
    653 	 */
    654 
    655 	if (drvp->PIO_mode < 2)
    656 		return ret;
    657 
    658 	ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel);
    659 	if (drvp->PIO_mode >= 3) {
    660 		ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel);
    661 		ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel);
    662 	}
    663 	return ret;
    664 }
    665 
    666 /* setup values in SIDETIM registers, based on mode */
    667 static u_int32_t
    668 piix_setup_sidetim_timings(mode, dma, channel)
    669 	u_int8_t mode;
    670 	u_int8_t dma;
    671 	u_int8_t channel;
    672 {
    673 	if (dma)
    674 		return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) |
    675 		    PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel);
    676 	else
    677 		return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) |
    678 		    PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel);
    679 }
    680 
    681 static void
    682 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
    683 {
    684 	struct pciide_channel *cp;
    685 	bus_size_t cmdsize, ctlsize;
    686 	pcireg_t interface;
    687 	int channel;
    688 
    689 	if (pciide_chipen(sc, pa) == 0)
    690 		return;
    691 
    692 	aprint_normal("%s: bus-master DMA support present",
    693 	    sc->sc_wdcdev.sc_dev.dv_xname);
    694 	pciide_mapreg_dma(sc, pa);
    695 	aprint_normal("\n");
    696 
    697 	sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
    698 	    WDC_CAPABILITY_MODE;
    699 	sc->sc_wdcdev.PIO_cap = 4;
    700 	if (sc->sc_dma_ok) {
    701 		sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
    702 		sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
    703 		sc->sc_wdcdev.irqack = pciide_irqack;
    704 		sc->sc_wdcdev.DMA_cap = 2;
    705 		sc->sc_wdcdev.UDMA_cap = 6;
    706 	}
    707 	sc->sc_wdcdev.set_modes = sata_setup_channel;
    708 
    709 	sc->sc_wdcdev.channels = sc->wdc_chanarray;
    710 	sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
    711 
    712 	interface = PCI_INTERFACE(pa->pa_class);
    713 
    714 	for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
    715 		cp = &sc->pciide_channels[channel];
    716 		if (pciide_chansetup(sc, channel, interface) == 0)
    717 			continue;
    718 		pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
    719 		    pciide_pci_intr);
    720 	}
    721 }
    722