piixide.c revision 1.9.2.9
1 /* $NetBSD: piixide.c,v 1.9.2.9 2005/03/04 16:45:25 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_piix_reg.h> 40 41 static void piix_chip_map(struct pciide_softc*, struct pci_attach_args *); 42 static void piix_setup_channel(struct ata_channel *); 43 static void piix3_4_setup_channel(struct ata_channel *); 44 static u_int32_t piix_setup_idetim_timings(u_int8_t, u_int8_t, u_int8_t); 45 static u_int32_t piix_setup_idetim_drvs(struct ata_drive_datas *); 46 static u_int32_t piix_setup_sidetim_timings(u_int8_t, u_int8_t, u_int8_t); 47 static void piixsata_chip_map(struct pciide_softc*, struct pci_attach_args *); 48 49 static void piixide_powerhook(int, void *); 50 static int piixide_match(struct device *, struct cfdata *, void *); 51 static void piixide_attach(struct device *, struct device *, void *); 52 53 static const struct pciide_product_desc pciide_intel_products[] = { 54 { PCI_PRODUCT_INTEL_82092AA, 55 0, 56 "Intel 82092AA IDE controller", 57 default_chip_map, 58 }, 59 { PCI_PRODUCT_INTEL_82371FB_IDE, 60 0, 61 "Intel 82371FB IDE controller (PIIX)", 62 piix_chip_map, 63 }, 64 { PCI_PRODUCT_INTEL_82371SB_IDE, 65 0, 66 "Intel 82371SB IDE Interface (PIIX3)", 67 piix_chip_map, 68 }, 69 { PCI_PRODUCT_INTEL_82371AB_IDE, 70 0, 71 "Intel 82371AB IDE controller (PIIX4)", 72 piix_chip_map, 73 }, 74 { PCI_PRODUCT_INTEL_82440MX_IDE, 75 0, 76 "Intel 82440MX IDE controller", 77 piix_chip_map 78 }, 79 { PCI_PRODUCT_INTEL_82801AA_IDE, 80 0, 81 "Intel 82801AA IDE Controller (ICH)", 82 piix_chip_map, 83 }, 84 { PCI_PRODUCT_INTEL_82801AB_IDE, 85 0, 86 "Intel 82801AB IDE Controller (ICH0)", 87 piix_chip_map, 88 }, 89 { PCI_PRODUCT_INTEL_82801BA_IDE, 90 0, 91 "Intel 82801BA IDE Controller (ICH2)", 92 piix_chip_map, 93 }, 94 { PCI_PRODUCT_INTEL_82801BAM_IDE, 95 0, 96 "Intel 82801BAM IDE Controller (ICH2-M)", 97 piix_chip_map, 98 }, 99 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 100 0, 101 "Intel 82801CA IDE Controller (ICH3)", 102 piix_chip_map, 103 }, 104 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 105 0, 106 "Intel 82801CA IDE Controller (ICH3)", 107 piix_chip_map, 108 }, 109 { PCI_PRODUCT_INTEL_82801DB_IDE, 110 0, 111 "Intel 82801DB IDE Controller (ICH4)", 112 piix_chip_map, 113 }, 114 { PCI_PRODUCT_INTEL_82801DBM_IDE, 115 0, 116 "Intel 82801DBM IDE Controller (ICH4-M)", 117 piix_chip_map, 118 }, 119 { PCI_PRODUCT_INTEL_82801EB_IDE, 120 0, 121 "Intel 82801EB IDE Controller (ICH5)", 122 piix_chip_map, 123 }, 124 { PCI_PRODUCT_INTEL_82801EB_SATA, 125 0, 126 "Intel 82801EB Serial ATA Controller", 127 piixsata_chip_map, 128 }, 129 { PCI_PRODUCT_INTEL_82801ER_SATA, 130 0, 131 "Intel 82801ER Serial ATA/Raid Controller", 132 piixsata_chip_map, 133 }, 134 { PCI_PRODUCT_INTEL_6300ESB_IDE, 135 0, 136 "Intel 6300ESB IDE Controller (ICH5)", 137 piix_chip_map, 138 }, 139 { PCI_PRODUCT_INTEL_6300ESB_SATA, 140 0, 141 "Intel 6300ESB Serial ATA Controller", 142 piixsata_chip_map, 143 }, 144 { PCI_PRODUCT_INTEL_82801FB_IDE, 145 0, 146 "Intel 82801FB IDE Controller (ICH6)", 147 piix_chip_map, 148 }, 149 { PCI_PRODUCT_INTEL_82801FB_SATA, 150 0, 151 "Intel 82801FB Serial ATA/Raid Controller", 152 piixsata_chip_map, 153 }, 154 { PCI_PRODUCT_INTEL_82801FR_SATA, 155 0, 156 "Intel 82801FR Serial ATA/Raid Controller", 157 piixsata_chip_map, 158 }, 159 { 0, 160 0, 161 NULL, 162 NULL 163 } 164 }; 165 166 CFATTACH_DECL(piixide, sizeof(struct pciide_softc), 167 piixide_match, piixide_attach, NULL, NULL); 168 169 static int 170 piixide_match(struct device *parent, struct cfdata *match, void *aux) 171 { 172 struct pci_attach_args *pa = aux; 173 174 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 175 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 176 return (2); 177 } 178 return (0); 179 } 180 181 static void 182 piixide_attach(struct device *parent, struct device *self, void *aux) 183 { 184 struct pci_attach_args *pa = aux; 185 struct pciide_softc *sc = (struct pciide_softc *)self; 186 187 pciide_common_attach(sc, pa, 188 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 189 190 /* Setup our powerhook */ 191 sc->sc_powerhook = powerhook_establish(piixide_powerhook, sc); 192 if (sc->sc_powerhook == NULL) 193 printf("%s: WARNING: unable to establish PCI power hook\n", 194 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 195 } 196 197 static void 198 piixide_powerhook(int why, void *hdl) 199 { 200 struct pciide_softc *sc = (struct pciide_softc *)hdl; 201 202 switch (why) { 203 case PWR_SUSPEND: 204 case PWR_STANDBY: 205 pci_conf_capture(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 206 break; 207 case PWR_RESUME: 208 pci_conf_restore(sc->sc_pc, sc->sc_tag, &sc->sc_pciconf); 209 break; 210 case PWR_SOFTSUSPEND: 211 case PWR_SOFTSTANDBY: 212 case PWR_SOFTRESUME: 213 break; 214 } 215 216 return; 217 } 218 219 static void 220 piix_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 221 { 222 struct pciide_channel *cp; 223 int channel; 224 u_int32_t idetim; 225 bus_size_t cmdsize, ctlsize; 226 227 if (pciide_chipen(sc, pa) == 0) 228 return; 229 230 aprint_normal("%s: bus-master DMA support present", 231 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 232 pciide_mapreg_dma(sc, pa); 233 aprint_normal("\n"); 234 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 235 if (sc->sc_dma_ok) { 236 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 237 sc->sc_wdcdev.irqack = pciide_irqack; 238 switch(sc->sc_pp->ide_product) { 239 case PCI_PRODUCT_INTEL_82371AB_IDE: 240 case PCI_PRODUCT_INTEL_82440MX_IDE: 241 case PCI_PRODUCT_INTEL_82801AA_IDE: 242 case PCI_PRODUCT_INTEL_82801AB_IDE: 243 case PCI_PRODUCT_INTEL_82801BA_IDE: 244 case PCI_PRODUCT_INTEL_82801BAM_IDE: 245 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 246 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 247 case PCI_PRODUCT_INTEL_82801DB_IDE: 248 case PCI_PRODUCT_INTEL_82801DBM_IDE: 249 case PCI_PRODUCT_INTEL_82801EB_IDE: 250 case PCI_PRODUCT_INTEL_6300ESB_IDE: 251 case PCI_PRODUCT_INTEL_82801FB_IDE: 252 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 253 } 254 } 255 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 256 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 257 switch(sc->sc_pp->ide_product) { 258 case PCI_PRODUCT_INTEL_82801AA_IDE: 259 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 260 break; 261 case PCI_PRODUCT_INTEL_82801BA_IDE: 262 case PCI_PRODUCT_INTEL_82801BAM_IDE: 263 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 264 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 265 case PCI_PRODUCT_INTEL_82801DB_IDE: 266 case PCI_PRODUCT_INTEL_82801DBM_IDE: 267 case PCI_PRODUCT_INTEL_82801EB_IDE: 268 case PCI_PRODUCT_INTEL_6300ESB_IDE: 269 case PCI_PRODUCT_INTEL_82801FB_IDE: 270 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 271 break; 272 default: 273 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 274 } 275 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 276 sc->sc_wdcdev.sc_atac.atac_set_modes = piix_setup_channel; 277 else 278 sc->sc_wdcdev.sc_atac.atac_set_modes = piix3_4_setup_channel; 279 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 280 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 281 282 ATADEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 283 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 284 DEBUG_PROBE); 285 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 286 ATADEBUG_PRINT((", sidetim=0x%x", 287 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 288 DEBUG_PROBE); 289 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 290 ATADEBUG_PRINT((", udamreg 0x%x", 291 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 292 DEBUG_PROBE); 293 } 294 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 295 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 296 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 297 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 298 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 299 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 300 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 301 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 302 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 303 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 304 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 305 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 306 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 307 DEBUG_PROBE); 308 } 309 310 } 311 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 312 313 wdc_allocate_regs(&sc->sc_wdcdev); 314 315 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 316 channel++) { 317 cp = &sc->pciide_channels[channel]; 318 /* PIIX is compat-only */ 319 if (pciide_chansetup(sc, channel, 0) == 0) 320 continue; 321 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 322 if ((PIIX_IDETIM_READ(idetim, channel) & 323 PIIX_IDETIM_IDE) == 0) { 324 #if 1 325 aprint_normal("%s: %s channel ignored (disabled)\n", 326 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 327 cp->ata_channel.ch_flags |= ATACH_DISABLED; 328 continue; 329 #else 330 pcireg_t interface; 331 332 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 333 channel); 334 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 335 idetim); 336 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 337 sc->sc_tag, PCI_CLASS_REG)); 338 aprint_normal("channel %d idetim=%08x interface=%02x\n", 339 channel, idetim, interface); 340 #endif 341 } 342 /* PIIX are compat-only pciide devices */ 343 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 344 } 345 346 ATADEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 347 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 348 DEBUG_PROBE); 349 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 350 ATADEBUG_PRINT((", sidetim=0x%x", 351 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 352 DEBUG_PROBE); 353 if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) { 354 ATADEBUG_PRINT((", udamreg 0x%x", 355 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 356 DEBUG_PROBE); 357 } 358 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 359 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 360 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 361 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 362 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 363 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 364 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 365 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 366 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 367 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 368 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 369 ATADEBUG_PRINT((", IDE_CONTROL 0x%x", 370 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 371 DEBUG_PROBE); 372 } 373 } 374 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 375 } 376 377 static void 378 piix_setup_channel(struct ata_channel *chp) 379 { 380 u_int8_t mode[2], drive; 381 u_int32_t oidetim, idetim, idedma_ctl; 382 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 383 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 384 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 385 386 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 387 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->ch_channel); 388 idedma_ctl = 0; 389 390 /* set up new idetim: Enable IDE registers decode */ 391 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 392 chp->ch_channel); 393 394 /* setup DMA */ 395 pciide_channel_dma_setup(cp); 396 397 /* 398 * Here we have to mess up with drives mode: PIIX can't have 399 * different timings for master and slave drives. 400 * We need to find the best combination. 401 */ 402 403 /* If both drives supports DMA, take the lower mode */ 404 if ((drvp[0].drive_flags & DRIVE_DMA) && 405 (drvp[1].drive_flags & DRIVE_DMA)) { 406 mode[0] = mode[1] = 407 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 408 drvp[0].DMA_mode = mode[0]; 409 drvp[1].DMA_mode = mode[1]; 410 goto ok; 411 } 412 /* 413 * If only one drive supports DMA, use its mode, and 414 * put the other one in PIO mode 0 if mode not compatible 415 */ 416 if (drvp[0].drive_flags & DRIVE_DMA) { 417 mode[0] = drvp[0].DMA_mode; 418 mode[1] = drvp[1].PIO_mode; 419 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 420 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 421 mode[1] = drvp[1].PIO_mode = 0; 422 goto ok; 423 } 424 if (drvp[1].drive_flags & DRIVE_DMA) { 425 mode[1] = drvp[1].DMA_mode; 426 mode[0] = drvp[0].PIO_mode; 427 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 428 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 429 mode[0] = drvp[0].PIO_mode = 0; 430 goto ok; 431 } 432 /* 433 * If both drives are not DMA, takes the lower mode, unless 434 * one of them is PIO mode < 2 435 */ 436 if (drvp[0].PIO_mode < 2) { 437 mode[0] = drvp[0].PIO_mode = 0; 438 mode[1] = drvp[1].PIO_mode; 439 } else if (drvp[1].PIO_mode < 2) { 440 mode[1] = drvp[1].PIO_mode = 0; 441 mode[0] = drvp[0].PIO_mode; 442 } else { 443 mode[0] = mode[1] = 444 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 445 drvp[0].PIO_mode = mode[0]; 446 drvp[1].PIO_mode = mode[1]; 447 } 448 ok: /* The modes are setup */ 449 for (drive = 0; drive < 2; drive++) { 450 if (drvp[drive].drive_flags & DRIVE_DMA) { 451 idetim |= piix_setup_idetim_timings( 452 mode[drive], 1, chp->ch_channel); 453 goto end; 454 } 455 } 456 /* If we are there, none of the drives are DMA */ 457 if (mode[0] >= 2) 458 idetim |= piix_setup_idetim_timings( 459 mode[0], 0, chp->ch_channel); 460 else 461 idetim |= piix_setup_idetim_timings( 462 mode[1], 0, chp->ch_channel); 463 end: /* 464 * timing mode is now set up in the controller. Enable 465 * it per-drive 466 */ 467 for (drive = 0; drive < 2; drive++) { 468 /* If no drive, skip */ 469 if ((drvp[drive].drive_flags & DRIVE) == 0) 470 continue; 471 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 472 if (drvp[drive].drive_flags & DRIVE_DMA) 473 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 474 } 475 if (idedma_ctl != 0) { 476 /* Add software bits in status register */ 477 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 478 idedma_ctl); 479 } 480 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 481 } 482 483 static void 484 piix3_4_setup_channel(struct ata_channel *chp) 485 { 486 struct ata_drive_datas *drvp; 487 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 488 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 489 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 490 struct wdc_softc *wdc = &sc->sc_wdcdev; 491 int drive, s; 492 int channel = chp->ch_channel; 493 494 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 495 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 496 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 497 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 498 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 499 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 500 PIIX_SIDETIM_RTC_MASK(channel)); 501 idedma_ctl = 0; 502 503 /* set up new idetim: Enable IDE registers decode */ 504 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 505 506 /* setup DMA if needed */ 507 pciide_channel_dma_setup(cp); 508 509 for (drive = 0; drive < 2; drive++) { 510 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 511 PIIX_UDMATIM_SET(0x3, channel, drive)); 512 drvp = &chp->ch_drive[drive]; 513 /* If no drive, skip */ 514 if ((drvp->drive_flags & DRIVE) == 0) 515 continue; 516 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 517 (drvp->drive_flags & DRIVE_UDMA) == 0)) 518 goto pio; 519 520 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 521 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 522 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 523 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 524 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 525 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 526 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 527 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 528 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 529 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 530 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 531 ideconf |= PIIX_CONFIG_PINGPONG; 532 } 533 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 534 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 535 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 536 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 537 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 538 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 539 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE || 540 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801FB_IDE || 541 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_6300ESB_IDE) { 542 /* setup Ultra/100 */ 543 if (drvp->UDMA_mode > 2 && 544 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 545 drvp->UDMA_mode = 2; 546 if (drvp->UDMA_mode > 4) { 547 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 548 } else { 549 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 550 if (drvp->UDMA_mode > 2) { 551 ideconf |= PIIX_CONFIG_UDMA66(channel, 552 drive); 553 } else { 554 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 555 drive); 556 } 557 } 558 } 559 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 560 /* setup Ultra/66 */ 561 if (drvp->UDMA_mode > 2 && 562 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 563 drvp->UDMA_mode = 2; 564 if (drvp->UDMA_mode > 2) 565 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 566 else 567 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 568 } 569 if ((wdc->sc_atac.atac_cap & ATAC_CAP_UDMA) && 570 (drvp->drive_flags & DRIVE_UDMA)) { 571 /* use Ultra/DMA */ 572 s = splbio(); 573 drvp->drive_flags &= ~DRIVE_DMA; 574 splx(s); 575 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 576 udmareg |= PIIX_UDMATIM_SET( 577 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 578 } else { 579 /* use Multiword DMA */ 580 s = splbio(); 581 drvp->drive_flags &= ~DRIVE_UDMA; 582 splx(s); 583 if (drive == 0) { 584 idetim |= piix_setup_idetim_timings( 585 drvp->DMA_mode, 1, channel); 586 } else { 587 sidetim |= piix_setup_sidetim_timings( 588 drvp->DMA_mode, 1, channel); 589 idetim =PIIX_IDETIM_SET(idetim, 590 PIIX_IDETIM_SITRE, channel); 591 } 592 } 593 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 594 595 pio: /* use PIO mode */ 596 idetim |= piix_setup_idetim_drvs(drvp); 597 if (drive == 0) { 598 idetim |= piix_setup_idetim_timings( 599 drvp->PIO_mode, 0, channel); 600 } else { 601 sidetim |= piix_setup_sidetim_timings( 602 drvp->PIO_mode, 0, channel); 603 idetim =PIIX_IDETIM_SET(idetim, 604 PIIX_IDETIM_SITRE, channel); 605 } 606 } 607 if (idedma_ctl != 0) { 608 /* Add software bits in status register */ 609 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 610 idedma_ctl); 611 } 612 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 613 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 614 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 615 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 616 } 617 618 619 /* setup ISP and RTC fields, based on mode */ 620 static u_int32_t 621 piix_setup_idetim_timings(mode, dma, channel) 622 u_int8_t mode; 623 u_int8_t dma; 624 u_int8_t channel; 625 { 626 627 if (dma) 628 return PIIX_IDETIM_SET(0, 629 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 630 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 631 channel); 632 else 633 return PIIX_IDETIM_SET(0, 634 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 635 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 636 channel); 637 } 638 639 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 640 static u_int32_t 641 piix_setup_idetim_drvs(drvp) 642 struct ata_drive_datas *drvp; 643 { 644 u_int32_t ret = 0; 645 struct ata_channel *chp = drvp->chnl_softc; 646 u_int8_t channel = chp->ch_channel; 647 u_int8_t drive = drvp->drive; 648 649 /* 650 * If drive is using UDMA, timings setups are independant 651 * So just check DMA and PIO here. 652 */ 653 if (drvp->drive_flags & DRIVE_DMA) { 654 /* if mode = DMA mode 0, use compatible timings */ 655 if ((drvp->drive_flags & DRIVE_DMA) && 656 drvp->DMA_mode == 0) { 657 drvp->PIO_mode = 0; 658 return ret; 659 } 660 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 661 /* 662 * PIO and DMA timings are the same, use fast timings for PIO 663 * too, else use compat timings. 664 */ 665 if ((piix_isp_pio[drvp->PIO_mode] != 666 piix_isp_dma[drvp->DMA_mode]) || 667 (piix_rtc_pio[drvp->PIO_mode] != 668 piix_rtc_dma[drvp->DMA_mode])) 669 drvp->PIO_mode = 0; 670 /* if PIO mode <= 2, use compat timings for PIO */ 671 if (drvp->PIO_mode <= 2) { 672 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 673 channel); 674 return ret; 675 } 676 } 677 678 /* 679 * Now setup PIO modes. If mode < 2, use compat timings. 680 * Else enable fast timings. Enable IORDY and prefetch/post 681 * if PIO mode >= 3. 682 */ 683 684 if (drvp->PIO_mode < 2) 685 return ret; 686 687 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 688 if (drvp->PIO_mode >= 3) { 689 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 690 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 691 } 692 return ret; 693 } 694 695 /* setup values in SIDETIM registers, based on mode */ 696 static u_int32_t 697 piix_setup_sidetim_timings(mode, dma, channel) 698 u_int8_t mode; 699 u_int8_t dma; 700 u_int8_t channel; 701 { 702 if (dma) 703 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 704 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 705 else 706 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 707 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 708 } 709 710 static void 711 piixsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 712 { 713 struct pciide_channel *cp; 714 bus_size_t cmdsize, ctlsize; 715 pcireg_t interface; 716 int channel; 717 718 if (pciide_chipen(sc, pa) == 0) 719 return; 720 721 aprint_normal("%s: bus-master DMA support present", 722 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 723 pciide_mapreg_dma(sc, pa); 724 aprint_normal("\n"); 725 726 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 727 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 728 if (sc->sc_dma_ok) { 729 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 730 sc->sc_wdcdev.irqack = pciide_irqack; 731 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 732 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 733 } 734 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 735 736 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 737 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 738 739 interface = PCI_INTERFACE(pa->pa_class); 740 741 wdc_allocate_regs(&sc->sc_wdcdev); 742 743 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 744 channel++) { 745 cp = &sc->pciide_channels[channel]; 746 if (pciide_chansetup(sc, channel, interface) == 0) 747 continue; 748 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 749 pciide_pci_intr); 750 } 751 } 752
Indexes created Wed Oct 15 16:09:53 GMT 2025