piixpm.c revision 1.1
1 /* $NetBSD: piixpm.c,v 1.1 2006/05/07 01:32:42 jmcneill Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/device.h> 27 #include <sys/kernel.h> 28 #include <sys/lock.h> 29 #include <sys/proc.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcidevs.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 37 #include <dev/pci/piixpmreg.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #ifdef PIIXPM_DEBUG 42 #define DPRINTF(x) printf x 43 #else 44 #define DPRINTF(x) 45 #endif 46 47 #define PIIXPM_DELAY 200 48 #define PIIXPM_TIMEOUT 1 49 50 struct piixpm_softc { 51 struct device sc_dev; 52 53 bus_space_tag_t sc_iot; 54 bus_space_handle_t sc_ioh; 55 void * sc_ih; 56 int sc_poll; 57 58 struct i2c_controller sc_i2c_tag; 59 struct lock sc_i2c_lock; 60 struct { 61 i2c_op_t op; 62 void * buf; 63 size_t len; 64 int flags; 65 volatile int error; 66 } sc_i2c_xfer; 67 }; 68 69 int piixpm_match(struct device *, struct cfdata *, void *); 70 void piixpm_attach(struct device *, struct device *, void *); 71 72 int piixpm_i2c_acquire_bus(void *, int); 73 void piixpm_i2c_release_bus(void *, int); 74 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 75 void *, size_t, int); 76 77 int piixpm_intr(void *); 78 79 CFATTACH_DECL(piixpm, sizeof(struct piixpm_softc), 80 piixpm_match, piixpm_attach, NULL, NULL); 81 82 int 83 piixpm_match(struct device *parent, struct cfdata *match, void *aux) 84 { 85 struct pci_attach_args *pa; 86 87 pa = (struct pci_attach_args *)aux; 88 switch (PCI_VENDOR(pa->pa_id)) { 89 case PCI_VENDOR_INTEL: 90 switch (PCI_PRODUCT(pa->pa_id)) { 91 case PCI_PRODUCT_INTEL_82371AB_PMC: 92 case PCI_PRODUCT_INTEL_82440MX_PMC: 93 return 1; 94 } 95 break; 96 case PCI_VENDOR_ATI: 97 switch (PCI_PRODUCT(pa->pa_id)) { 98 case PCI_PRODUCT_ATI_SB200_SMB: 99 return 1; 100 } 101 break; 102 } 103 104 return 0; 105 } 106 107 void 108 piixpm_attach(struct device *parent, struct device *self, void *aux) 109 { 110 struct piixpm_softc *sc = (struct piixpm_softc *)self; 111 struct pci_attach_args *pa = aux; 112 struct i2cbus_attach_args iba; 113 pcireg_t base, conf; 114 pci_intr_handle_t ih; 115 const char *intrstr = NULL; 116 117 /* Read configuration */ 118 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 119 DPRINTF((": conf 0x%x", conf)); 120 121 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 122 printf(": SMBus disabled\n"); 123 return; 124 } 125 126 /* Map I/O space */ 127 sc->sc_iot = pa->pa_iot; 128 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 129 if (bus_space_map(sc->sc_iot, PCI_MAPREG_IO_ADDR(base), 130 PIIX_SMB_SIZE, 0, &sc->sc_ioh)) { 131 printf(": can't map I/O space\n"); 132 return; 133 } 134 135 sc->sc_poll = 1; 136 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 137 /* No PCI IRQ */ 138 printf(": SMI"); 139 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 140 /* Install interrupt handler */ 141 if (pci_intr_map(pa, &ih) == 0) { 142 intrstr = pci_intr_string(pa->pa_pc, ih); 143 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 144 piixpm_intr, sc); 145 if (sc->sc_ih != NULL) { 146 printf(": %s", intrstr); 147 sc->sc_poll = 0; 148 } 149 } 150 if (sc->sc_poll) 151 printf(": polling"); 152 } 153 154 printf("\n"); 155 156 /* Attach I2C bus */ 157 lockinit(&sc->sc_i2c_lock, PRIBIO | PCATCH, "iiclk", 0, 0); 158 sc->sc_i2c_tag.ic_cookie = sc; 159 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 160 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 161 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 162 163 bzero(&iba, sizeof(iba)); 164 iba.iba_name = "iic"; 165 iba.iba_tag = &sc->sc_i2c_tag; 166 config_found(self, &iba, iicbus_print); 167 168 return; 169 } 170 171 int 172 piixpm_i2c_acquire_bus(void *cookie, int flags) 173 { 174 struct piixpm_softc *sc = cookie; 175 176 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 177 return (0); 178 179 return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 180 } 181 182 void 183 piixpm_i2c_release_bus(void *cookie, int flags) 184 { 185 struct piixpm_softc *sc = cookie; 186 187 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 188 return; 189 190 lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 191 } 192 193 int 194 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 195 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 196 { 197 struct piixpm_softc *sc = cookie; 198 const u_int8_t *b; 199 u_int8_t ctl = 0, st; 200 int retries; 201 202 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %d, len %d, flags 0x%x\n", 203 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags)); 204 205 /* Wait for bus to be idle */ 206 for (retries = 100; retries > 0; retries--) { 207 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 208 if (!(st & PIIX_SMB_HS_BUSY)) 209 break; 210 DELAY(PIIXPM_DELAY); 211 } 212 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 213 PIIX_SMB_HS_BITS)); 214 if (st & PIIX_SMB_HS_BUSY) 215 return (1); 216 217 if (cold || sc->sc_poll) 218 flags |= I2C_F_POLL; 219 220 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 221 return (1); 222 223 /* Setup transfer */ 224 sc->sc_i2c_xfer.op = op; 225 sc->sc_i2c_xfer.buf = buf; 226 sc->sc_i2c_xfer.len = len; 227 sc->sc_i2c_xfer.flags = flags; 228 sc->sc_i2c_xfer.error = 0; 229 230 /* Set slave address and transfer direction */ 231 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_TXSLVA, 232 PIIX_SMB_TXSLVA_ADDR(addr) | 233 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 234 235 b = cmdbuf; 236 if (cmdlen > 0) 237 /* Set command byte */ 238 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HCMD, b[0]); 239 240 if (I2C_OP_WRITE_P(op)) { 241 /* Write data */ 242 b = buf; 243 if (len > 0) 244 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 245 PIIX_SMB_HD0, b[0]); 246 if (len > 1) 247 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 248 PIIX_SMB_HD1, b[1]); 249 } 250 251 /* Set SMBus command */ 252 if (len == 0) 253 ctl = PIIX_SMB_HC_CMD_BYTE; 254 else if (len == 1) 255 ctl = PIIX_SMB_HC_CMD_BDATA; 256 else if (len == 2) 257 ctl = PIIX_SMB_HC_CMD_WDATA; 258 259 if ((flags & I2C_F_POLL) == 0) 260 ctl |= PIIX_SMB_HC_INTREN; 261 262 /* Start transaction */ 263 ctl |= PIIX_SMB_HC_START; 264 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, ctl); 265 266 if (flags & I2C_F_POLL) { 267 /* Poll for completion */ 268 DELAY(PIIXPM_DELAY); 269 for (retries = 1000; retries > 0; retries--) { 270 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 271 PIIX_SMB_HS); 272 if ((st & PIIX_SMB_HS_BUSY) == 0) 273 break; 274 DELAY(PIIXPM_DELAY); 275 } 276 if (st & PIIX_SMB_HS_BUSY) 277 goto timeout; 278 piixpm_intr(sc); 279 } else { 280 /* Wait for interrupt */ 281 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 282 goto timeout; 283 } 284 285 if (sc->sc_i2c_xfer.error) 286 return (1); 287 288 return (0); 289 290 timeout: 291 /* 292 * Transfer timeout. Kill the transaction and clear status bits. 293 */ 294 printf("%s: timeout, status 0x%x\n", sc->sc_dev.dv_xname, st); 295 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HC, 296 PIIX_SMB_HC_KILL); 297 DELAY(PIIXPM_DELAY); 298 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 299 if ((st & PIIX_SMB_HS_FAILED) == 0) 300 printf("%s: transaction abort failed, status 0x%x\n", 301 sc->sc_dev.dv_xname, st); 302 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 303 return (1); 304 } 305 306 int 307 piixpm_intr(void *arg) 308 { 309 struct piixpm_softc *sc = arg; 310 u_int8_t st; 311 u_int8_t *b; 312 size_t len; 313 314 /* Read status */ 315 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS); 316 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 317 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 318 PIIX_SMB_HS_FAILED)) == 0) 319 /* Interrupt was not for us */ 320 return (0); 321 322 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 323 PIIX_SMB_HS_BITS)); 324 325 /* Clear status bits */ 326 bus_space_write_1(sc->sc_iot, sc->sc_ioh, PIIX_SMB_HS, st); 327 328 /* Check for errors */ 329 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 330 PIIX_SMB_HS_FAILED)) { 331 sc->sc_i2c_xfer.error = 1; 332 goto done; 333 } 334 335 if (st & PIIX_SMB_HS_INTR) { 336 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 337 goto done; 338 339 /* Read data */ 340 b = sc->sc_i2c_xfer.buf; 341 len = sc->sc_i2c_xfer.len; 342 if (len > 0) 343 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 344 PIIX_SMB_HD0); 345 if (len > 1) 346 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 347 PIIX_SMB_HD1); 348 } 349 350 done: 351 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 352 wakeup(sc); 353 return (1); 354 } 355
Indexes created Mon Sep 29 21:09:56 GMT 2025