piixpm.c revision 1.10
1 /* $NetBSD: piixpm.c,v 1.10 2006/10/31 14:03:07 toshii Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/device.h> 27 #include <sys/kernel.h> 28 #include <sys/lock.h> 29 #include <sys/proc.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcidevs.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 37 #include <dev/pci/piixpmreg.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #ifdef __HAVE_TIMECOUNTER 42 #include <dev/ic/acpipmtimer.h> 43 #endif 44 45 #ifdef PIIXPM_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define PIIXPM_DELAY 200 52 #define PIIXPM_TIMEOUT 1 53 54 struct piixpm_softc { 55 struct device sc_dev; 56 57 bus_space_tag_t sc_smb_iot; 58 bus_space_handle_t sc_smb_ioh; 59 void * sc_smb_ih; 60 int sc_poll; 61 62 bus_space_tag_t sc_pm_iot; 63 bus_space_handle_t sc_pm_ioh; 64 65 pci_chipset_tag_t sc_pc; 66 pcitag_t sc_pcitag; 67 68 struct i2c_controller sc_i2c_tag; 69 struct lock sc_i2c_lock; 70 struct { 71 i2c_op_t op; 72 void * buf; 73 size_t len; 74 int flags; 75 volatile int error; 76 } sc_i2c_xfer; 77 78 void * sc_powerhook; 79 struct pci_conf_state sc_pciconf; 80 pcireg_t sc_devact[2]; 81 }; 82 83 int piixpm_match(struct device *, struct cfdata *, void *); 84 void piixpm_attach(struct device *, struct device *, void *); 85 86 void piixpm_powerhook(int, void *); 87 88 int piixpm_i2c_acquire_bus(void *, int); 89 void piixpm_i2c_release_bus(void *, int); 90 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 91 void *, size_t, int); 92 93 int piixpm_intr(void *); 94 95 CFATTACH_DECL(piixpm, sizeof(struct piixpm_softc), 96 piixpm_match, piixpm_attach, NULL, NULL); 97 98 int 99 piixpm_match(struct device *parent __unused, struct cfdata *match __unused, 100 void *aux) 101 { 102 struct pci_attach_args *pa; 103 104 pa = (struct pci_attach_args *)aux; 105 switch (PCI_VENDOR(pa->pa_id)) { 106 case PCI_VENDOR_INTEL: 107 switch (PCI_PRODUCT(pa->pa_id)) { 108 case PCI_PRODUCT_INTEL_82371AB_PMC: 109 case PCI_PRODUCT_INTEL_82440MX_PMC: 110 return 1; 111 } 112 break; 113 case PCI_VENDOR_ATI: 114 switch (PCI_PRODUCT(pa->pa_id)) { 115 case PCI_PRODUCT_ATI_SB200_SMB: 116 case PCI_PRODUCT_ATI_SB300_SMB: 117 case PCI_PRODUCT_ATI_SB400_SMB: 118 return 1; 119 } 120 break; 121 } 122 123 return 0; 124 } 125 126 void 127 piixpm_attach(struct device *parent __unused, struct device *self, void *aux) 128 { 129 struct piixpm_softc *sc = (struct piixpm_softc *)self; 130 struct pci_attach_args *pa = aux; 131 struct i2cbus_attach_args iba; 132 pcireg_t base, conf; 133 #ifdef __HAVE_TIMECOUNTER 134 pcireg_t pmmisc; 135 #endif 136 pci_intr_handle_t ih; 137 const char *intrstr = NULL; 138 139 sc->sc_pc = pa->pa_pc; 140 sc->sc_pcitag = pa->pa_tag; 141 142 aprint_naive("\n"); 143 aprint_normal(": Power Management Controller\n"); 144 145 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 146 piixpm_powerhook, sc); 147 if (sc->sc_powerhook == NULL) 148 aprint_error("%s: can't establish powerhook\n", 149 sc->sc_dev.dv_xname); 150 151 /* Read configuration */ 152 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 153 DPRINTF((": conf 0x%x", conf)); 154 155 #ifdef __HAVE_TIMECOUNTER 156 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 157 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 158 goto nopowermanagement; 159 160 /* check whether I/O access to PM regs is enabled */ 161 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 162 if (!(pmmisc & 1)) 163 goto nopowermanagement; 164 165 sc->sc_pm_iot = pa->pa_iot; 166 /* Map I/O space */ 167 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 168 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 169 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 170 aprint_error("%s: can't map power management I/O space\n", 171 sc->sc_dev.dv_xname); 172 goto nopowermanagement; 173 } 174 175 /* 176 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 177 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 178 * in the "Specification update" (document #297738). 179 */ 180 acpipmtimer_attach(&sc->sc_dev, sc->sc_pm_iot, sc->sc_pm_ioh, 181 PIIX_PM_PMTMR, 182 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 183 184 nopowermanagement: 185 #endif 186 187 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 188 aprint_normal("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 189 return; 190 } 191 192 /* Map I/O space */ 193 sc->sc_smb_iot = pa->pa_iot; 194 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 195 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 196 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 197 aprint_error("%s: can't map smbus I/O space\n", 198 sc->sc_dev.dv_xname); 199 return; 200 } 201 202 sc->sc_poll = 1; 203 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 204 /* No PCI IRQ */ 205 aprint_normal("%s: interrupting at SMI", sc->sc_dev.dv_xname); 206 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 207 /* Install interrupt handler */ 208 if (pci_intr_map(pa, &ih) == 0) { 209 intrstr = pci_intr_string(pa->pa_pc, ih); 210 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 211 piixpm_intr, sc); 212 if (sc->sc_smb_ih != NULL) { 213 aprint_normal("%s: interrupting at %s", 214 sc->sc_dev.dv_xname, intrstr); 215 sc->sc_poll = 0; 216 } 217 } 218 if (sc->sc_poll) 219 aprint_normal("%s: polling", sc->sc_dev.dv_xname); 220 } 221 222 aprint_normal("\n"); 223 224 /* Attach I2C bus */ 225 lockinit(&sc->sc_i2c_lock, PRIBIO | PCATCH, "iiclk", 0, 0); 226 sc->sc_i2c_tag.ic_cookie = sc; 227 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 228 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 229 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 230 231 bzero(&iba, sizeof(iba)); 232 iba.iba_tag = &sc->sc_i2c_tag; 233 config_found_ia(self, "i2cbus", &iba, iicbus_print); 234 235 return; 236 } 237 238 void 239 piixpm_powerhook(int why, void *cookie) 240 { 241 struct piixpm_softc *sc = cookie; 242 pci_chipset_tag_t pc = sc->sc_pc; 243 pcitag_t tag = sc->sc_pcitag; 244 245 switch (why) { 246 case PWR_SUSPEND: 247 pci_conf_capture(pc, tag, &sc->sc_pciconf); 248 sc->sc_devact[0] = pci_conf_read(pc, tag, PIIX_DEVACTA); 249 sc->sc_devact[1] = pci_conf_read(pc, tag, PIIX_DEVACTB); 250 break; 251 case PWR_RESUME: 252 pci_conf_restore(pc, tag, &sc->sc_pciconf); 253 pci_conf_write(pc, tag, PIIX_DEVACTA, sc->sc_devact[0]); 254 pci_conf_write(pc, tag, PIIX_DEVACTB, sc->sc_devact[1]); 255 break; 256 } 257 258 return; 259 } 260 261 int 262 piixpm_i2c_acquire_bus(void *cookie, int flags) 263 { 264 struct piixpm_softc *sc = cookie; 265 266 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 267 return (0); 268 269 return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 270 } 271 272 void 273 piixpm_i2c_release_bus(void *cookie, int flags) 274 { 275 struct piixpm_softc *sc = cookie; 276 277 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 278 return; 279 280 lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 281 } 282 283 int 284 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 285 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 286 { 287 struct piixpm_softc *sc = cookie; 288 const u_int8_t *b; 289 u_int8_t ctl = 0, st; 290 int retries; 291 292 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %d, len %d, flags 0x%x\n", 293 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags)); 294 295 /* Wait for bus to be idle */ 296 for (retries = 100; retries > 0; retries--) { 297 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 298 PIIX_SMB_HS); 299 if (!(st & PIIX_SMB_HS_BUSY)) 300 break; 301 DELAY(PIIXPM_DELAY); 302 } 303 DPRINTF(("%s: exec: st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 304 if (st & PIIX_SMB_HS_BUSY) 305 return (1); 306 307 if (cold || sc->sc_poll) 308 flags |= I2C_F_POLL; 309 310 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 311 return (1); 312 313 /* Setup transfer */ 314 sc->sc_i2c_xfer.op = op; 315 sc->sc_i2c_xfer.buf = buf; 316 sc->sc_i2c_xfer.len = len; 317 sc->sc_i2c_xfer.flags = flags; 318 sc->sc_i2c_xfer.error = 0; 319 320 /* Set slave address and transfer direction */ 321 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 322 PIIX_SMB_TXSLVA_ADDR(addr) | 323 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 324 325 b = cmdbuf; 326 if (cmdlen > 0) 327 /* Set command byte */ 328 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 329 PIIX_SMB_HCMD, b[0]); 330 331 if (I2C_OP_WRITE_P(op)) { 332 /* Write data */ 333 b = buf; 334 if (len > 0) 335 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 336 PIIX_SMB_HD0, b[0]); 337 if (len > 1) 338 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 339 PIIX_SMB_HD1, b[1]); 340 } 341 342 /* Set SMBus command */ 343 if (len == 0) 344 ctl = PIIX_SMB_HC_CMD_BYTE; 345 else if (len == 1) 346 ctl = PIIX_SMB_HC_CMD_BDATA; 347 else if (len == 2) 348 ctl = PIIX_SMB_HC_CMD_WDATA; 349 350 if ((flags & I2C_F_POLL) == 0) 351 ctl |= PIIX_SMB_HC_INTREN; 352 353 /* Start transaction */ 354 ctl |= PIIX_SMB_HC_START; 355 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 356 357 if (flags & I2C_F_POLL) { 358 /* Poll for completion */ 359 DELAY(PIIXPM_DELAY); 360 for (retries = 1000; retries > 0; retries--) { 361 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 362 PIIX_SMB_HS); 363 if ((st & PIIX_SMB_HS_BUSY) == 0) 364 break; 365 DELAY(PIIXPM_DELAY); 366 } 367 if (st & PIIX_SMB_HS_BUSY) 368 goto timeout; 369 piixpm_intr(sc); 370 } else { 371 /* Wait for interrupt */ 372 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 373 goto timeout; 374 } 375 376 if (sc->sc_i2c_xfer.error) 377 return (1); 378 379 return (0); 380 381 timeout: 382 /* 383 * Transfer timeout. Kill the transaction and clear status bits. 384 */ 385 aprint_error("%s: timeout, status 0x%x\n", sc->sc_dev.dv_xname, st); 386 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 387 PIIX_SMB_HC_KILL); 388 DELAY(PIIXPM_DELAY); 389 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 390 if ((st & PIIX_SMB_HS_FAILED) == 0) 391 aprint_error("%s: transaction abort failed, status 0x%x\n", 392 sc->sc_dev.dv_xname, st); 393 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 394 return (1); 395 } 396 397 int 398 piixpm_intr(void *arg) 399 { 400 struct piixpm_softc *sc = arg; 401 u_int8_t st; 402 u_int8_t *b; 403 size_t len; 404 405 /* Read status */ 406 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 407 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 408 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 409 PIIX_SMB_HS_FAILED)) == 0) 410 /* Interrupt was not for us */ 411 return (0); 412 413 DPRINTF(("%s: intr st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 414 415 /* Clear status bits */ 416 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 417 418 /* Check for errors */ 419 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 420 PIIX_SMB_HS_FAILED)) { 421 sc->sc_i2c_xfer.error = 1; 422 goto done; 423 } 424 425 if (st & PIIX_SMB_HS_INTR) { 426 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 427 goto done; 428 429 /* Read data */ 430 b = sc->sc_i2c_xfer.buf; 431 len = sc->sc_i2c_xfer.len; 432 if (len > 0) 433 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 434 PIIX_SMB_HD0); 435 if (len > 1) 436 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 437 PIIX_SMB_HD1); 438 } 439 440 done: 441 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 442 wakeup(sc); 443 return (1); 444 } 445
Indexes created Mon Sep 29 21:09:56 GMT 2025