piixpm.c revision 1.12
1 /* $NetBSD: piixpm.c,v 1.12 2006/12/10 00:34:52 uwe Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/device.h> 27 #include <sys/kernel.h> 28 #include <sys/lock.h> 29 #include <sys/proc.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcidevs.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 37 #include <dev/pci/piixpmreg.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #ifdef __HAVE_TIMECOUNTER 42 #include <dev/ic/acpipmtimer.h> 43 #endif 44 45 #ifdef PIIXPM_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define PIIXPM_DELAY 200 52 #define PIIXPM_TIMEOUT 1 53 54 struct piixpm_softc { 55 struct device sc_dev; 56 57 bus_space_tag_t sc_smb_iot; 58 bus_space_handle_t sc_smb_ioh; 59 void * sc_smb_ih; 60 int sc_poll; 61 62 bus_space_tag_t sc_pm_iot; 63 bus_space_handle_t sc_pm_ioh; 64 65 pci_chipset_tag_t sc_pc; 66 pcitag_t sc_pcitag; 67 68 struct i2c_controller sc_i2c_tag; 69 struct lock sc_i2c_lock; 70 struct { 71 i2c_op_t op; 72 void * buf; 73 size_t len; 74 int flags; 75 volatile int error; 76 } sc_i2c_xfer; 77 78 void * sc_powerhook; 79 struct pci_conf_state sc_pciconf; 80 pcireg_t sc_devact[2]; 81 }; 82 83 int piixpm_match(struct device *, struct cfdata *, void *); 84 void piixpm_attach(struct device *, struct device *, void *); 85 86 void piixpm_powerhook(int, void *); 87 88 int piixpm_i2c_acquire_bus(void *, int); 89 void piixpm_i2c_release_bus(void *, int); 90 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 91 void *, size_t, int); 92 93 int piixpm_intr(void *); 94 95 CFATTACH_DECL(piixpm, sizeof(struct piixpm_softc), 96 piixpm_match, piixpm_attach, NULL, NULL); 97 98 int 99 piixpm_match(struct device *parent, struct cfdata *match, 100 void *aux) 101 { 102 struct pci_attach_args *pa; 103 104 pa = (struct pci_attach_args *)aux; 105 switch (PCI_VENDOR(pa->pa_id)) { 106 case PCI_VENDOR_INTEL: 107 switch (PCI_PRODUCT(pa->pa_id)) { 108 case PCI_PRODUCT_INTEL_82371AB_PMC: 109 case PCI_PRODUCT_INTEL_82440MX_PMC: 110 return 1; 111 } 112 break; 113 case PCI_VENDOR_ATI: 114 switch (PCI_PRODUCT(pa->pa_id)) { 115 case PCI_PRODUCT_ATI_SB200_SMB: 116 case PCI_PRODUCT_ATI_SB300_SMB: 117 case PCI_PRODUCT_ATI_SB400_SMB: 118 return 1; 119 } 120 break; 121 } 122 123 return 0; 124 } 125 126 void 127 piixpm_attach(struct device *parent, struct device *self, void *aux) 128 { 129 struct piixpm_softc *sc = (struct piixpm_softc *)self; 130 struct pci_attach_args *pa = aux; 131 struct i2cbus_attach_args iba; 132 pcireg_t base, conf; 133 #ifdef __HAVE_TIMECOUNTER 134 pcireg_t pmmisc; 135 #endif 136 pci_intr_handle_t ih; 137 char devinfo[256]; 138 const char *intrstr = NULL; 139 140 sc->sc_pc = pa->pa_pc; 141 sc->sc_pcitag = pa->pa_tag; 142 143 aprint_naive("\n"); 144 145 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 146 aprint_normal("\n%s: %s (rev. 0x%02x)\n", 147 device_xname(self), devinfo, PCI_REVISION(pa->pa_class)); 148 149 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 150 piixpm_powerhook, sc); 151 if (sc->sc_powerhook == NULL) 152 aprint_error("%s: can't establish powerhook\n", 153 sc->sc_dev.dv_xname); 154 155 /* Read configuration */ 156 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 157 DPRINTF((": conf 0x%x", conf)); 158 159 #ifdef __HAVE_TIMECOUNTER 160 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 161 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 162 goto nopowermanagement; 163 164 /* check whether I/O access to PM regs is enabled */ 165 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 166 if (!(pmmisc & 1)) 167 goto nopowermanagement; 168 169 sc->sc_pm_iot = pa->pa_iot; 170 /* Map I/O space */ 171 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 172 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 173 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 174 aprint_error("%s: can't map power management I/O space\n", 175 sc->sc_dev.dv_xname); 176 goto nopowermanagement; 177 } 178 179 /* 180 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 181 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 182 * in the "Specification update" (document #297738). 183 */ 184 acpipmtimer_attach(&sc->sc_dev, sc->sc_pm_iot, sc->sc_pm_ioh, 185 PIIX_PM_PMTMR, 186 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 187 188 nopowermanagement: 189 #endif 190 191 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 192 aprint_normal("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 193 return; 194 } 195 196 /* Map I/O space */ 197 sc->sc_smb_iot = pa->pa_iot; 198 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 199 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 200 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 201 aprint_error("%s: can't map smbus I/O space\n", 202 sc->sc_dev.dv_xname); 203 return; 204 } 205 206 sc->sc_poll = 1; 207 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 208 /* No PCI IRQ */ 209 aprint_normal("%s: interrupting at SMI", sc->sc_dev.dv_xname); 210 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 211 /* Install interrupt handler */ 212 if (pci_intr_map(pa, &ih) == 0) { 213 intrstr = pci_intr_string(pa->pa_pc, ih); 214 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 215 piixpm_intr, sc); 216 if (sc->sc_smb_ih != NULL) { 217 aprint_normal("%s: interrupting at %s", 218 sc->sc_dev.dv_xname, intrstr); 219 sc->sc_poll = 0; 220 } 221 } 222 if (sc->sc_poll) 223 aprint_normal("%s: polling", sc->sc_dev.dv_xname); 224 } 225 226 aprint_normal("\n"); 227 228 /* Attach I2C bus */ 229 lockinit(&sc->sc_i2c_lock, PRIBIO | PCATCH, "iiclk", 0, 0); 230 sc->sc_i2c_tag.ic_cookie = sc; 231 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 232 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 233 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 234 235 bzero(&iba, sizeof(iba)); 236 iba.iba_tag = &sc->sc_i2c_tag; 237 config_found_ia(self, "i2cbus", &iba, iicbus_print); 238 239 return; 240 } 241 242 void 243 piixpm_powerhook(int why, void *cookie) 244 { 245 struct piixpm_softc *sc = cookie; 246 pci_chipset_tag_t pc = sc->sc_pc; 247 pcitag_t tag = sc->sc_pcitag; 248 249 switch (why) { 250 case PWR_SUSPEND: 251 pci_conf_capture(pc, tag, &sc->sc_pciconf); 252 sc->sc_devact[0] = pci_conf_read(pc, tag, PIIX_DEVACTA); 253 sc->sc_devact[1] = pci_conf_read(pc, tag, PIIX_DEVACTB); 254 break; 255 case PWR_RESUME: 256 pci_conf_restore(pc, tag, &sc->sc_pciconf); 257 pci_conf_write(pc, tag, PIIX_DEVACTA, sc->sc_devact[0]); 258 pci_conf_write(pc, tag, PIIX_DEVACTB, sc->sc_devact[1]); 259 break; 260 } 261 262 return; 263 } 264 265 int 266 piixpm_i2c_acquire_bus(void *cookie, int flags) 267 { 268 struct piixpm_softc *sc = cookie; 269 270 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 271 return (0); 272 273 return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 274 } 275 276 void 277 piixpm_i2c_release_bus(void *cookie, int flags) 278 { 279 struct piixpm_softc *sc = cookie; 280 281 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 282 return; 283 284 lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 285 } 286 287 int 288 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 289 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 290 { 291 struct piixpm_softc *sc = cookie; 292 const u_int8_t *b; 293 u_int8_t ctl = 0, st; 294 int retries; 295 296 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %d, len %d, flags 0x%x\n", 297 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags)); 298 299 /* Wait for bus to be idle */ 300 for (retries = 100; retries > 0; retries--) { 301 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 302 PIIX_SMB_HS); 303 if (!(st & PIIX_SMB_HS_BUSY)) 304 break; 305 DELAY(PIIXPM_DELAY); 306 } 307 DPRINTF(("%s: exec: st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 308 if (st & PIIX_SMB_HS_BUSY) 309 return (1); 310 311 if (cold || sc->sc_poll) 312 flags |= I2C_F_POLL; 313 314 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 315 return (1); 316 317 /* Setup transfer */ 318 sc->sc_i2c_xfer.op = op; 319 sc->sc_i2c_xfer.buf = buf; 320 sc->sc_i2c_xfer.len = len; 321 sc->sc_i2c_xfer.flags = flags; 322 sc->sc_i2c_xfer.error = 0; 323 324 /* Set slave address and transfer direction */ 325 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 326 PIIX_SMB_TXSLVA_ADDR(addr) | 327 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 328 329 b = cmdbuf; 330 if (cmdlen > 0) 331 /* Set command byte */ 332 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 333 PIIX_SMB_HCMD, b[0]); 334 335 if (I2C_OP_WRITE_P(op)) { 336 /* Write data */ 337 b = buf; 338 if (len > 0) 339 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 340 PIIX_SMB_HD0, b[0]); 341 if (len > 1) 342 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 343 PIIX_SMB_HD1, b[1]); 344 } 345 346 /* Set SMBus command */ 347 if (len == 0) 348 ctl = PIIX_SMB_HC_CMD_BYTE; 349 else if (len == 1) 350 ctl = PIIX_SMB_HC_CMD_BDATA; 351 else if (len == 2) 352 ctl = PIIX_SMB_HC_CMD_WDATA; 353 354 if ((flags & I2C_F_POLL) == 0) 355 ctl |= PIIX_SMB_HC_INTREN; 356 357 /* Start transaction */ 358 ctl |= PIIX_SMB_HC_START; 359 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 360 361 if (flags & I2C_F_POLL) { 362 /* Poll for completion */ 363 DELAY(PIIXPM_DELAY); 364 for (retries = 1000; retries > 0; retries--) { 365 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 366 PIIX_SMB_HS); 367 if ((st & PIIX_SMB_HS_BUSY) == 0) 368 break; 369 DELAY(PIIXPM_DELAY); 370 } 371 if (st & PIIX_SMB_HS_BUSY) 372 goto timeout; 373 piixpm_intr(sc); 374 } else { 375 /* Wait for interrupt */ 376 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 377 goto timeout; 378 } 379 380 if (sc->sc_i2c_xfer.error) 381 return (1); 382 383 return (0); 384 385 timeout: 386 /* 387 * Transfer timeout. Kill the transaction and clear status bits. 388 */ 389 aprint_error("%s: timeout, status 0x%x\n", sc->sc_dev.dv_xname, st); 390 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 391 PIIX_SMB_HC_KILL); 392 DELAY(PIIXPM_DELAY); 393 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 394 if ((st & PIIX_SMB_HS_FAILED) == 0) 395 aprint_error("%s: transaction abort failed, status 0x%x\n", 396 sc->sc_dev.dv_xname, st); 397 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 398 return (1); 399 } 400 401 int 402 piixpm_intr(void *arg) 403 { 404 struct piixpm_softc *sc = arg; 405 u_int8_t st; 406 u_int8_t *b; 407 size_t len; 408 409 /* Read status */ 410 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 411 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 412 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 413 PIIX_SMB_HS_FAILED)) == 0) 414 /* Interrupt was not for us */ 415 return (0); 416 417 DPRINTF(("%s: intr st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 418 419 /* Clear status bits */ 420 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 421 422 /* Check for errors */ 423 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 424 PIIX_SMB_HS_FAILED)) { 425 sc->sc_i2c_xfer.error = 1; 426 goto done; 427 } 428 429 if (st & PIIX_SMB_HS_INTR) { 430 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 431 goto done; 432 433 /* Read data */ 434 b = sc->sc_i2c_xfer.buf; 435 len = sc->sc_i2c_xfer.len; 436 if (len > 0) 437 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 438 PIIX_SMB_HD0); 439 if (len > 1) 440 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 441 PIIX_SMB_HD1); 442 } 443 444 done: 445 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 446 wakeup(sc); 447 return (1); 448 } 449
Indexes created Mon Sep 29 21:09:56 GMT 2025