piixpm.c revision 1.14
1 /* $NetBSD: piixpm.c,v 1.14 2007/08/06 22:41:22 martin Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/device.h> 27 #include <sys/kernel.h> 28 #include <sys/lock.h> 29 #include <sys/proc.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcidevs.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 37 #include <dev/pci/piixpmreg.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #ifdef __HAVE_TIMECOUNTER 42 #include <dev/ic/acpipmtimer.h> 43 #endif 44 45 #ifdef PIIXPM_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define PIIXPM_DELAY 200 52 #define PIIXPM_TIMEOUT 1 53 54 struct piixpm_softc { 55 struct device sc_dev; 56 57 bus_space_tag_t sc_smb_iot; 58 bus_space_handle_t sc_smb_ioh; 59 void * sc_smb_ih; 60 int sc_poll; 61 62 bus_space_tag_t sc_pm_iot; 63 bus_space_handle_t sc_pm_ioh; 64 65 pci_chipset_tag_t sc_pc; 66 pcitag_t sc_pcitag; 67 68 struct i2c_controller sc_i2c_tag; 69 struct lock sc_i2c_lock; 70 struct { 71 i2c_op_t op; 72 void * buf; 73 size_t len; 74 int flags; 75 volatile int error; 76 } sc_i2c_xfer; 77 78 void * sc_powerhook; 79 struct pci_conf_state sc_pciconf; 80 pcireg_t sc_devact[2]; 81 }; 82 83 int piixpm_match(struct device *, struct cfdata *, void *); 84 void piixpm_attach(struct device *, struct device *, void *); 85 86 void piixpm_powerhook(int, void *); 87 88 int piixpm_i2c_acquire_bus(void *, int); 89 void piixpm_i2c_release_bus(void *, int); 90 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 91 void *, size_t, int); 92 93 int piixpm_intr(void *); 94 95 CFATTACH_DECL(piixpm, sizeof(struct piixpm_softc), 96 piixpm_match, piixpm_attach, NULL, NULL); 97 98 int 99 piixpm_match(struct device *parent, struct cfdata *match, 100 void *aux) 101 { 102 struct pci_attach_args *pa; 103 104 pa = (struct pci_attach_args *)aux; 105 switch (PCI_VENDOR(pa->pa_id)) { 106 case PCI_VENDOR_INTEL: 107 switch (PCI_PRODUCT(pa->pa_id)) { 108 case PCI_PRODUCT_INTEL_82371AB_PMC: 109 case PCI_PRODUCT_INTEL_82440MX_PMC: 110 return 1; 111 } 112 break; 113 case PCI_VENDOR_ATI: 114 switch (PCI_PRODUCT(pa->pa_id)) { 115 case PCI_PRODUCT_ATI_SB200_SMB: 116 case PCI_PRODUCT_ATI_SB300_SMB: 117 case PCI_PRODUCT_ATI_SB400_SMB: 118 return 1; 119 } 120 break; 121 case PCI_VENDOR_SERVERWORKS: 122 switch (PCI_PRODUCT(pa->pa_id)) { 123 case PCI_PRODUCT_SERVERWORKS_OSB4: 124 case PCI_PRODUCT_SERVERWORKS_CSB5: 125 case PCI_PRODUCT_SERVERWORKS_CSB6: 126 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 127 return 1; 128 } 129 } 130 131 return 0; 132 } 133 134 void 135 piixpm_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct piixpm_softc *sc = (struct piixpm_softc *)self; 138 struct pci_attach_args *pa = aux; 139 struct i2cbus_attach_args iba; 140 pcireg_t base, conf; 141 #ifdef __HAVE_TIMECOUNTER 142 pcireg_t pmmisc; 143 #endif 144 pci_intr_handle_t ih; 145 char devinfo[256]; 146 const char *intrstr = NULL; 147 148 sc->sc_pc = pa->pa_pc; 149 sc->sc_pcitag = pa->pa_tag; 150 151 aprint_naive("\n"); 152 153 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 154 aprint_normal("\n%s: %s (rev. 0x%02x)\n", 155 device_xname(self), devinfo, PCI_REVISION(pa->pa_class)); 156 157 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 158 piixpm_powerhook, sc); 159 if (sc->sc_powerhook == NULL) 160 aprint_error("%s: can't establish powerhook\n", 161 sc->sc_dev.dv_xname); 162 163 /* Read configuration */ 164 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 165 DPRINTF((": conf 0x%x", conf)); 166 167 #ifdef __HAVE_TIMECOUNTER 168 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 169 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 170 goto nopowermanagement; 171 172 /* check whether I/O access to PM regs is enabled */ 173 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 174 if (!(pmmisc & 1)) 175 goto nopowermanagement; 176 177 sc->sc_pm_iot = pa->pa_iot; 178 /* Map I/O space */ 179 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 180 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 181 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 182 aprint_error("%s: can't map power management I/O space\n", 183 sc->sc_dev.dv_xname); 184 goto nopowermanagement; 185 } 186 187 /* 188 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 189 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 190 * in the "Specification update" (document #297738). 191 */ 192 acpipmtimer_attach(&sc->sc_dev, sc->sc_pm_iot, sc->sc_pm_ioh, 193 PIIX_PM_PMTMR, 194 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 195 196 nopowermanagement: 197 #endif 198 199 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 200 aprint_normal("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 201 return; 202 } 203 204 /* Map I/O space */ 205 sc->sc_smb_iot = pa->pa_iot; 206 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 207 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 208 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 209 aprint_error("%s: can't map smbus I/O space\n", 210 sc->sc_dev.dv_xname); 211 return; 212 } 213 214 sc->sc_poll = 1; 215 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 216 /* No PCI IRQ */ 217 aprint_normal("%s: interrupting at SMI", sc->sc_dev.dv_xname); 218 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 219 /* Install interrupt handler */ 220 if (pci_intr_map(pa, &ih) == 0) { 221 intrstr = pci_intr_string(pa->pa_pc, ih); 222 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 223 piixpm_intr, sc); 224 if (sc->sc_smb_ih != NULL) { 225 aprint_normal("%s: interrupting at %s", 226 sc->sc_dev.dv_xname, intrstr); 227 sc->sc_poll = 0; 228 } 229 } 230 if (sc->sc_poll) 231 aprint_normal("%s: polling", sc->sc_dev.dv_xname); 232 } 233 234 aprint_normal("\n"); 235 236 /* Attach I2C bus */ 237 lockinit(&sc->sc_i2c_lock, PRIBIO | PCATCH, "iiclk", 0, 0); 238 sc->sc_i2c_tag.ic_cookie = sc; 239 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 240 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 241 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 242 243 bzero(&iba, sizeof(iba)); 244 iba.iba_tag = &sc->sc_i2c_tag; 245 config_found_ia(self, "i2cbus", &iba, iicbus_print); 246 247 return; 248 } 249 250 void 251 piixpm_powerhook(int why, void *cookie) 252 { 253 struct piixpm_softc *sc = cookie; 254 pci_chipset_tag_t pc = sc->sc_pc; 255 pcitag_t tag = sc->sc_pcitag; 256 257 switch (why) { 258 case PWR_SUSPEND: 259 pci_conf_capture(pc, tag, &sc->sc_pciconf); 260 sc->sc_devact[0] = pci_conf_read(pc, tag, PIIX_DEVACTA); 261 sc->sc_devact[1] = pci_conf_read(pc, tag, PIIX_DEVACTB); 262 break; 263 case PWR_RESUME: 264 pci_conf_restore(pc, tag, &sc->sc_pciconf); 265 pci_conf_write(pc, tag, PIIX_DEVACTA, sc->sc_devact[0]); 266 pci_conf_write(pc, tag, PIIX_DEVACTB, sc->sc_devact[1]); 267 break; 268 } 269 270 return; 271 } 272 273 int 274 piixpm_i2c_acquire_bus(void *cookie, int flags) 275 { 276 struct piixpm_softc *sc = cookie; 277 278 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 279 return (0); 280 281 return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 282 } 283 284 void 285 piixpm_i2c_release_bus(void *cookie, int flags) 286 { 287 struct piixpm_softc *sc = cookie; 288 289 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 290 return; 291 292 lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 293 } 294 295 int 296 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 297 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 298 { 299 struct piixpm_softc *sc = cookie; 300 const u_int8_t *b; 301 u_int8_t ctl = 0, st; 302 int retries; 303 304 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %d, len %d, flags 0x%x\n", 305 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags)); 306 307 /* Wait for bus to be idle */ 308 for (retries = 100; retries > 0; retries--) { 309 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 310 PIIX_SMB_HS); 311 if (!(st & PIIX_SMB_HS_BUSY)) 312 break; 313 DELAY(PIIXPM_DELAY); 314 } 315 DPRINTF(("%s: exec: st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 316 if (st & PIIX_SMB_HS_BUSY) 317 return (1); 318 319 if (cold || sc->sc_poll) 320 flags |= I2C_F_POLL; 321 322 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 323 return (1); 324 325 /* Setup transfer */ 326 sc->sc_i2c_xfer.op = op; 327 sc->sc_i2c_xfer.buf = buf; 328 sc->sc_i2c_xfer.len = len; 329 sc->sc_i2c_xfer.flags = flags; 330 sc->sc_i2c_xfer.error = 0; 331 332 /* Set slave address and transfer direction */ 333 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 334 PIIX_SMB_TXSLVA_ADDR(addr) | 335 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 336 337 b = cmdbuf; 338 if (cmdlen > 0) 339 /* Set command byte */ 340 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 341 PIIX_SMB_HCMD, b[0]); 342 343 if (I2C_OP_WRITE_P(op)) { 344 /* Write data */ 345 b = buf; 346 if (len > 0) 347 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 348 PIIX_SMB_HD0, b[0]); 349 if (len > 1) 350 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 351 PIIX_SMB_HD1, b[1]); 352 } 353 354 /* Set SMBus command */ 355 if (len == 0) 356 ctl = PIIX_SMB_HC_CMD_BYTE; 357 else if (len == 1) 358 ctl = PIIX_SMB_HC_CMD_BDATA; 359 else if (len == 2) 360 ctl = PIIX_SMB_HC_CMD_WDATA; 361 362 if ((flags & I2C_F_POLL) == 0) 363 ctl |= PIIX_SMB_HC_INTREN; 364 365 /* Start transaction */ 366 ctl |= PIIX_SMB_HC_START; 367 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 368 369 if (flags & I2C_F_POLL) { 370 /* Poll for completion */ 371 DELAY(PIIXPM_DELAY); 372 for (retries = 1000; retries > 0; retries--) { 373 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 374 PIIX_SMB_HS); 375 if ((st & PIIX_SMB_HS_BUSY) == 0) 376 break; 377 DELAY(PIIXPM_DELAY); 378 } 379 if (st & PIIX_SMB_HS_BUSY) 380 goto timeout; 381 piixpm_intr(sc); 382 } else { 383 /* Wait for interrupt */ 384 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 385 goto timeout; 386 } 387 388 if (sc->sc_i2c_xfer.error) 389 return (1); 390 391 return (0); 392 393 timeout: 394 /* 395 * Transfer timeout. Kill the transaction and clear status bits. 396 */ 397 aprint_error("%s: timeout, status 0x%x\n", sc->sc_dev.dv_xname, st); 398 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 399 PIIX_SMB_HC_KILL); 400 DELAY(PIIXPM_DELAY); 401 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 402 if ((st & PIIX_SMB_HS_FAILED) == 0) 403 aprint_error("%s: transaction abort failed, status 0x%x\n", 404 sc->sc_dev.dv_xname, st); 405 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 406 return (1); 407 } 408 409 int 410 piixpm_intr(void *arg) 411 { 412 struct piixpm_softc *sc = arg; 413 u_int8_t st; 414 u_int8_t *b; 415 size_t len; 416 417 /* Read status */ 418 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 419 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 420 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 421 PIIX_SMB_HS_FAILED)) == 0) 422 /* Interrupt was not for us */ 423 return (0); 424 425 DPRINTF(("%s: intr st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 426 427 /* Clear status bits */ 428 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 429 430 /* Check for errors */ 431 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 432 PIIX_SMB_HS_FAILED)) { 433 sc->sc_i2c_xfer.error = 1; 434 goto done; 435 } 436 437 if (st & PIIX_SMB_HS_INTR) { 438 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 439 goto done; 440 441 /* Read data */ 442 b = sc->sc_i2c_xfer.buf; 443 len = sc->sc_i2c_xfer.len; 444 if (len > 0) 445 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 446 PIIX_SMB_HD0); 447 if (len > 1) 448 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 449 PIIX_SMB_HD1); 450 } 451 452 done: 453 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 454 wakeup(sc); 455 return (1); 456 } 457
Indexes created Mon Sep 29 21:09:56 GMT 2025