piixpm.c revision 1.18
1 /* $NetBSD: piixpm.c,v 1.18 2007/12/09 20:28:13 jmcneill Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/device.h> 27 #include <sys/kernel.h> 28 #include <sys/rwlock.h> 29 #include <sys/proc.h> 30 31 #include <sys/bus.h> 32 33 #include <dev/pci/pcidevs.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 37 #include <dev/pci/piixpmreg.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #include <dev/ic/acpipmtimer.h> 42 43 #ifdef PIIXPM_DEBUG 44 #define DPRINTF(x) printf x 45 #else 46 #define DPRINTF(x) 47 #endif 48 49 #define PIIXPM_DELAY 200 50 #define PIIXPM_TIMEOUT 1 51 52 struct piixpm_softc { 53 struct device sc_dev; 54 55 bus_space_tag_t sc_smb_iot; 56 bus_space_handle_t sc_smb_ioh; 57 void * sc_smb_ih; 58 int sc_poll; 59 60 bus_space_tag_t sc_pm_iot; 61 bus_space_handle_t sc_pm_ioh; 62 63 pci_chipset_tag_t sc_pc; 64 pcitag_t sc_pcitag; 65 66 struct i2c_controller sc_i2c_tag; 67 krwlock_t sc_i2c_rwlock; 68 struct { 69 i2c_op_t op; 70 void * buf; 71 size_t len; 72 int flags; 73 volatile int error; 74 } sc_i2c_xfer; 75 76 pcireg_t sc_devact[2]; 77 }; 78 79 int piixpm_match(struct device *, struct cfdata *, void *); 80 void piixpm_attach(struct device *, struct device *, void *); 81 82 static bool piixpm_suspend(device_t); 83 static bool piixpm_resume(device_t); 84 85 int piixpm_i2c_acquire_bus(void *, int); 86 void piixpm_i2c_release_bus(void *, int); 87 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 88 void *, size_t, int); 89 90 int piixpm_intr(void *); 91 92 CFATTACH_DECL(piixpm, sizeof(struct piixpm_softc), 93 piixpm_match, piixpm_attach, NULL, NULL); 94 95 int 96 piixpm_match(struct device *parent, struct cfdata *match, 97 void *aux) 98 { 99 struct pci_attach_args *pa; 100 101 pa = (struct pci_attach_args *)aux; 102 switch (PCI_VENDOR(pa->pa_id)) { 103 case PCI_VENDOR_INTEL: 104 switch (PCI_PRODUCT(pa->pa_id)) { 105 case PCI_PRODUCT_INTEL_82371AB_PMC: 106 case PCI_PRODUCT_INTEL_82440MX_PMC: 107 return 1; 108 } 109 break; 110 case PCI_VENDOR_ATI: 111 switch (PCI_PRODUCT(pa->pa_id)) { 112 case PCI_PRODUCT_ATI_SB200_SMB: 113 case PCI_PRODUCT_ATI_SB300_SMB: 114 case PCI_PRODUCT_ATI_SB400_SMB: 115 return 1; 116 } 117 break; 118 case PCI_VENDOR_SERVERWORKS: 119 switch (PCI_PRODUCT(pa->pa_id)) { 120 case PCI_PRODUCT_SERVERWORKS_OSB4: 121 case PCI_PRODUCT_SERVERWORKS_CSB5: 122 case PCI_PRODUCT_SERVERWORKS_CSB6: 123 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 124 return 1; 125 } 126 } 127 128 return 0; 129 } 130 131 void 132 piixpm_attach(struct device *parent, struct device *self, void *aux) 133 { 134 struct piixpm_softc *sc = (struct piixpm_softc *)self; 135 struct pci_attach_args *pa = aux; 136 struct i2cbus_attach_args iba; 137 pcireg_t base, conf; 138 pcireg_t pmmisc; 139 pci_intr_handle_t ih; 140 char devinfo[256]; 141 const char *intrstr = NULL; 142 143 sc->sc_pc = pa->pa_pc; 144 sc->sc_pcitag = pa->pa_tag; 145 146 aprint_naive("\n"); 147 148 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 149 aprint_normal("\n%s: %s (rev. 0x%02x)\n", 150 device_xname(self), devinfo, PCI_REVISION(pa->pa_class)); 151 152 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 153 aprint_error_dev(self, "couldn't establish power handler\n"); 154 155 /* Read configuration */ 156 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 157 DPRINTF((": conf 0x%x", conf)); 158 159 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 160 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 161 goto nopowermanagement; 162 163 /* check whether I/O access to PM regs is enabled */ 164 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 165 if (!(pmmisc & 1)) 166 goto nopowermanagement; 167 168 sc->sc_pm_iot = pa->pa_iot; 169 /* Map I/O space */ 170 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 171 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 172 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 173 aprint_error("%s: can't map power management I/O space\n", 174 sc->sc_dev.dv_xname); 175 goto nopowermanagement; 176 } 177 178 /* 179 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 180 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 181 * in the "Specification update" (document #297738). 182 */ 183 acpipmtimer_attach(&sc->sc_dev, sc->sc_pm_iot, sc->sc_pm_ioh, 184 PIIX_PM_PMTMR, 185 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 186 187 nopowermanagement: 188 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 189 aprint_normal("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 190 return; 191 } 192 193 /* Map I/O space */ 194 sc->sc_smb_iot = pa->pa_iot; 195 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 196 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 197 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 198 aprint_error("%s: can't map smbus I/O space\n", 199 sc->sc_dev.dv_xname); 200 return; 201 } 202 203 sc->sc_poll = 1; 204 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 205 /* No PCI IRQ */ 206 aprint_normal("%s: interrupting at SMI", sc->sc_dev.dv_xname); 207 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 208 /* Install interrupt handler */ 209 if (pci_intr_map(pa, &ih) == 0) { 210 intrstr = pci_intr_string(pa->pa_pc, ih); 211 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 212 piixpm_intr, sc); 213 if (sc->sc_smb_ih != NULL) { 214 aprint_normal("%s: interrupting at %s", 215 sc->sc_dev.dv_xname, intrstr); 216 sc->sc_poll = 0; 217 } 218 } 219 if (sc->sc_poll) 220 aprint_normal("%s: polling", sc->sc_dev.dv_xname); 221 } 222 223 aprint_normal("\n"); 224 225 /* Attach I2C bus */ 226 rw_init(&sc->sc_i2c_rwlock); 227 sc->sc_i2c_tag.ic_cookie = sc; 228 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 229 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 230 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 231 232 bzero(&iba, sizeof(iba)); 233 iba.iba_tag = &sc->sc_i2c_tag; 234 config_found_ia(self, "i2cbus", &iba, iicbus_print); 235 236 return; 237 } 238 239 static bool 240 piixpm_suspend(device_t dv) 241 { 242 struct piixpm_softc *sc = device_private(dv); 243 244 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 245 PIIX_DEVACTA); 246 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 247 PIIX_DEVACTB); 248 249 return true; 250 } 251 252 static bool 253 piixpm_resume(device_t dv) 254 { 255 struct piixpm_softc *sc = device_private(dv); 256 257 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 258 sc->sc_devact[0]); 259 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 260 sc->sc_devact[1]); 261 262 return true; 263 } 264 265 int 266 piixpm_i2c_acquire_bus(void *cookie, int flags) 267 { 268 struct piixpm_softc *sc = cookie; 269 270 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 271 return (0); 272 273 rw_enter(&sc->sc_i2c_rwlock, RW_WRITER); 274 return 0; 275 } 276 277 void 278 piixpm_i2c_release_bus(void *cookie, int flags) 279 { 280 struct piixpm_softc *sc = cookie; 281 282 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 283 return; 284 285 rw_exit(&sc->sc_i2c_rwlock); 286 } 287 288 int 289 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 290 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 291 { 292 struct piixpm_softc *sc = cookie; 293 const u_int8_t *b; 294 u_int8_t ctl = 0, st; 295 int retries; 296 297 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %d, len %d, flags 0x%x\n", 298 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags)); 299 300 /* Wait for bus to be idle */ 301 for (retries = 100; retries > 0; retries--) { 302 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 303 PIIX_SMB_HS); 304 if (!(st & PIIX_SMB_HS_BUSY)) 305 break; 306 DELAY(PIIXPM_DELAY); 307 } 308 DPRINTF(("%s: exec: st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 309 if (st & PIIX_SMB_HS_BUSY) 310 return (1); 311 312 if (cold || sc->sc_poll) 313 flags |= I2C_F_POLL; 314 315 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 316 return (1); 317 318 /* Setup transfer */ 319 sc->sc_i2c_xfer.op = op; 320 sc->sc_i2c_xfer.buf = buf; 321 sc->sc_i2c_xfer.len = len; 322 sc->sc_i2c_xfer.flags = flags; 323 sc->sc_i2c_xfer.error = 0; 324 325 /* Set slave address and transfer direction */ 326 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 327 PIIX_SMB_TXSLVA_ADDR(addr) | 328 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 329 330 b = cmdbuf; 331 if (cmdlen > 0) 332 /* Set command byte */ 333 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 334 PIIX_SMB_HCMD, b[0]); 335 336 if (I2C_OP_WRITE_P(op)) { 337 /* Write data */ 338 b = buf; 339 if (len > 0) 340 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 341 PIIX_SMB_HD0, b[0]); 342 if (len > 1) 343 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 344 PIIX_SMB_HD1, b[1]); 345 } 346 347 /* Set SMBus command */ 348 if (len == 0) 349 ctl = PIIX_SMB_HC_CMD_BYTE; 350 else if (len == 1) 351 ctl = PIIX_SMB_HC_CMD_BDATA; 352 else if (len == 2) 353 ctl = PIIX_SMB_HC_CMD_WDATA; 354 355 if ((flags & I2C_F_POLL) == 0) 356 ctl |= PIIX_SMB_HC_INTREN; 357 358 /* Start transaction */ 359 ctl |= PIIX_SMB_HC_START; 360 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 361 362 if (flags & I2C_F_POLL) { 363 /* Poll for completion */ 364 DELAY(PIIXPM_DELAY); 365 for (retries = 1000; retries > 0; retries--) { 366 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 367 PIIX_SMB_HS); 368 if ((st & PIIX_SMB_HS_BUSY) == 0) 369 break; 370 DELAY(PIIXPM_DELAY); 371 } 372 if (st & PIIX_SMB_HS_BUSY) 373 goto timeout; 374 piixpm_intr(sc); 375 } else { 376 /* Wait for interrupt */ 377 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 378 goto timeout; 379 } 380 381 if (sc->sc_i2c_xfer.error) 382 return (1); 383 384 return (0); 385 386 timeout: 387 /* 388 * Transfer timeout. Kill the transaction and clear status bits. 389 */ 390 aprint_error("%s: timeout, status 0x%x\n", sc->sc_dev.dv_xname, st); 391 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 392 PIIX_SMB_HC_KILL); 393 DELAY(PIIXPM_DELAY); 394 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 395 if ((st & PIIX_SMB_HS_FAILED) == 0) 396 aprint_error("%s: transaction abort failed, status 0x%x\n", 397 sc->sc_dev.dv_xname, st); 398 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 399 return (1); 400 } 401 402 int 403 piixpm_intr(void *arg) 404 { 405 struct piixpm_softc *sc = arg; 406 u_int8_t st; 407 u_int8_t *b; 408 size_t len; 409 410 /* Read status */ 411 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 412 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 413 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 414 PIIX_SMB_HS_FAILED)) == 0) 415 /* Interrupt was not for us */ 416 return (0); 417 418 DPRINTF(("%s: intr st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 419 420 /* Clear status bits */ 421 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 422 423 /* Check for errors */ 424 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 425 PIIX_SMB_HS_FAILED)) { 426 sc->sc_i2c_xfer.error = 1; 427 goto done; 428 } 429 430 if (st & PIIX_SMB_HS_INTR) { 431 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 432 goto done; 433 434 /* Read data */ 435 b = sc->sc_i2c_xfer.buf; 436 len = sc->sc_i2c_xfer.len; 437 if (len > 0) 438 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 439 PIIX_SMB_HD0); 440 if (len > 1) 441 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 442 PIIX_SMB_HD1); 443 } 444 445 done: 446 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 447 wakeup(sc); 448 return (1); 449 } 450
Indexes created Mon Sep 29 21:09:56 GMT 2025