piixpm.c revision 1.24
1 /* $NetBSD: piixpm.c,v 1.24 2008/04/10 19:13:37 cegger Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.24 2008/04/10 19:13:37 cegger Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/rwlock.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_DELAY 200 53 #define PIIXPM_TIMEOUT 1 54 55 struct piixpm_softc { 56 struct device sc_dev; 57 58 bus_space_tag_t sc_smb_iot; 59 bus_space_handle_t sc_smb_ioh; 60 void * sc_smb_ih; 61 int sc_poll; 62 63 bus_space_tag_t sc_pm_iot; 64 bus_space_handle_t sc_pm_ioh; 65 66 pci_chipset_tag_t sc_pc; 67 pcitag_t sc_pcitag; 68 69 struct i2c_controller sc_i2c_tag; 70 krwlock_t sc_i2c_rwlock; 71 struct { 72 i2c_op_t op; 73 void * buf; 74 size_t len; 75 int flags; 76 volatile int error; 77 } sc_i2c_xfer; 78 79 pcireg_t sc_devact[2]; 80 }; 81 82 int piixpm_match(struct device *, struct cfdata *, void *); 83 void piixpm_attach(struct device *, struct device *, void *); 84 85 static bool piixpm_suspend(device_t PMF_FN_PROTO); 86 static bool piixpm_resume(device_t PMF_FN_PROTO); 87 88 int piixpm_i2c_acquire_bus(void *, int); 89 void piixpm_i2c_release_bus(void *, int); 90 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 91 void *, size_t, int); 92 93 int piixpm_intr(void *); 94 95 CFATTACH_DECL(piixpm, sizeof(struct piixpm_softc), 96 piixpm_match, piixpm_attach, NULL, NULL); 97 98 int 99 piixpm_match(struct device *parent, struct cfdata *match, 100 void *aux) 101 { 102 struct pci_attach_args *pa; 103 104 pa = (struct pci_attach_args *)aux; 105 switch (PCI_VENDOR(pa->pa_id)) { 106 case PCI_VENDOR_INTEL: 107 switch (PCI_PRODUCT(pa->pa_id)) { 108 case PCI_PRODUCT_INTEL_82371AB_PMC: 109 case PCI_PRODUCT_INTEL_82440MX_PMC: 110 return 1; 111 } 112 break; 113 case PCI_VENDOR_ATI: 114 switch (PCI_PRODUCT(pa->pa_id)) { 115 case PCI_PRODUCT_ATI_SB200_SMB: 116 case PCI_PRODUCT_ATI_SB300_SMB: 117 case PCI_PRODUCT_ATI_SB400_SMB: 118 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 119 return 1; 120 } 121 break; 122 case PCI_VENDOR_SERVERWORKS: 123 switch (PCI_PRODUCT(pa->pa_id)) { 124 case PCI_PRODUCT_SERVERWORKS_OSB4: 125 case PCI_PRODUCT_SERVERWORKS_CSB5: 126 case PCI_PRODUCT_SERVERWORKS_CSB6: 127 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 128 return 1; 129 } 130 } 131 132 return 0; 133 } 134 135 void 136 piixpm_attach(struct device *parent, struct device *self, void *aux) 137 { 138 struct piixpm_softc *sc = (struct piixpm_softc *)self; 139 struct pci_attach_args *pa = aux; 140 struct i2cbus_attach_args iba; 141 pcireg_t base, conf; 142 pcireg_t pmmisc; 143 pci_intr_handle_t ih; 144 char devinfo[256]; 145 const char *intrstr = NULL; 146 147 sc->sc_pc = pa->pa_pc; 148 sc->sc_pcitag = pa->pa_tag; 149 150 aprint_naive("\n"); 151 152 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 153 aprint_normal("\n%s: %s (rev. 0x%02x)\n", 154 device_xname(self), devinfo, PCI_REVISION(pa->pa_class)); 155 156 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 157 aprint_error_dev(self, "couldn't establish power handler\n"); 158 159 /* Read configuration */ 160 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 161 DPRINTF(("%s: conf 0x%x\n", device_xname(&sc->sc_dev), conf)); 162 163 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 164 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 165 goto nopowermanagement; 166 167 /* check whether I/O access to PM regs is enabled */ 168 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 169 if (!(pmmisc & 1)) 170 goto nopowermanagement; 171 172 sc->sc_pm_iot = pa->pa_iot; 173 /* Map I/O space */ 174 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 175 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 176 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 177 aprint_error_dev(&sc->sc_dev, "can't map power management I/O space\n"); 178 goto nopowermanagement; 179 } 180 181 /* 182 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 183 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 184 * in the "Specification update" (document #297738). 185 */ 186 acpipmtimer_attach(&sc->sc_dev, sc->sc_pm_iot, sc->sc_pm_ioh, 187 PIIX_PM_PMTMR, 188 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 189 190 nopowermanagement: 191 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 192 aprint_normal_dev(&sc->sc_dev, "SMBus disabled\n"); 193 return; 194 } 195 196 /* Map I/O space */ 197 sc->sc_smb_iot = pa->pa_iot; 198 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 199 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 200 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 201 aprint_error_dev(&sc->sc_dev, "can't map smbus I/O space\n"); 202 return; 203 } 204 205 sc->sc_poll = 1; 206 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 207 /* No PCI IRQ */ 208 aprint_normal_dev(&sc->sc_dev, "interrupting at SMI"); 209 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 210 /* Install interrupt handler */ 211 if (pci_intr_map(pa, &ih) == 0) { 212 intrstr = pci_intr_string(pa->pa_pc, ih); 213 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 214 piixpm_intr, sc); 215 if (sc->sc_smb_ih != NULL) { 216 aprint_normal_dev(&sc->sc_dev, "interrupting at %s", 217 intrstr); 218 sc->sc_poll = 0; 219 } 220 } 221 if (sc->sc_poll) 222 aprint_normal_dev(&sc->sc_dev, "polling"); 223 } 224 225 aprint_normal("\n"); 226 227 /* Attach I2C bus */ 228 rw_init(&sc->sc_i2c_rwlock); 229 sc->sc_i2c_tag.ic_cookie = sc; 230 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 231 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 232 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 233 234 bzero(&iba, sizeof(iba)); 235 iba.iba_tag = &sc->sc_i2c_tag; 236 config_found_ia(self, "i2cbus", &iba, iicbus_print); 237 238 return; 239 } 240 241 static bool 242 piixpm_suspend(device_t dv PMF_FN_ARGS) 243 { 244 struct piixpm_softc *sc = device_private(dv); 245 246 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 247 PIIX_DEVACTA); 248 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 249 PIIX_DEVACTB); 250 251 return true; 252 } 253 254 static bool 255 piixpm_resume(device_t dv PMF_FN_ARGS) 256 { 257 struct piixpm_softc *sc = device_private(dv); 258 259 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 260 sc->sc_devact[0]); 261 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 262 sc->sc_devact[1]); 263 264 return true; 265 } 266 267 int 268 piixpm_i2c_acquire_bus(void *cookie, int flags) 269 { 270 struct piixpm_softc *sc = cookie; 271 272 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 273 return (0); 274 275 rw_enter(&sc->sc_i2c_rwlock, RW_WRITER); 276 return 0; 277 } 278 279 void 280 piixpm_i2c_release_bus(void *cookie, int flags) 281 { 282 struct piixpm_softc *sc = cookie; 283 284 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 285 return; 286 287 rw_exit(&sc->sc_i2c_rwlock); 288 } 289 290 int 291 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 292 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 293 { 294 struct piixpm_softc *sc = cookie; 295 const u_int8_t *b; 296 u_int8_t ctl = 0, st; 297 int retries; 298 299 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %d, len %d, flags 0x%x\n", 300 device_xname(&sc->sc_dev), op, addr, cmdlen, len, flags)); 301 302 /* Wait for bus to be idle */ 303 for (retries = 100; retries > 0; retries--) { 304 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 305 PIIX_SMB_HS); 306 if (!(st & PIIX_SMB_HS_BUSY)) 307 break; 308 DELAY(PIIXPM_DELAY); 309 } 310 DPRINTF(("%s: exec: st 0x%d\n", device_xname(&sc->sc_dev), st & 0xff)); 311 if (st & PIIX_SMB_HS_BUSY) 312 return (1); 313 314 if (cold || sc->sc_poll) 315 flags |= I2C_F_POLL; 316 317 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 318 return (1); 319 320 /* Setup transfer */ 321 sc->sc_i2c_xfer.op = op; 322 sc->sc_i2c_xfer.buf = buf; 323 sc->sc_i2c_xfer.len = len; 324 sc->sc_i2c_xfer.flags = flags; 325 sc->sc_i2c_xfer.error = 0; 326 327 /* Set slave address and transfer direction */ 328 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 329 PIIX_SMB_TXSLVA_ADDR(addr) | 330 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 331 332 b = cmdbuf; 333 if (cmdlen > 0) 334 /* Set command byte */ 335 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 336 PIIX_SMB_HCMD, b[0]); 337 338 if (I2C_OP_WRITE_P(op)) { 339 /* Write data */ 340 b = buf; 341 if (len > 0) 342 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 343 PIIX_SMB_HD0, b[0]); 344 if (len > 1) 345 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 346 PIIX_SMB_HD1, b[1]); 347 } 348 349 /* Set SMBus command */ 350 if (len == 0) 351 ctl = PIIX_SMB_HC_CMD_BYTE; 352 else if (len == 1) 353 ctl = PIIX_SMB_HC_CMD_BDATA; 354 else if (len == 2) 355 ctl = PIIX_SMB_HC_CMD_WDATA; 356 357 if ((flags & I2C_F_POLL) == 0) 358 ctl |= PIIX_SMB_HC_INTREN; 359 360 /* Start transaction */ 361 ctl |= PIIX_SMB_HC_START; 362 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 363 364 if (flags & I2C_F_POLL) { 365 /* Poll for completion */ 366 DELAY(PIIXPM_DELAY); 367 for (retries = 1000; retries > 0; retries--) { 368 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 369 PIIX_SMB_HS); 370 if ((st & PIIX_SMB_HS_BUSY) == 0) 371 break; 372 DELAY(PIIXPM_DELAY); 373 } 374 if (st & PIIX_SMB_HS_BUSY) 375 goto timeout; 376 piixpm_intr(sc); 377 } else { 378 /* Wait for interrupt */ 379 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 380 goto timeout; 381 } 382 383 if (sc->sc_i2c_xfer.error) 384 return (1); 385 386 return (0); 387 388 timeout: 389 /* 390 * Transfer timeout. Kill the transaction and clear status bits. 391 */ 392 aprint_error_dev(&sc->sc_dev, "timeout, status 0x%x\n", st); 393 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 394 PIIX_SMB_HC_KILL); 395 DELAY(PIIXPM_DELAY); 396 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 397 if ((st & PIIX_SMB_HS_FAILED) == 0) 398 aprint_error_dev(&sc->sc_dev, "transaction abort failed, status 0x%x\n", st); 399 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 400 return (1); 401 } 402 403 int 404 piixpm_intr(void *arg) 405 { 406 struct piixpm_softc *sc = arg; 407 u_int8_t st; 408 u_int8_t *b; 409 size_t len; 410 411 /* Read status */ 412 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 413 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 414 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 415 PIIX_SMB_HS_FAILED)) == 0) 416 /* Interrupt was not for us */ 417 return (0); 418 419 DPRINTF(("%s: intr st 0x%d\n", device_xname(&sc->sc_dev), st & 0xff)); 420 421 /* Clear status bits */ 422 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 423 424 /* Check for errors */ 425 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 426 PIIX_SMB_HS_FAILED)) { 427 sc->sc_i2c_xfer.error = 1; 428 goto done; 429 } 430 431 if (st & PIIX_SMB_HS_INTR) { 432 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 433 goto done; 434 435 /* Read data */ 436 b = sc->sc_i2c_xfer.buf; 437 len = sc->sc_i2c_xfer.len; 438 if (len > 0) 439 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 440 PIIX_SMB_HD0); 441 if (len > 1) 442 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 443 PIIX_SMB_HD1); 444 } 445 446 done: 447 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 448 wakeup(sc); 449 return (1); 450 } 451
Indexes created Mon Sep 29 21:09:56 GMT 2025